Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 Analog Devices, Inc.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_
       9              : 
      10            0 : #define MAX32_DMA_SLOT_MEMTOMEM  0x00U
      11            0 : #define MAX32_DMA_SLOT_SPI0_RX   0x01U
      12            0 : #define MAX32_DMA_SLOT_SPI1_RX   0x02U
      13            0 : #define MAX32_DMA_SLOT_UART0_RX  0x04U
      14            0 : #define MAX32_DMA_SLOT_UART1_RX  0x05U
      15            0 : #define MAX32_DMA_SLOT_I2C0_RX   0x07U
      16            0 : #define MAX32_DMA_SLOT_I2C1_RX   0x08U
      17            0 : #define MAX32_DMA_SLOT_SPI0_TX   0x21U
      18            0 : #define MAX32_DMA_SLOT_SPI1_TX   0x22U
      19            0 : #define MAX32_DMA_SLOT_UART0_TX  0x24U
      20            0 : #define MAX32_DMA_SLOT_UART1_TX  0x25U
      21            0 : #define MAX32_DMA_SLOT_I2C0_TX   0x27U
      22            0 : #define MAX32_DMA_SLOT_I2C1_TX   0x28U
      23              : 
      24              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_ */