Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2024 Analog Devices, Inc.
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_
       8             : #define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_
       9             : 
      10           0 : #define MAX32_DMA_SLOT_MEMTOMEM  0x00U
      11           0 : #define MAX32_DMA_SLOT_SPI0_RX   0x01U
      12           0 : #define MAX32_DMA_SLOT_SPI1_RX   0x02U
      13           0 : #define MAX32_DMA_SLOT_UART0_RX  0x04U
      14           0 : #define MAX32_DMA_SLOT_UART1_RX  0x05U
      15           0 : #define MAX32_DMA_SLOT_CAN_RX    0x06U
      16           0 : #define MAX32_DMA_SLOT_I2C0_RX   0x07U
      17           0 : #define MAX32_DMA_SLOT_I2C1_RX   0x08U
      18           0 : #define MAX32_DMA_SLOT_ADC       0x09U
      19           0 : #define MAX32_DMA_SLOT_I2S_RX    0x1EU
      20           0 : #define MAX32_DMA_SLOT_SPI0_TX   0x21U
      21           0 : #define MAX32_DMA_SLOT_SPI1_TX   0x22U
      22           0 : #define MAX32_DMA_SLOT_UART0_TX  0x24U
      23           0 : #define MAX32_DMA_SLOT_UART1_TX  0x25U
      24           0 : #define MAX32_DMA_SLOT_CAN_TX    0x26U
      25           0 : #define MAX32_DMA_SLOT_I2C0_TX   0x27U
      26           0 : #define MAX32_DMA_SLOT_I2C1_TX   0x28U
      27           0 : #define MAX32_DMA_SLOT_I2S_TX    0x3EU
      28             : 
      29             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_ */