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1 0 : /*
2 : * Copyright (c) 2024 Analog Devices, Inc.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32672_DMA_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32672_DMA_H_
9 :
10 0 : #define MAX32_DMA_SLOT_MEMTOMEM 0x00U
11 0 : #define MAX32_DMA_SLOT_SPI0_RX 0x01U
12 0 : #define MAX32_DMA_SLOT_SPI1_RX 0x02U
13 0 : #define MAX32_DMA_SLOT_SPI2_RX 0x03U
14 0 : #define MAX32_DMA_SLOT_UART0_RX 0x04U
15 0 : #define MAX32_DMA_SLOT_UART1_RX 0x05U
16 0 : #define MAX32_DMA_SLOT_I2C0_RX 0x07U
17 0 : #define MAX32_DMA_SLOT_I2C1_RX 0x08U
18 0 : #define MAX32_DMA_SLOT_ADC 0x09U
19 0 : #define MAX32_DMA_SLOT_I2C2_RX 0x0AU
20 0 : #define MAX32_DMA_SLOT_UART2_RX 0x0EU
21 0 : #define MAX32_DMA_SLOT_AES_RX 0x10U
22 0 : #define MAX32_DMA_SLOT_UART3_RX 0x1CU
23 0 : #define MAX32_DMA_SLOT_I2S_RX 0x1EU
24 0 : #define MAX32_DMA_SLOT_SPI0_TX 0x21U
25 0 : #define MAX32_DMA_SLOT_SPI1_TX 0x22U
26 0 : #define MAX32_DMA_SLOT_SPI2_TX 0x23U
27 0 : #define MAX32_DMA_SLOT_UART0_TX 0x24U
28 0 : #define MAX32_DMA_SLOT_UART1_TX 0x25U
29 0 : #define MAX32_DMA_SLOT_I2C0_TX 0x27U
30 0 : #define MAX32_DMA_SLOT_I2C1_TX 0x28U
31 0 : #define MAX32_DMA_SLOT_I2C2_TX 0x2AU
32 0 : #define MAX32_DMA_SLOT_CRC 0x2CU
33 0 : #define MAX32_DMA_SLOT_UART2_TX 0x2EU
34 0 : #define MAX32_DMA_SLOT_AES_TX 0x30U
35 0 : #define MAX32_DMA_SLOT_UART3_TX 0x3CU
36 0 : #define MAX32_DMA_SLOT_I2S_TX 0x3EU
37 :
38 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32672_DMA_H_ */
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