Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2021-2022, Weidmueller Interface GmbH & Co. KG
       3             :  * SPDX-License-Identifier: Apache-2.0
       4             :  */
       5             : 
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_
       8             : 
       9             : /* PHY auto-detection alias */
      10           0 : #define XLNX_GEM_PHY_AUTO_DETECT 0
      11             : 
      12             : /*
      13             :  * MDC divider values
      14             :  *
      15             :  * According to the ZynqMP's gem.network_config register documentation (UG1087),
      16             :  * divider /32 is the reset value. The network_config[mdc_clock_division]
      17             :  * documentation in UG1087 is likely wrong (copied directly from the Zynq-7000),
      18             :  * as it claims that the MDC clock division is applied to the cpu_1x clock
      19             :  * which the UltraScale doesn't have. Contradicting information is provided in
      20             :  * the UltraScale TRM (UG1085), which mentions in chapter 34, section "Configure
      21             :  * the PHY", p. 1074, that the MDC clock division is applied to the IOU_SWITCH_CLK.
      22             :  * Xilinx's emacps driver doesn't (or no longer does) limit the range of dividers
      23             :  * on the UltraScale compared to the Zynq-7000.
      24             :  * -> Contrary to earlier revisions of this driver, all dividers are available
      25             :  *    to both the UltraScale and the Zynq-7000.
      26             :  */
      27             : 
      28           0 : #define XLNX_GEM_MDC_DIVIDER_8   0 /* cpu_1x or IOU_SWITCH_CLK     <  20 MHz */
      29           0 : #define XLNX_GEM_MDC_DIVIDER_16  1 /* cpu_1x or IOU_SWITCH_CLK  20 -  40 MHz */
      30           0 : #define XLNX_GEM_MDC_DIVIDER_32  2 /* cpu_1x or IOU_SWITCH_CLK  40 -  80 MHz */
      31           0 : #define XLNX_GEM_MDC_DIVIDER_48  3 /* cpu_1x or IOU_SWITCH_CLK  80 - 120 MHz */
      32           0 : #define XLNX_GEM_MDC_DIVIDER_64  4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
      33           0 : #define XLNX_GEM_MDC_DIVIDER_96  5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
      34           0 : #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
      35           0 : #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
      36             : 
      37             : /* Link speed values */
      38           0 : #define XLNX_GEM_LINK_SPEED_10MBIT  1
      39           0 : #define XLNX_GEM_LINK_SPEED_100MBIT 2
      40           0 : #define XLNX_GEM_LINK_SPEED_1GBIT   3
      41             : 
      42             : /* AMBA AHB data bus width */
      43           0 : #define XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT  0
      44           0 : #define XLNX_GEM_AMBA_AHB_DBUS_WIDTH_64BIT  1
      45           0 : #define XLNX_GEM_AMBA_AHB_DBUS_WIDTH_128BIT 2
      46             : 
      47             : /* AMBA AHB burst length */
      48           0 : #define XLNX_GEM_AMBA_AHB_BURST_SINGLE 1
      49           0 : #define XLNX_GEM_AMBA_AHB_BURST_INCR4  4
      50           0 : #define XLNX_GEM_AMBA_AHB_BURST_INCR8  8
      51           0 : #define XLNX_GEM_AMBA_AHB_BURST_INCR16 16
      52             : 
      53             : /* Hardware RX buffer size */
      54           0 : #define XLNX_GEM_HW_RX_BUFFER_SIZE_1KB 0
      55           0 : #define XLNX_GEM_HW_RX_BUFFER_SIZE_2KB 1
      56           0 : #define XLNX_GEM_HW_RX_BUFFER_SIZE_4KB 2
      57           0 : #define XLNX_GEM_HW_RX_BUFFER_SIZE_8KB 3
      58             : 
      59             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_XLNX_GEM_H_ */