Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2023 Nuvoton Technology Corporation.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_NPCX_FIU_QSPI_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_NPCX_FIU_QSPI_H_
       8              : 
       9              : #include <zephyr/dt-bindings/dt-util.h>
      10              : 
      11              : /* Software controlled Chip-Select number for UMA transactions */
      12            0 : #define NPCX_QSPI_SW_CS0        BIT(0)
      13            0 : #define NPCX_QSPI_SW_CS1        BIT(1)
      14            0 : #define NPCX_QSPI_SW_CS2        BIT(2)
      15            0 : #define NPCX_QSPI_SW_CS_MASK    (NPCX_QSPI_SW_CS0 | NPCX_QSPI_SW_CS1 | NPCX_QSPI_SW_CS2)
      16              : 
      17              : /* Supported flash interfaces for UMA transactions */
      18            0 : #define NPCX_QSPI_SEC_FLASH_SL  BIT(4)
      19            0 : #define NPCX_QSPI_PVT_FLASH_SL  BIT(5)
      20            0 : #define NPCX_QSPI_SHD_FLASH_SL  BIT(6)
      21            0 : #define NPCX_QSPI_BKP_FLASH_SL  BIT(7)
      22              : 
      23              : /* Supported read mode for Direct Read Access */
      24            0 : #define NPCX_RD_MODE_NORMAL     0
      25            0 : #define NPCX_RD_MODE_FAST       1
      26            0 : #define NPCX_RD_MODE_FAST_DUAL  3
      27              : 
      28              : #if defined(CONFIG_NPCX_SOC_VARIANT_NPCKN)
      29              : /* Maximum length of a valid read burst */
      30              : #define NPCX_BURST_MODE_1_BYTE  0
      31              : #define NPCX_BURST_MODE_16_BYTE 3
      32              : #endif
      33              : 
      34              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_NPCX_FIU_QSPI_H_ */