Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2022 Vestas Wind Systems A/S
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_
       8             : 
       9             : /**
      10             :  * @name GPIO drive strength flags
      11             :  *
      12             :  * The drive strength flags are a Zephyr specific extension of the standard GPIO
      13             :  * flags specified by the Linux GPIO binding. Only applicable for Espressif
      14             :  * ESP32 SoCs.
      15             :  *
      16             :  * The interface supports two different drive strengths:
      17             :  * `DFLT` - The lowest drive strength supported by the HW
      18             :  * `ALT` - The highest drive strength supported by the HW
      19             :  *
      20             :  * @{
      21             :  */
      22             : /** @cond INTERNAL_HIDDEN */
      23             : #define ESP32_GPIO_DS_POS 9
      24             : #define ESP32_GPIO_DS_MASK (0x3U << ESP32_GPIO_DS_POS)
      25             : /** @endcond */
      26             : 
      27             : /** Default drive strength. */
      28           1 : #define ESP32_GPIO_DS_DFLT (0x0U << ESP32_GPIO_DS_POS)
      29             : 
      30             : /** Alternative drive strength. */
      31           1 : #define ESP32_GPIO_DS_ALT (0x3U << ESP32_GPIO_DS_POS)
      32             : 
      33             : /** @} */
      34             : 
      35             : /**
      36             :  * @name GPIO pin input/output enable flags
      37             :  *
      38             :  * These flags allow configuring a pin as input or output while keeping untouched
      39             :  * its complementary configuration. By instance, if we configure a GPIO pin as an
      40             :  * input and pass the flag ESP32_GPIO_PIN_OUT_EN, the driver will not disable the
      41             :  * pin's output buffer. This functionality can be useful to render a pin both an
      42             :  * input and output, for diagnose or testing purposes.
      43             :  *
      44             :  * @{
      45             :  */
      46             : 
      47             : /** Keep GPIO pin enabled as output */
      48           1 : #define ESP32_GPIO_PIN_OUT_EN (1 << 12)
      49             : 
      50             : /** Keep GPIO pin enabled as input */
      51           1 : #define ESP32_GPIO_PIN_IN_EN (1 << 13)
      52             : 
      53             : /** @} */
      54             : 
      55             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_ */