Line data    Source code

       1            0 : /*
       2              :  * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  *
       6              :  */
       7              : 
       8              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_MICROCHIP_SAM_GPIO_H_
       9              : #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_MICROCHIP_SAM_GPIO_H_
      10              : 
      11              : /*
      12              :  * By default the gpio driver will enable slew rate control for
      13              :  * each GPIO being used.
      14              :  * Use this flag to disable the enable operation
      15              :  */
      16            0 : #define SAM_GPIO_DIS_SLEWRATE           (1U << 8)
      17              : /*
      18              :  * With this flag, IFEN and IFSCEN will be enabled simultaneously
      19              :  */
      20            0 : #define SAM_GPIO_DEBOUNCE               (1U << 9)
      21              : /*
      22              :  * The Schmitt Trigger is enabled after chip reset
      23              :  * Use this flag to disable it
      24              :  */
      25            0 : #define SAM_GPIO_DIS_SCHMIT             (1U << 10)
      26              : 
      27              : /*
      28              :  * Use these flags to select the drive strength
      29              :  * Otherwise the SAM_GPIO_DRVSTR_DEFAULT will be used
      30              :  */
      31            0 : #define SAM_GPIO_DRVSTR_POS             (11U)
      32            0 : #define SAM_GPIO_DRVSTR_MASK            (0x3U << SAM_GPIO_DRVSTR_POS)
      33            0 : #define SAM_GPIO_DRVSTR_DEFAULT         (0U << SAM_GPIO_DRVSTR_POS)
      34            0 : #define SAM_GPIO_DRVSTR_LOW             (1U << SAM_GPIO_DRVSTR_POS)
      35            0 : #define SAM_GPIO_DRVSTR_MED             (2U << SAM_GPIO_DRVSTR_POS)
      36            0 : #define SAM_GPIO_DRVSTR_HI              (3U << SAM_GPIO_DRVSTR_POS)
      37              : 
      38              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_MICROCHIP_SAM_GPIO_H_ */