Line data    Source code

       1            0 : /*
       2              :  * Copyright 2025 NXP
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_PCA_SERIES_GPIO_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_PCA_SERIES_GPIO_H_
       8              : 
       9              : /**
      10              :  * @brief PCA-Series GPIO expander specific flags
      11              :  *
      12              :  * The driver flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
      13              :  * follows:
      14              :  *
      15              :  * - Bit 8-9: Drive strength for output drive strength register.
      16              :  *
      17              :  * @ingroup gpio_interface
      18              :  * @{
      19              :  */
      20              : 
      21              : /** @cond INTERNAL_HIDDEN */
      22              : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_CONFIG_POS \
      23              :                 8
      24              : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_CONFIG_MASK \
      25              :                 (0x3U << PCA_SERIES_GPIO_DRIVE_STRENGTH_CONFIG_POS)
      26              : 
      27              : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_POS \
      28              :                 10
      29              : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_MASK \
      30              :                 (0x1U << PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_POS)
      31              : /** @endcond */
      32              : 
      33              : /**
      34              :  * @name PCA-Series GPIO drive strength flags
      35              :  * @brief Macros for configuring output drive strength, aligned
      36              :  *        with enum gpio_pca_series_drive_strength in gpio_pca_series.c.
      37              :  *        PCA_SERIES_GPIO_DRIVE_STRENGTH_X1 is the lowest strength,
      38              :  *        PCA_SERIES_GPIO_DRIVE_STRENGTH_X4 is the highest strength.
      39              :  *        Upon reset, the default drive strength is PCA_SERIES_GPIO_DRIVE_STRENGTH_X4.
      40              :  * @note Only applies to part no with PCA_HAS_LATCH capability.
      41              :  * @{
      42              :  */
      43              : 
      44              : /** Interrupt routed to the WKPU controller */
      45            1 : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_X1 \
      46              :         ((0x0U << PCA_SERIES_GPIO_DRIVE_STRENGTH_POS) | \
      47              :          (0x1U << PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_POS))
      48            0 : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_X2 \
      49              :         ((0x1U << PCA_SERIES_GPIO_DRIVE_STRENGTH_POS) | \
      50              :          (0x1U << PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_POS))
      51            0 : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_X3 \
      52              :         ((0x2U << PCA_SERIES_GPIO_DRIVE_STRENGTH_POS) | \
      53              :          (0x1U << PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_POS))
      54            0 : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_X4 \
      55              :         ((0x3U << PCA_SERIES_GPIO_DRIVE_STRENGTH_POS) | \
      56              :          (0x1U << PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_POS))
      57              : 
      58              : /** Default drive strength on device reset */
      59            1 : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_DEFAULT PCA_SERIES_GPIO_DRIVE_STRENGTH_X4
      60              : 
      61            0 : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_CONFIG(x) \
      62              :         ((x & PCA_SERIES_GPIO_DRIVE_STRENGTH_CONFIG_MASK) >> \
      63              :         PCA_SERIES_GPIO_DRIVE_STRENGTH_CONFIG_POS)
      64              : 
      65            0 : #define PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE(x) \
      66              :         ((x & PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_MASK) >> \
      67              :         PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_POS)
      68              : 
      69              : /** @} */
      70              : 
      71              : /** @} */
      72              : 
      73              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_PCA_SERIES_GPIO_H_ */