LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/gpio - realtek-gpio.h Coverage Total Hit
Test: new.info Lines: 9.7 % 124 12
Test Date: 2025-09-25 19:22:35

            Line data    Source code
       1            0 : /*
       2              :  * SPDX-License-Identifier: Apache-2.0
       3              :  *
       4              :  * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
       5              :  * Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
       6              :  */
       7              : 
       8              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_
       9              : #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_
      10              : 
      11              : /** Enable input detect */
      12            1 : #define RTS5912_GPIO_INDETEN  BIT(8)
      13              : /** Set pin driving current */
      14            1 : #define RTS5912_GPIO_OUTDRV   BIT(9)
      15              : /** Set GPIO slew rate */
      16            1 : #define RTS5912_GPIO_SLEWRATE BIT(10)
      17              : /** Enable Schmitt-trigger */
      18            1 : #define RTS5912_GPIO_SCHEN    BIT(11)
      19              : 
      20            0 : #define RTS5912_GPIO_VOLTAGE_POS     12
      21            0 : #define RTS5912_GPIO_VOLTAGE_MASK    GENMASK(13, 12)
      22              : /** Set pin at the default voltage level */
      23            1 : #define RTS5912_GPIO_VOLTAGE_DEFAULT (0U << RTS5912_GPIO_VOLTAGE_POS)
      24              : /** Set pin voltage level at 1.8 V */
      25            1 : #define RTS5912_GPIO_VOLTAGE_1V8     (1U << RTS5912_GPIO_VOLTAGE_POS)
      26              : /** Set pin voltage level at 3.3 V */
      27            1 : #define RTS5912_GPIO_VOLTAGE_3V3     (2U << RTS5912_GPIO_VOLTAGE_POS)
      28              : /** Set pin voltage level at 5.0 V */
      29            1 : #define RTS5912_GPIO_VOLTAGE_5V0     (3U << RTS5912_GPIO_VOLTAGE_POS)
      30              : 
      31              : /** Multi function */
      32            1 : #define RTS5912_GPIO_MFCTRL_POS  14
      33            0 : #define RTS5912_GPIO_MFCTRL_MASK GENMASK(15, 14)
      34              : /** 0x00:Function 0 0x01: Function 1 0x02: Function 2 0x03: Function 3 */
      35            1 : #define RTS5912_GPIO_MFCTRL_0    (0U << RTS5912_GPIO_MFCTRL_POS)
      36            0 : #define RTS5912_GPIO_MFCTRL_1    (1U << RTS5912_GPIO_MFCTRL_POS)
      37            0 : #define RTS5912_GPIO_MFCTRL_2    (2U << RTS5912_GPIO_MFCTRL_POS)
      38            0 : #define RTS5912_GPIO_MFCTRL_3    (3U << RTS5912_GPIO_MFCTRL_POS)
      39              : /** Interrupt Mask since rts5912 does not support GPIO_INT_LEVELS_LOGICAL*/
      40            1 : #define RTS5912_GPIO_INTR_MASK   (1U << 21 | 1U << 22 | 1U << 24 | 1U << 25 | 1U << 26)
      41              : 
      42              : /**
      43              :  * @brief Map GPIO signal name to devicetree binding.
      44              :  *
      45              :  * RTS5912 documentation uses octal GPIO pin
      46              :  * numbering. These macros do not require the user to do the transfer for gpio.
      47              :  *
      48              :  * Example DT usage:
      49              :  *
      50              :  * @code{.dts}
      51              :  * gpios = <RTS5912_GPIO102 (GPIO_OUTPUT)>;
      52              :  * @endcode
      53              :  *
      54              :  * @{
      55              :  */
      56              : 
      57            1 : #define RTS5912_GPIO000 &gpioa 0
      58            0 : #define RTS5912_GPIO001 &gpioa 1
      59            0 : #define RTS5912_GPIO002 &gpioa 2
      60            0 : #define RTS5912_GPIO003 &gpioa 3
      61            0 : #define RTS5912_GPIO004 &gpioa 4
      62            0 : #define RTS5912_GPIO009 &gpioa 9
      63            0 : #define RTS5912_GPIO013 &gpioa 13
      64            0 : #define RTS5912_GPIO014 &gpioa 14
      65            0 : #define RTS5912_GPIO015 &gpioa 15
      66            0 : #define RTS5912_GPIO016 &gpiob 0
      67            0 : #define RTS5912_GPIO017 &gpiob 1
      68            0 : #define RTS5912_GPIO018 &gpiob 2
      69            0 : #define RTS5912_GPIO019 &gpiob 3
      70            0 : #define RTS5912_GPIO020 &gpiob 4
      71            0 : #define RTS5912_GPIO021 &gpiob 5
      72            0 : #define RTS5912_GPIO022 &gpiob 6
      73            0 : #define RTS5912_GPIO023 &gpiob 7
      74            0 : #define RTS5912_GPIO025 &gpiob 9
      75            0 : #define RTS5912_GPIO026 &gpiob 10
      76            0 : #define RTS5912_GPIO027 &gpiob 11
      77            0 : #define RTS5912_GPIO028 &gpiob 12
      78            0 : #define RTS5912_GPIO029 &gpiob 13
      79            0 : #define RTS5912_GPIO030 &gpiob 14
      80            0 : #define RTS5912_GPIO031 &gpiob 15
      81            0 : #define RTS5912_GPIO040 &gpioc 8
      82            0 : #define RTS5912_GPIO041 &gpioc 9
      83            0 : #define RTS5912_GPIO042 &gpioc 10
      84            0 : #define RTS5912_GPIO043 &gpioc 11
      85            0 : #define RTS5912_GPIO044 &gpioc 12
      86            0 : #define RTS5912_GPIO045 &gpioc 13
      87            0 : #define RTS5912_GPIO046 &gpioc 14
      88            0 : #define RTS5912_GPIO047 &gpioc 15
      89            0 : #define RTS5912_GPIO048 &gpiod 0
      90            0 : #define RTS5912_GPIO049 &gpiod 1
      91            0 : #define RTS5912_GPIO050 &gpiod 2
      92            0 : #define RTS5912_GPIO051 &gpiod 3
      93            0 : #define RTS5912_GPIO052 &gpiod 4
      94            0 : #define RTS5912_GPIO053 &gpiod 5
      95            0 : #define RTS5912_GPIO055 &gpiod 7
      96            0 : #define RTS5912_GPIO056 &gpiod 8
      97            0 : #define RTS5912_GPIO057 &gpiod 9
      98            0 : #define RTS5912_GPIO058 &gpiod 10
      99            0 : #define RTS5912_GPIO059 &gpiod 11
     100            0 : #define RTS5912_GPIO060 &gpiod 12
     101            0 : #define RTS5912_GPIO061 &gpiod 13
     102            0 : #define RTS5912_GPIO064 &gpioe 0
     103            0 : #define RTS5912_GPIO065 &gpioe 1
     104            0 : #define RTS5912_GPIO066 &gpioe 2
     105            0 : #define RTS5912_GPIO067 &gpioe 3
     106            0 : #define RTS5912_GPIO068 &gpioe 4
     107            0 : #define RTS5912_GPIO069 &gpioe 5
     108            0 : #define RTS5912_GPIO070 &gpioe 6
     109            0 : #define RTS5912_GPIO071 &gpioe 7
     110            0 : #define RTS5912_GPIO074 &gpioe 10
     111            0 : #define RTS5912_GPIO075 &gpioe 11
     112            0 : #define RTS5912_GPIO076 &gpioe 12
     113            0 : #define RTS5912_GPIO077 &gpioe 13
     114            0 : #define RTS5912_GPIO078 &gpioe 14
     115            0 : #define RTS5912_GPIO079 &gpioe 15
     116            0 : #define RTS5912_GPIO080 &gpiof 0
     117            0 : #define RTS5912_GPIO081 &gpiof 1
     118            0 : #define RTS5912_GPIO083 &gpiof 3
     119            0 : #define RTS5912_GPIO084 &gpiof 4
     120            0 : #define RTS5912_GPIO085 &gpiof 5
     121            0 : #define RTS5912_GPIO086 &gpiof 6
     122            0 : #define RTS5912_GPIO087 &gpiof 7
     123            0 : #define RTS5912_GPIO088 &gpiof 8
     124            0 : #define RTS5912_GPIO089 &gpiof 9
     125            0 : #define RTS5912_GPIO090 &gpiof 10
     126            0 : #define RTS5912_GPIO091 &gpiof 11
     127            0 : #define RTS5912_GPIO092 &gpiof 12
     128            0 : #define RTS5912_GPIO093 &gpiof 13
     129            0 : #define RTS5912_GPIO094 &gpiof 14
     130            0 : #define RTS5912_GPIO095 &gpiof 15
     131            0 : #define RTS5912_GPIO096 &gpiog 0
     132            0 : #define RTS5912_GPIO097 &gpiog 1
     133            0 : #define RTS5912_GPIO099 &gpiog 3
     134            0 : #define RTS5912_GPIO100 &gpiog 4
     135            0 : #define RTS5912_GPIO101 &gpiog 5
     136            0 : #define RTS5912_GPIO102 &gpiog 6
     137            0 : #define RTS5912_GPIO103 &gpiog 7
     138            0 : #define RTS5912_GPIO104 &gpiog 8
     139            0 : #define RTS5912_GPIO105 &gpiog 9
     140            0 : #define RTS5912_GPIO106 &gpiog 10
     141            0 : #define RTS5912_GPIO107 &gpiog 11
     142            0 : #define RTS5912_GPIO108 &gpiog 12
     143            0 : #define RTS5912_GPIO109 &gpiog 13
     144            0 : #define RTS5912_GPIO111 &gpiog 15
     145            0 : #define RTS5912_GPIO112 &gpioh 0
     146            0 : #define RTS5912_GPIO113 &gpioh 1
     147            0 : #define RTS5912_GPIO114 &gpioh 2
     148            0 : #define RTS5912_GPIO115 &gpioh 3
     149            0 : #define RTS5912_GPIO117 &gpioh 5
     150            0 : #define RTS5912_GPIO118 &gpioh 6
     151            0 : #define RTS5912_GPIO119 &gpioh 7
     152            0 : #define RTS5912_GPIO120 &gpioh 8
     153            0 : #define RTS5912_GPIO121 &gpioh 9
     154            0 : #define RTS5912_GPIO122 &gpioh 10
     155            0 : #define RTS5912_GPIO123 &gpioh 11
     156            0 : #define RTS5912_GPIO124 &gpioh 12
     157            0 : #define RTS5912_GPIO125 &gpioh 13
     158            0 : #define RTS5912_GPIO126 &gpioh 14
     159            0 : #define RTS5912_GPIO127 &gpioh 15
     160            0 : #define RTS5912_GPIO128 &gpioi 0
     161            0 : #define RTS5912_GPIO130 &gpioi 2
     162            0 : #define RTS5912_GPIO131 &gpioi 3
     163              : 
     164              : /** @} */
     165              : 
     166              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_ */
        

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