Line data    Source code

       1            0 : /*
       2              :  * SPDX-License-Identifier: Apache-2.0
       3              :  *
       4              :  * Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
       5              :  * Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
       6              :  */
       7              : 
       8              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_
       9              : #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_
      10              : 
      11              : /** Enable input detect */
      12            1 : #define RTS5912_GPIO_INDETEN  BIT(8)
      13              : /** Set pin driving current */
      14            1 : #define RTS5912_GPIO_OUTDRV   BIT(9)
      15              : /** Set GPIO slew rate */
      16            1 : #define RTS5912_GPIO_SLEWRATE BIT(10)
      17              : /** Enable Schmitt-trigger */
      18            1 : #define RTS5912_GPIO_SCHEN    BIT(11)
      19              : 
      20            0 : #define RTS5912_GPIO_VOLTAGE_POS     12
      21            0 : #define RTS5912_GPIO_VOLTAGE_MASK    GENMASK(13, 12)
      22              : /** Set pin at the default voltage level */
      23            1 : #define RTS5912_GPIO_VOLTAGE_DEFAULT (0U << RTS5912_GPIO_VOLTAGE_POS)
      24              : /** Set pin voltage level at 1.8 V */
      25            1 : #define RTS5912_GPIO_VOLTAGE_1V8     (1U << RTS5912_GPIO_VOLTAGE_POS)
      26              : /** Set pin voltage level at 3.3 V */
      27            1 : #define RTS5912_GPIO_VOLTAGE_3V3     (2U << RTS5912_GPIO_VOLTAGE_POS)
      28              : /** Set pin voltage level at 5.0 V */
      29            1 : #define RTS5912_GPIO_VOLTAGE_5V0     (3U << RTS5912_GPIO_VOLTAGE_POS)
      30              : 
      31              : /** Multi function */
      32            1 : #define RTS5912_GPIO_MFCTRL_POS  14
      33            0 : #define RTS5912_GPIO_MFCTRL_MASK GENMASK(15, 14)
      34              : /** 0x00:Function 0 0x01: Function 1 0x02: Function 2 0x03: Function 3 */
      35            1 : #define RTS5912_GPIO_MFCTRL_0    (0U << RTS5912_GPIO_MFCTRL_POS)
      36            0 : #define RTS5912_GPIO_MFCTRL_1    (1U << RTS5912_GPIO_MFCTRL_POS)
      37            0 : #define RTS5912_GPIO_MFCTRL_2    (2U << RTS5912_GPIO_MFCTRL_POS)
      38            0 : #define RTS5912_GPIO_MFCTRL_3    (3U << RTS5912_GPIO_MFCTRL_POS)
      39              : /** Interrupt Mask since rts5912 does not support GPIO_INT_LEVELS_LOGICAL*/
      40            1 : #define RTS5912_GPIO_INTR_MASK   (1U << 21 | 1U << 22 | 1U << 24 | 1U << 25 | 1U << 26)
      41              : 
      42              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_ */