Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2024 Renesas Electronics Corporation
       3             :  * SPDX-License-Identifier: Apache-2.0
       4             :  */
       5             : 
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_
       8             : 
       9             : /*********************************RZG3S*****************************************/
      10             : 
      11             : /**
      12             :  * @brief RZ G3S specific GPIO Flags
      13             :  * The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
      14             :  * follows:
      15             :  * - Bit 9..8: Pin driving ability value
      16             :  * - Bit 11..10: Digital Noise Filter Clock Selection value
      17             :  * - Bit 13..12: Digital Noise Filter Number value
      18             :  * - Bit 14: Digital Noise Filter ON/OFF
      19             :  * example:
      20             :  * gpio-consumer {
      21             :  *      out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_FILTER_SET(1, 3, 3))>;
      22             :  * };
      23             :  * gpio-consumer {
      24             :  *      out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_IOLH_SET(2))>;
      25             :  * };
      26             :  */
      27             : 
      28             : /* GPIO drive IOLH */
      29           1 : #define RZG3S_GPIO_IOLH_SHIFT         7U
      30           0 : #define RZG3S_GPIO_IOLH_SET(iolh_val) (iolh_val << RZG3S_GPIO_IOLH_SHIFT)
      31             : 
      32             : /* GPIO filter */
      33           0 : #define RZG3S_GPIO_FILTER_SHIFT    9U
      34           0 : #define RZG3S_GPIO_FILNUM_SHIFT    1U
      35           0 : #define RZG3S_GPIO_FILCLKSEL_SHIFT 3U
      36           0 : #define RZG3S_GPIO_FILTER_SET(fillonoff, filnum, filclksel)                                        \
      37             :         (((fillonoff) | ((filnum) << RZG3S_GPIO_FILNUM_SHIFT) |                                    \
      38             :           ((filclksel) << RZG3S_GPIO_FILCLKSEL_SHIFT))                                             \
      39             :          << RZG3S_GPIO_FILTER_SHIFT)
      40             : 
      41             : /*******************************************************************************/
      42             : 
      43             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ */