Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2024-2025 Renesas Electronics Corporation
       3              :  * SPDX-License-Identifier: Apache-2.0
       4              :  */
       5              : 
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_
       8              : 
       9              : /*********************************RZ/A,G,V**************************************/
      10              : 
      11              : /**
      12              :  * @brief RZ/A,G,V-specific GPIO Flags
      13              :  * The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
      14              :  * follows:
      15              :  * - Bit 8..9: Pin driving ability value
      16              :  * - Bit 10: Digital Noise Filter ON/OFF
      17              :  * - Bit 11..12: Digital Noise Filter Number value
      18              :  * - Bit 13..14: Digital Noise Filter Clock Selection value
      19              :  * example:
      20              :  * gpio-consumer {
      21              :  *      out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_FILTER_SET(1, 3, 3))>;
      22              :  * };
      23              :  * gpio-consumer {
      24              :  *      out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_IOLH_SET(2))>;
      25              :  * };
      26              :  */
      27              : 
      28              : /* GPIO drive IOLH */
      29            1 : #define RZ_GPIO_IOLH_SHIFT         8U
      30            0 : #define RZ_GPIO_IOLH_SET(iolh_val) (iolh_val << RZ_GPIO_IOLH_SHIFT)
      31              : 
      32              : /* GPIO filter */
      33            0 : #define RZ_GPIO_FILTER_SHIFT    10U
      34            0 : #define RZ_GPIO_FILNUM_SHIFT    1U
      35            0 : #define RZ_GPIO_FILCLKSEL_SHIFT 3U
      36            0 : #define RZ_GPIO_FILTER_SET(fillonoff, filnum, filclksel)                                           \
      37              :         (((fillonoff) | ((filnum) << RZ_GPIO_FILNUM_SHIFT) |                                       \
      38              :           ((filclksel) << RZ_GPIO_FILCLKSEL_SHIFT))                                                \
      39              :          << RZ_GPIO_FILTER_SHIFT)
      40              : 
      41              : /*******************************************************************************/
      42              : 
      43              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ */