Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2023 Antmicro <www.antmicro.com>
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZT2M_H_
       8             : #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZT2M_H_
       9             : #include <zephyr/sys/util.h>
      10             : 
      11           0 : #define RZT2M_GPIO_DRIVE_OFFSET 8
      12           0 : #define RZT2M_GPIO_DRIVE_MASK   GENMASK(RZT2M_GPIO_DRIVE_OFFSET + 2, RZT2M_GPIO_DRIVE_OFFSET)
      13             : 
      14             : /**
      15             :  * @brief Select GPIO pin drive strength
      16             :  */
      17           1 : #define RZT2M_GPIO_DRIVE_LOW        (0U << RZT2M_GPIO_DRIVE_OFFSET)
      18           0 : #define RZT2M_GPIO_DRIVE_MIDDLE     (1U << RZT2M_GPIO_DRIVE_OFFSET)
      19           0 : #define RZT2M_GPIO_DRIVE_HIGH       (2U << RZT2M_GPIO_DRIVE_OFFSET)
      20           0 : #define RZT2M_GPIO_DRIVE_ULTRA_HIGH (3U << RZT2M_GPIO_DRIVE_OFFSET)
      21             : 
      22           0 : #define RZT2M_GPIO_SCHMITT_TRIGGER_OFFSET 10
      23           0 : #define RZT2M_GPIO_SCHMITT_TRIGGER_MASK   BIT(RZT2M_GPIO_SCHMITT_TRIGGER_OFFSET)
      24             : 
      25             : /**
      26             :  * @brief Enable GPIO pin schmitt trigger
      27             :  */
      28           1 : #define RZT2M_GPIO_SCHMITT_TRIGGER BIT(RZT2M_GPIO_SCHMITT_TRIGGER_OFFSET)
      29             : 
      30           0 : #define RZT2M_GPIO_SLEW_RATE_OFFSET 11
      31           0 : #define RZT2M_GPIO_SLEW_RATE_MASK   BIT(RZT2M_GPIO_SLEW_RATE_OFFSET)
      32             : 
      33             : /**
      34             :  * @brief Select GPIO pin slew rate
      35             :  */
      36           1 : #define RZT2M_GPIO_SLEW_RATE_SLOW 0U
      37           0 : #define RZT2M_GPIO_SLEW_RATE_FAST BIT(RZT2M_GPIO_SLEW_RATE_OFFSET)
      38             : 
      39             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZT2M_H_ */