Line data    Source code

       1           0 : /*
       2             :  * Copyright 2023 NXP
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INPUTMUX_TRIGGER_PORTS_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_INPUTMUX_TRIGGER_PORTS_H_
       8             : 
       9           0 : #define LPC55S69_DMA0_OTRIG_BASE 0x16000000
      10           0 : #define LPC55S69_DMA0_ITRIG_BASE 0x0E00000F
      11           0 : #define LPC55S69_DMA1_OTRIG_BASE 0x24000002
      12           0 : #define LPC55S69_DMA1_ITRIG_BASE 0x20000008
      13             : 
      14           0 : #define RT595_DMA0_OTRIG_BASE 0x30000000
      15           0 : #define RT595_DMA0_ITRIG_BASE 0x2000000E
      16           0 : #define RT595_DMA1_OTRIG_BASE 0x50000000
      17           0 : #define RT595_DMA1_ITRIG_BASE 0x4000000E
      18             : 
      19           0 : #define LPC55S36_DMA0_OTRIG_BASE 0x16000000
      20           0 : #define LPC55S36_DMA0_ITRIG_BASE 0x0E000011
      21           0 : #define LPC55S36_DMA1_OTRIG_BASE 0x24000002
      22           0 : #define LPC55S36_DMA1_ITRIG_BASE 0x20000008
      23             : 
      24             : #endif