Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
       9              : 
      10            0 : #define WIFI_MAC_INTR_SOURCE                0
      11            0 : #define WIFI_MAC_NMI_SOURCE                 1
      12            0 : #define WIFI_PWR_INTR_SOURCE                2
      13            0 : #define WIFI_BB_INTR_SOURCE                 3
      14            0 : #define BT_MAC_INTR_SOURCE                  4
      15            0 : #define BT_BB_INTR_SOURCE                   5
      16            0 : #define BT_BB_NMI_SOURCE                    6
      17            0 : #define RWBT_INTR_SOURCE                    7
      18            0 : #define RWBLE_INTR_SOURCE                   8
      19            0 : #define RWBT_NMI_SOURCE                     9
      20            0 : #define RWBLE_NMI_SOURCE                    10
      21            0 : #define I2C_MASTER_SOURCE                   11
      22            0 : #define SLC0_INTR_SOURCE                    12
      23            0 : #define SLC1_INTR_SOURCE                    13
      24            0 : #define APB_CTRL_INTR_SOURCE                14
      25            0 : #define UHCI0_INTR_SOURCE                   15
      26            0 : #define GPIO_INTR_SOURCE                    16
      27            0 : #define GPIO_NMI_SOURCE                     17
      28            0 : #define SPI1_INTR_SOURCE                    18
      29            0 : #define SPI2_INTR_SOURCE                    19
      30            0 : #define I2S1_INTR_SOURCE                    20
      31            0 : #define UART0_INTR_SOURCE                   21
      32            0 : #define UART1_INTR_SOURCE                   22
      33            0 : #define LEDC_INTR_SOURCE                    23
      34            0 : #define EFUSE_INTR_SOURCE                   24
      35            0 : #define TWAI_INTR_SOURCE                    25
      36            0 : #define USB_INTR_SOURCE                     26
      37            0 : #define RTC_CORE_INTR_SOURCE                27
      38            0 : #define RMT_INTR_SOURCE                     28
      39            0 : #define I2C_EXT0_INTR_SOURCE                29
      40            0 : #define TIMER1_INTR_SOURCE                  30
      41            0 : #define TIMER2_INTR_SOURCE                  31
      42            0 : #define TG0_T0_LEVEL_INTR_SOURCE            32
      43            0 : #define TG0_WDT_LEVEL_INTR_SOURCE           33
      44            0 : #define TG1_T0_LEVEL_INTR_SOURCE            34
      45            0 : #define TG1_WDT_LEVEL_INTR_SOURCE           35
      46            0 : #define CACHE_IA_INTR_SOURCE                36
      47            0 : #define SYSTIMER_TARGET0_EDGE_INTR_SOURCE   37
      48            0 : #define SYSTIMER_TARGET1_EDGE_INTR_SOURCE   38
      49            0 : #define SYSTIMER_TARGET2_EDGE_INTR_SOURCE   39
      50            0 : #define SPI_MEM_REJECT_CACHE_INTR_SOURCE    40
      51            0 : #define ICACHE_PRELOAD0_INTR_SOURCE         41
      52            0 : #define ICACHE_SYNC0_INTR_SOURCE            42
      53            0 : #define APB_ADC_INTR_SOURCE                 43
      54            0 : #define DMA_CH0_INTR_SOURCE                 44
      55            0 : #define DMA_CH1_INTR_SOURCE                 45
      56            0 : #define DMA_CH2_INTR_SOURCE                 46
      57            0 : #define RSA_INTR_SOURCE                     47
      58            0 : #define AES_INTR_SOURCE                     48
      59            0 : #define SHA_INTR_SOURCE                     49
      60            0 : #define FROM_CPU_INTR0_SOURCE               50
      61            0 : #define FROM_CPU_INTR1_SOURCE               51
      62            0 : #define FROM_CPU_INTR2_SOURCE               52
      63            0 : #define FROM_CPU_INTR3_SOURCE               53
      64            0 : #define ASSIST_DEBUG_INTR_SOURCE            54
      65            0 : #define DMA_APBPERI_PMS_INTR_SOURCE         55
      66            0 : #define CORE0_IRAM0_PMS_INTR_SOURCE         56
      67            0 : #define CORE0_DRAM0_PMS_INTR_SOURCE         57
      68            0 : #define CORE0_PIF_PMS_INTR_SOURCE           58
      69            0 : #define CORE0_PIF_PMS_SIZE_INTR_SOURCE      59
      70            0 : #define BAK_PMS_VIOLATE_INTR_SOURCE         60
      71            0 : #define CACHE_CORE0_ACS_INTR_SOURCE         61
      72              : 
      73              : /* RISC-V supports priority values from 1 (lowest) to 15.
      74              :  * As interrupt controller for Xtensa and RISC-V is shared, this is
      75              :  * set to an intermediate and compatible value.
      76              :  */
      77            0 : #define IRQ_DEFAULT_PRIORITY    3
      78              : 
      79            0 : #define ESP_INTR_FLAG_SHARED    (1<<8)    /* Interrupt can be shared between ISRs */
      80              : 
      81              : #endif