Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32H2_INTMUX_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32H2_INTMUX_H_
       9              : 
      10            0 : #define PMU_INTR_SOURCE                   0
      11            0 : #define EFUSE_INTR_SOURCE                 1
      12            0 : #define LP_RTC_TIMER_INTR_SOURCE          2
      13            0 : #define LP_BLE_TIMER_INTR_SOURCE          3
      14            0 : #define LP_WDT_INTR_SOURCE                4
      15            0 : #define LP_PERI_TIMEOUT_INTR_SOURCE       5
      16            0 : #define LP_APM_M0_INTR_SOURCE             6
      17            0 : #define FROM_CPU_INTR0_SOURCE             7
      18            0 : #define FROM_CPU_INTR1_SOURCE             8
      19            0 : #define FROM_CPU_INTR2_SOURCE             9
      20            0 : #define FROM_CPU_INTR3_SOURCE             10
      21            0 : #define ASSIST_DEBUG_INTR_SOURCE          11
      22            0 : #define TRACE_INTR_SOURCE                 12
      23            0 : #define CACHE_INTR_SOURCE                 13
      24            0 : #define CPU_PERI_TIMEOUT_INTR_SOURCE      14
      25            0 : #define BT_MAC_INTR_SOURCE                15
      26            0 : #define BT_BB_INTR_SOURCE                 16
      27            0 : #define BT_BB_NMI_INTR_SOURCE             17
      28            0 : #define COEX_INTR_SOURCE                  18
      29            0 : #define BLE_TIMER_INTR_SOURCE             19
      30            0 : #define BLE_SEC_INTR_SOURCE               20
      31            0 : #define ZB_MAC_INTR_SOURCE                21
      32            0 : #define GPIO_INTR_SOURCE                  22
      33            0 : #define GPIO_NMI_SOURCE                   23
      34            0 : #define PAU_INTR_SOURCE                   24
      35            0 : #define HP_PERI_TIMEOUT_INTR_SOURCE       25
      36            0 : #define HP_APM_M0_INTR_SOURCE             26
      37            0 : #define HP_APM_M1_INTR_SOURCE             27
      38            0 : #define HP_APM_M2_INTR_SOURCE             28
      39            0 : #define HP_APM_M3_INTR_SOURCE             29
      40            0 : #define MSPI_INTR_SOURCE                  30
      41            0 : #define I2S1_INTR_SOURCE                  31
      42            0 : #define UHCI0_INTR_SOURCE                 32
      43            0 : #define UART0_INTR_SOURCE                 33
      44            0 : #define UART1_INTR_SOURCE                 34
      45            0 : #define LEDC_INTR_SOURCE                  35
      46            0 : #define TWAI0_INTR_SOURCE                 36
      47            0 : #define USB_SERIAL_JTAG_INTR_SOURCE       37
      48            0 : #define RMT_INTR_SOURCE                   38
      49            0 : #define I2C_EXT0_INTR_SOURCE              39
      50            0 : #define I2C_EXT1_INTR_SOURCE              40
      51            0 : #define TG0_T0_LEVEL_INTR_SOURCE          41
      52            0 : #define TG0_WDT_LEVEL_INTR_SOURCE         42
      53            0 : #define TG1_T0_LEVEL_INTR_SOURCE          43
      54            0 : #define TG1_WDT_LEVEL_INTR_SOURCE         44
      55            0 : #define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 45
      56            0 : #define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 46
      57            0 : #define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 47
      58            0 : #define APB_ADC_INTR_SOURCE               48
      59            0 : #define MCPWM0_INTR_SOURCE                49
      60            0 : #define PCNT_INTR_SOURCE                  50
      61            0 : #define PARL_IO_TX_INTR_SOURCE            51
      62            0 : #define PARL_IO_RX_INTR_SOURCE            52
      63            0 : #define DMA_IN_CH0_INTR_SOURCE            53
      64            0 : #define DMA_IN_CH1_INTR_SOURCE            54
      65            0 : #define DMA_IN_CH2_INTR_SOURCE            55
      66            0 : #define DMA_OUT_CH0_INTR_SOURCE           56
      67            0 : #define DMA_OUT_CH1_INTR_SOURCE           57
      68            0 : #define DMA_OUT_CH2_INTR_SOURCE           58
      69            0 : #define GSPI2_INTR_SOURCE                 59
      70            0 : #define AES_INTR_SOURCE                   60
      71            0 : #define SHA_INTR_SOURCE                   61
      72            0 : #define RSA_INTR_SOURCE                   62
      73            0 : #define ECC_INTR_SOURCE                   63
      74            0 : #define ECDSA_INTR_SOURCE                 64
      75            0 : #define MAX_INTR_SOURCE                   65
      76              : 
      77              : /* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */
      78            0 : #define IRQ_DEFAULT_PRIORITY 0
      79              : 
      80            0 : #define ESP_INTR_FLAG_SHARED (1 << 8) /* Interrupt can be shared between ISRs */
      81              : 
      82              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32H2_INTMUX_H_ */