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1 0 : /*
2 : * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_
9 :
10 0 : #define WIFI_MAC_INTR_SOURCE 0 /* WiFi MAC, level */
11 0 : #define WIFI_MAC_NMI_SOURCE 1 /* WiFi MAC, NMI, use if MAC needs fix in NMI */
12 0 : #define WIFI_BB_INTR_SOURCE 2 /* WiFi BB, level, we can do some calibration */
13 0 : #define BT_MAC_INTR_SOURCE 3 /* will be cancelled */
14 0 : #define BT_BB_INTR_SOURCE 4 /* BB, level */
15 0 : #define BT_BB_NMI_SOURCE 5 /* BT BB, NMI, use if BB have bug to fix in NMI */
16 0 : #define RWBT_INTR_SOURCE 6 /* RWBT, level */
17 0 : #define RWBLE_INTR_SOURCE 7 /* RWBLE, level */
18 0 : #define RWBT_NMI_SOURCE 8 /* RWBT, NMI, use if RWBT has bug to fix in NMI */
19 0 : #define RWBLE_NMI_SOURCE 9 /* RWBLE, NMI, use if RWBT has bug to fix in NMI */
20 0 : #define SLC0_INTR_SOURCE 10 /* SLC0, level */
21 0 : #define SLC1_INTR_SOURCE 11 /* SLC1, level */
22 0 : #define UHCI0_INTR_SOURCE 12 /* UHCI0, level */
23 0 : #define UHCI1_INTR_SOURCE 13 /* UHCI1, level */
24 0 : #define TG0_T0_LEVEL_INTR_SOURCE 14 /* TIMER_GROUP0, TIMER0, level */
25 0 : #define TG0_T1_LEVEL_INTR_SOURCE 15 /* TIMER_GROUP0, TIMER1, level */
26 0 : #define TG0_WDT_LEVEL_INTR_SOURCE 16 /* TIMER_GROUP0, WATCHDOG, level */
27 0 : #define TG0_LACT_LEVEL_INTR_SOURCE 17 /* TIMER_GROUP0, LACT, level */
28 0 : #define TG1_T0_LEVEL_INTR_SOURCE 18 /* TIMER_GROUP1, TIMER0, level */
29 0 : #define TG1_T1_LEVEL_INTR_SOURCE 19 /* TIMER_GROUP1, TIMER1, level */
30 0 : #define TG1_WDT_LEVEL_INTR_SOURCE 20 /* TIMER_GROUP1, WATCHDOG, level */
31 0 : #define TG1_LACT_LEVEL_INTR_SOURCE 21 /* TIMER_GROUP1, LACT, level */
32 0 : #define GPIO_INTR_SOURCE 22 /* interrupt of GPIO, level */
33 0 : #define GPIO_NMI_SOURCE 23 /* interrupt of GPIO, NMI */
34 0 : #define FROM_CPU_INTR0_SOURCE 24 /* int0 from a CPU, level */
35 0 : #define FROM_CPU_INTR1_SOURCE 25 /* int1 from a CPU, level */
36 0 : #define FROM_CPU_INTR2_SOURCE 26 /* int2 from a CPU, level, for DPORT Access */
37 0 : #define FROM_CPU_INTR3_SOURCE 27 /* int3 from a CPU, level, for DPORT Access */
38 0 : #define SPI0_INTR_SOURCE 28 /* SPI0, level, for $ Access, do not use this */
39 0 : #define SPI1_INTR_SOURCE 29 /* SPI1, level, flash r/w, do not use this */
40 0 : #define SPI2_INTR_SOURCE 30 /* SPI2, level */
41 0 : #define SPI3_INTR_SOURCE 31 /* SPI3, level */
42 0 : #define I2S0_INTR_SOURCE 32 /* I2S0, level */
43 0 : #define I2S1_INTR_SOURCE 33 /* I2S1, level */
44 0 : #define UART0_INTR_SOURCE 34 /* UART0, level */
45 0 : #define UART1_INTR_SOURCE 35 /* UART1, level */
46 0 : #define UART2_INTR_SOURCE 36 /* UART2, level */
47 0 : #define SDIO_HOST_INTR_SOURCE 37 /* SD/SDIO/MMC HOST, level */
48 0 : #define ETH_MAC_INTR_SOURCE 38 /* ethernet mac, level */
49 0 : #define PWM0_INTR_SOURCE 39 /* PWM0, level, Reserved */
50 0 : #define PWM1_INTR_SOURCE 40 /* PWM1, level, Reserved */
51 0 : #define PWM2_INTR_SOURCE 41 /* PWM2, level */
52 0 : #define PWM3_INTR_SOURCE 42 /* PWM3, level */
53 0 : #define LEDC_INTR_SOURCE 43 /* LED PWM, level */
54 0 : #define EFUSE_INTR_SOURCE 44 /* efuse, level, not likely to use */
55 0 : #define TWAI_INTR_SOURCE 45 /* twai, level */
56 0 : #define CAN_INTR_SOURCE TWAI_INTR_SOURCE
57 0 : #define RTC_CORE_INTR_SOURCE 46 /* rtc core, level, include rtc watchdog */
58 0 : #define RMT_INTR_SOURCE 47 /* remote controller, level */
59 0 : #define PCNT_INTR_SOURCE 48 /* pulse count, level */
60 0 : #define I2C_EXT0_INTR_SOURCE 49 /* I2C controller1, level */
61 0 : #define I2C_EXT1_INTR_SOURCE 50 /* I2C controller0, level */
62 0 : #define RSA_INTR_SOURCE 51 /* RSA accelerator, level */
63 0 : #define SPI1_DMA_INTR_SOURCE 52 /* SPI1 DMA, for flash r/w, do not use it */
64 0 : #define SPI2_DMA_INTR_SOURCE 53 /* SPI2 DMA, level */
65 0 : #define SPI3_DMA_INTR_SOURCE 54 /* interrupt of SPI3 DMA, level */
66 0 : #define WDT_INTR_SOURCE 55 /* will be cancelled */
67 0 : #define TIMER1_INTR_SOURCE 56 /* will be cancelled */
68 0 : #define TIMER2_INTR_SOURCE 57 /* will be cancelled */
69 0 : #define TG0_T0_EDGE_INTR_SOURCE 58 /* TIMER_GROUP0, TIMER0, EDGE */
70 0 : #define TG0_T1_EDGE_INTR_SOURCE 59 /* TIMER_GROUP0, TIMER1, EDGE */
71 0 : #define TG0_WDT_EDGE_INTR_SOURCE 60 /* TIMER_GROUP0, WATCH DOG, EDGE */
72 0 : #define TG0_LACT_EDGE_INTR_SOURCE 61 /* TIMER_GROUP0, LACT, EDGE */
73 0 : #define TG1_T0_EDGE_INTR_SOURCE 62 /* TIMER_GROUP1, TIMER0, EDGE */
74 0 : #define TG1_T1_EDGE_INTR_SOURCE 63 /* TIMER_GROUP1, TIMER1, EDGE */
75 0 : #define TG1_WDT_EDGE_INTR_SOURCE 64 /* TIMER_GROUP1, WATCHDOG, EDGE */
76 0 : #define TG1_LACT_EDGE_INTR_SOURCE 65 /* TIMER_GROUP0, LACT, EDGE */
77 0 : #define MMU_IA_INTR_SOURCE 66 /* MMU Invalid Access, LEVEL */
78 0 : #define MPU_IA_INTR_SOURCE 67 /* MPU Invalid Access, LEVEL */
79 0 : #define CACHE_IA_INTR_SOURCE 68 /* Cache Invalid Access, LEVEL */
80 0 : #define MAX_INTR_SOURCE 69 /* total number of interrupt sources */
81 :
82 : /* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */
83 0 : #define IRQ_DEFAULT_PRIORITY 0
84 :
85 0 : #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
86 :
87 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_ */
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