LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/interrupt-controller - esp32s2-xtensa-intmux.h Coverage Total Hit
Test: new.info Lines: 0.0 % 99 0
Test Date: 2025-09-05 16:43:28

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S2_XTENSA_INTMUX_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S2_XTENSA_INTMUX_H_
       9              : 
      10            0 : #define WIFI_MAC_INTR_SOURCE                0   /* WiFi MAC, level */
      11            0 : #define WIFI_MAC_NMI_SOURCE                 1   /* WiFi MAC, NMI, use if MAC needs fix in NMI */
      12            0 : #define WIFI_PWR_INTR_SOURCE                2
      13            0 : #define WIFI_BB_INTR_SOURCE                 3   /* WiFi BB, level, we can do some calibration */
      14            0 : #define BT_MAC_INTR_SOURCE                  4   /* will be cancelled */
      15            0 : #define BT_BB_INTR_SOURCE                   5   /* BB, level */
      16            0 : #define BT_BB_NMI_SOURCE                    6   /* BT BB, NMI, use if BB have bug to fix in NMI */
      17            0 : #define RWBT_INTR_SOURCE                    7   /* RWBT, level */
      18            0 : #define RWBLE_INTR_SOURCE                   8   /* RWBLE, level */
      19            0 : #define RWBT_NMI_SOURCE                     9   /* RWBT, NMI, use if RWBT has bug to fix in NMI */
      20            0 : #define RWBLE_NMI_SOURCE                    10  /* RWBLE, NMI, use if RWBT has bug to fix in NMI */
      21            0 : #define SLC0_INTR_SOURCE                    11  /* SLC0, level */
      22            0 : #define SLC1_INTR_SOURCE                    12  /* SLC1, level */
      23            0 : #define UHCI0_INTR_SOURCE                   13  /* UHCI0, level */
      24            0 : #define UHCI1_INTR_SOURCE                   14  /* UHCI1, level */
      25            0 : #define TG0_T0_LEVEL_INTR_SOURCE            15  /* TIMER_GROUP0, TIMER0, level */
      26            0 : #define TG0_T1_LEVEL_INTR_SOURCE            16  /* TIMER_GROUP0, TIMER1, level */
      27            0 : #define TG0_WDT_LEVEL_INTR_SOURCE           17  /* TIMER_GROUP0, WATCHDOG, level */
      28            0 : #define TG0_LACT_LEVEL_INTR_SOURCE          18  /* TIMER_GROUP0, LACT, level */
      29            0 : #define TG1_T0_LEVEL_INTR_SOURCE            19  /* TIMER_GROUP1, TIMER0, level */
      30            0 : #define TG1_T1_LEVEL_INTR_SOURCE            20  /* TIMER_GROUP1, TIMER1, level */
      31            0 : #define TG1_WDT_LEVEL_INTR_SOURCE           21  /* TIMER_GROUP1, WATCHDOG, level */
      32            0 : #define TG1_LACT_LEVEL_INTR_SOURCE          22  /* TIMER_GROUP1, LACT, level */
      33            0 : #define GPIO_INTR_SOURCE                    23  /* interrupt of GPIO, level */
      34            0 : #define GPIO_NMI_SOURCE                     24  /* interrupt of GPIO, NMI */
      35            0 : #define GPIO_INTR_SOURCE2                   25  /* interrupt of GPIO, level */
      36            0 : #define GPIO_NMI_SOURCE2                    26  /* interrupt of GPIO, NMI */
      37            0 : #define DEDICATED_GPIO_INTR_SOURCE          27  /* interrupt of dedicated GPIO, level */
      38            0 : #define FROM_CPU_INTR0_SOURCE               28  /* int0 from a CPU, level */
      39            0 : #define FROM_CPU_INTR1_SOURCE               29  /* int1 from a CPU, level */
      40            0 : #define FROM_CPU_INTR2_SOURCE               30  /* int2 from a CPU, level, for DPORT Access */
      41            0 : #define FROM_CPU_INTR3_SOURCE               31  /* int3 from a CPU, level, for DPORT Access */
      42            0 : #define SPI1_INTR_SOURCE                    32  /* SPI1, level, flash r/w, do not use this */
      43            0 : #define SPI2_INTR_SOURCE                    33  /* SPI2, level */
      44            0 : #define SPI3_INTR_SOURCE                    34  /* SPI3, level */
      45            0 : #define I2S0_INTR_SOURCE                    35  /* I2S0, level */
      46            0 : #define I2S1_INTR_SOURCE                    36  /* I2S1, level */
      47            0 : #define UART0_INTR_SOURCE                   37  /* UART0, level */
      48            0 : #define UART1_INTR_SOURCE                   38  /* UART1, level */
      49            0 : #define UART2_INTR_SOURCE                   39  /* UART2, level */
      50            0 : #define SDIO_HOST_INTR_SOURCE               40  /* SD/SDIO/MMC HOST, level */
      51            0 : #define PWM0_INTR_SOURCE                    41  /* PWM0, level, Reserved */
      52            0 : #define PWM1_INTR_SOURCE                    42  /* PWM1, level, Reserved */
      53            0 : #define PWM2_INTR_SOURCE                    43  /* PWM2, level */
      54            0 : #define PWM3_INTR_SOURCE                    44  /* PWM3, level */
      55            0 : #define LEDC_INTR_SOURCE                    45  /* LED PWM, level */
      56            0 : #define EFUSE_INTR_SOURCE                   46  /* efuse, level, not likely to use */
      57            0 : #define TWAI_INTR_SOURCE                    47  /* twai, level */
      58            0 : #define USB_INTR_SOURCE                     48  /* interrupt of USB, level */
      59            0 : #define RTC_CORE_INTR_SOURCE                49  /* rtc core, level, include rtc watchdog */
      60            0 : #define RMT_INTR_SOURCE                     50  /* remote controller, level */
      61            0 : #define PCNT_INTR_SOURCE                    51  /* pulse count, level */
      62            0 : #define I2C_EXT0_INTR_SOURCE                52  /* I2C controller1, level */
      63            0 : #define I2C_EXT1_INTR_SOURCE                53  /* I2C controller0, level */
      64            0 : #define RSA_INTR_SOURCE                     54  /* RSA accelerator, level */
      65            0 : #define SHA_INTR_SOURCE                     55  /* interrupt of RSA accelerator, level */
      66            0 : #define AES_INTR_SOURCE                     56  /* interrupt of SHA accelerator, level */
      67            0 : #define SPI2_DMA_INTR_SOURCE                57  /* SPI2 DMA, level */
      68            0 : #define SPI3_DMA_INTR_SOURCE                58  /* interrupt of SPI3 DMA, level */
      69            0 : #define WDT_INTR_SOURCE                     59  /* will be cancelled */
      70            0 : #define TIMER1_INTR_SOURCE                  60  /* will be cancelled */
      71            0 : #define TIMER2_INTR_SOURCE                  61  /* will be cancelled */
      72            0 : #define TG0_T0_EDGE_INTR_SOURCE             62  /* TIMER_GROUP0, TIMER0, EDGE */
      73            0 : #define TG0_T1_EDGE_INTR_SOURCE             63  /* TIMER_GROUP0, TIMER1, EDGE */
      74            0 : #define TG0_WDT_EDGE_INTR_SOURCE            64  /* TIMER_GROUP0, WATCH DOG, EDGE */
      75            0 : #define TG0_LACT_EDGE_INTR_SOURCE           65  /* TIMER_GROUP0, LACT, EDGE */
      76            0 : #define TG1_T0_EDGE_INTR_SOURCE             66  /* TIMER_GROUP1, TIMER0, EDGE */
      77            0 : #define TG1_T1_EDGE_INTR_SOURCE             67  /* TIMER_GROUP1, TIMER1, EDGE */
      78            0 : #define TG1_WDT_EDGE_INTR_SOURCE            68  /* TIMER_GROUP1, WATCHDOG, EDGE */
      79            0 : #define TG1_LACT_EDGE_INTR_SOURCE           69  /* TIMER_GROUP0, LACT, EDGE */
      80            0 : #define CACHE_IA_INTR_SOURCE                70  /* Cache Invalid Access, level */
      81            0 : #define SYSTIMER_TARGET0_EDGE_INTR_SOURCE   71  /* system timer 0, edge */
      82            0 : #define SYSTIMER_TARGET1_EDGE_INTR_SOURCE   72  /* system timer 1, edge */
      83            0 : #define SYSTIMER_TARGET2_EDGE_INTR_SOURCE   73  /* system timer 2, edge */
      84            0 : #define ASSIST_DEBUG_INTR_SOURCE            74  /* Assist debug module, level */
      85            0 : #define PMS_PRO_IRAM0_ILG_INTR_SOURCE       75  /* illegal IRAM1 access, level */
      86            0 : #define PMS_PRO_DRAM0_ILG_INTR_SOURCE       76  /* illegal DRAM0 access, level */
      87            0 : #define PMS_PRO_DPORT_ILG_INTR_SOURCE       77  /* illegal DPORT access, level */
      88            0 : #define PMS_PRO_AHB_ILG_INTR_SOURCE         78  /* illegal AHB access, level */
      89            0 : #define PMS_PRO_CACHE_ILG_INTR_SOURCE       79  /* illegal CACHE access, level */
      90            0 : #define PMS_DMA_APB_I_ILG_INTR_SOURCE       80  /* illegal APB access, level */
      91            0 : #define PMS_DMA_RX_I_ILG_INTR_SOURCE        81  /* illegal DMA RX access, level */
      92            0 : #define PMS_DMA_TX_I_ILG_INTR_SOURCE        82  /* illegal DMA TX access, level */
      93              : #define SPI_MEM_REJECT_CACHE_INTR_SOURCE    83  /* SPI0 Cache access and
      94              :                                                  * SPI1 access rejected, level
      95            0 :                                                  */
      96            0 : #define DMA_COPY_INTR_SOURCE                84  /* DMA copy, level */
      97            0 : #define SPI4_DMA_INTR_SOURCE                85  /* SPI4 DMA, level */
      98            0 : #define SPI4_INTR_SOURCE                    86  /* SPI4, level */
      99            0 : #define ICACHE_PRELOAD_INTR_SOURCE          87  /* ICache preload operation, level */
     100            0 : #define DCACHE_PRELOAD_INTR_SOURCE          88  /* DCache preload operation, level */
     101            0 : #define APB_ADC_INTR_SOURCE                 89  /* APB ADC, level */
     102            0 : #define CRYPTO_DMA_INTR_SOURCE              90  /* encrypted DMA, level */
     103            0 : #define CPU_PERI_ERROR_INTR_SOURCE          91  /* CPU peripherals error, level */
     104            0 : #define APB_PERI_ERROR_INTR_SOURCE          92  /* APB peripherals error, level */
     105            0 : #define DCACHE_SYNC_INTR_SOURCE             93  /* data cache sync done, level */
     106            0 : #define ICACHE_SYNC_INTR_SOURCE             94  /* instruction cache sync done, level */
     107            0 : #define MAX_INTR_SOURCE                     95  /* total number of interrupt sources */
     108              : 
     109              : /* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */
     110            0 : #define IRQ_DEFAULT_PRIORITY    0
     111              : 
     112            0 : #define ESP_INTR_FLAG_SHARED    (1<<8)    /* Interrupt can be shared between ISRs */
     113              : 
     114              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S2_XTENSA_INTMUX_H_ */
        

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