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1 0 : /*
2 : * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S3_XTENSA_INTMUX_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S3_XTENSA_INTMUX_H_
9 :
10 0 : #define WIFI_MAC_INTR_SOURCE 0 /* interrupt of WiFi MAC, level*/
11 0 : #define WIFI_MAC_NMI_SOURCE 1 /* interrupt of WiFi MAC, NMI */
12 0 : #define WIFI_PWR_INTR_SOURCE 2
13 0 : #define WIFI_BB_INTR_SOURCE 3 /* interrupt of WiFi BB, level*/
14 0 : #define BT_MAC_INTR_SOURCE 4 /* will be cancelled*/
15 0 : #define BT_BB_INTR_SOURCE 5 /* interrupt of BT BB, level*/
16 0 : #define BT_BB_NMI_SOURCE 6 /* interrupt of BT BB, NMI*/
17 0 : #define RWBT_INTR_SOURCE 7 /* interrupt of RWBT, level*/
18 0 : #define RWBLE_INTR_SOURCE 8 /* interrupt of RWBLE, level*/
19 0 : #define RWBT_NMI_SOURCE 9 /* interrupt of RWBT, NMI*/
20 0 : #define RWBLE_NMI_SOURCE 10 /* interrupt of RWBLE, NMI*/
21 0 : #define I2C_MASTER_SOURCE 11 /* interrupt of I2C Master, level*/
22 0 : #define SLC0_INTR_SOURCE 12 /* interrupt of SLC0, level*/
23 0 : #define SLC1_INTR_SOURCE 13 /* interrupt of SLC1, level*/
24 0 : #define UHCI0_INTR_SOURCE 14 /* interrupt of UHCI0, level*/
25 0 : #define UHCI1_INTR_SOURCE 15 /* interrupt of UHCI1, level*/
26 0 : #define GPIO_INTR_SOURCE 16 /* interrupt of GPIO, level*/
27 0 : #define GPIO_NMI_SOURCE 17 /* interrupt of GPIO, NMI*/
28 0 : #define GPIO_INTR_SOURCE2 18 /* interrupt of GPIO, level*/
29 0 : #define GPIO_NMI_SOURCE2 19 /* interrupt of GPIO, NMI*/
30 0 : #define SPI1_INTR_SOURCE 20 /* interrupt of SPI1, level*/
31 0 : #define SPI2_INTR_SOURCE 21 /* interrupt of SPI2, level*/
32 0 : #define SPI3_INTR_SOURCE 22 /* interrupt of SPI3, level*/
33 0 : #define LCD_CAM_INTR_SOURCE 24 /* interrupt of LCD camera, level*/
34 0 : #define I2S0_INTR_SOURCE 25 /* interrupt of I2S0, level*/
35 0 : #define I2S1_INTR_SOURCE 26 /* interrupt of I2S1, level*/
36 0 : #define UART0_INTR_SOURCE 27 /* interrupt of UART0, level*/
37 0 : #define UART1_INTR_SOURCE 28 /* interrupt of UART1, level*/
38 0 : #define UART2_INTR_SOURCE 29 /* interrupt of UART2, level*/
39 0 : #define SDIO_HOST_INTR_SOURCE 30 /* interrupt of SD/SDIO/MMC HOST, level*/
40 0 : #define PWM0_INTR_SOURCE 31 /* interrupt of PWM0, level, Reserved*/
41 0 : #define PWM1_INTR_SOURCE 32 /* interrupt of PWM1, level, Reserved*/
42 0 : #define LEDC_INTR_SOURCE 35 /* interrupt of LED PWM, level*/
43 0 : #define EFUSE_INTR_SOURCE 36 /* interrupt of efuse, level, not likely to use*/
44 0 : #define TWAI_INTR_SOURCE 37 /* interrupt of can, level*/
45 0 : #define USB_INTR_SOURCE 38 /* interrupt of USB, level*/
46 0 : #define RTC_CORE_INTR_SOURCE 39 /* interrupt of rtc core and watchdog, level*/
47 0 : #define RMT_INTR_SOURCE 40 /* interrupt of remote controller, level*/
48 0 : #define PCNT_INTR_SOURCE 41 /* interrupt of pulse count, level*/
49 0 : #define I2C_EXT0_INTR_SOURCE 42 /* interrupt of I2C controller1, level*/
50 0 : #define I2C_EXT1_INTR_SOURCE 43 /* interrupt of I2C controller0, level*/
51 0 : #define SPI2_DMA_INTR_SOURCE 44 /* interrupt of SPI2 DMA, level*/
52 0 : #define SPI3_DMA_INTR_SOURCE 45 /* interrupt of SPI3 DMA, level*/
53 0 : #define WDT_INTR_SOURCE 47 /* will be cancelled*/
54 0 : #define TIMER1_INTR_SOURCE 48
55 0 : #define TIMER2_INTR_SOURCE 49
56 0 : #define TG0_T0_LEVEL_INTR_SOURCE 50 /* interrupt of TIMER_GROUP0, TIMER0, EDGE*/
57 0 : #define TG0_T1_LEVEL_INTR_SOURCE 51 /* interrupt of TIMER_GROUP0, TIMER1, EDGE*/
58 0 : #define TG0_WDT_LEVEL_INTR_SOURCE 52 /* interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
59 0 : #define TG1_T0_LEVEL_INTR_SOURCE 53 /* interrupt of TIMER_GROUP1, TIMER0, EDGE*/
60 0 : #define TG1_T1_LEVEL_INTR_SOURCE 54 /* interrupt of TIMER_GROUP1, TIMER1, EDGE*/
61 0 : #define TG1_WDT_LEVEL_INTR_SOURCE 55 /* interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
62 0 : #define CACHE_IA_INTR_SOURCE 56 /* interrupt of Cache Invalid Access, LEVEL*/
63 0 : #define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 57 /* interrupt of system timer 0, EDGE*/
64 0 : #define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 58 /* interrupt of system timer 1, EDGE*/
65 0 : #define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 59 /* interrupt of system timer 2, EDGE*/
66 0 : #define SPI_MEM_REJECT_CACHE_INTR_SOURCE 60 /* interrupt of SPI0/SPI1 Cache/Rejected, LEVEL*/
67 0 : #define DCACHE_PRELOAD0_INTR_SOURCE 61 /* interrupt of DCache preload operation, LEVEL*/
68 0 : #define ICACHE_PRELOAD0_INTR_SOURCE 62 /* interrupt of ICache perload operation, LEVEL*/
69 0 : #define DCACHE_SYNC0_INTR_SOURCE 63 /* interrupt of data cache sync done, LEVEL*/
70 0 : #define ICACHE_SYNC0_INTR_SOURCE 64 /* interrupt of instr. cache sync done, LEVEL*/
71 0 : #define APB_ADC_INTR_SOURCE 65 /* interrupt of APB ADC, LEVEL*/
72 0 : #define DMA_IN_CH0_INTR_SOURCE 66 /* interrupt of general DMA RX channel 0, LEVEL*/
73 0 : #define DMA_IN_CH1_INTR_SOURCE 67 /* interrupt of general DMA RX channel 1, LEVEL*/
74 0 : #define DMA_IN_CH2_INTR_SOURCE 68 /* interrupt of general DMA RX channel 2, LEVEL*/
75 0 : #define DMA_IN_CH3_INTR_SOURCE 69 /* interrupt of general DMA RX channel 3, LEVEL*/
76 0 : #define DMA_IN_CH4_INTR_SOURCE 70 /* interrupt of general DMA RX channel 4, LEVEL*/
77 0 : #define DMA_OUT_CH0_INTR_SOURCE 71 /* interrupt of general DMA TX channel 0, LEVEL*/
78 0 : #define DMA_OUT_CH1_INTR_SOURCE 72 /* interrupt of general DMA TX channel 1, LEVEL*/
79 0 : #define DMA_OUT_CH2_INTR_SOURCE 73 /* interrupt of general DMA TX channel 2, LEVEL*/
80 0 : #define DMA_OUT_CH3_INTR_SOURCE 74 /* interrupt of general DMA TX channel 3, LEVEL*/
81 0 : #define DMA_OUT_CH4_INTR_SOURCE 75 /* interrupt of general DMA TX channel 4, LEVEL*/
82 0 : #define RSA_INTR_SOURCE 76 /* interrupt of RSA accelerator, level*/
83 0 : #define AES_INTR_SOURCE 77 /* interrupt of AES accelerator, level*/
84 0 : #define SHA_INTR_SOURCE 78 /* interrupt of SHA accelerator, level*/
85 0 : #define FROM_CPU_INTR0_SOURCE 79 /* interrupt0 generated from a CPU, level*/
86 0 : #define FROM_CPU_INTR1_SOURCE 80 /* interrupt1 generated from a CPU, level*/
87 0 : #define FROM_CPU_INTR2_SOURCE 81 /* interrupt2 generated from a CPU, level*/
88 0 : #define FROM_CPU_INTR3_SOURCE 82 /* interrupt3 generated from a CPU, level*/
89 0 : #define ASSIST_DEBUG_INTR_SOURCE 83 /* interrupt of Assist debug module, LEVEL*/
90 0 : #define DMA_APBPERI_PMS_INTR_SOURCE 84
91 0 : #define CORE0_IRAM0_PMS_INTR_SOURCE 85
92 0 : #define CORE0_DRAM0_PMS_INTR_SOURCE 86
93 0 : #define CORE0_PIF_PMS_INTR_SOURCE 87
94 0 : #define CORE0_PIF_PMS_SIZE_INTR_SOURCE 88
95 0 : #define CORE1_IRAM0_PMS_INTR_SOURCE 89
96 0 : #define CORE1_DRAM0_PMS_INTR_SOURCE 90
97 0 : #define CORE1_PIF_PMS_INTR_SOURCE 91
98 0 : #define CORE1_PIF_PMS_SIZE_INTR_SOURCE 92
99 0 : #define BACKUP_PMS_VIOLATE_INTR_SOURCE 93
100 0 : #define CACHE_CORE0_ACS_INTR_SOURCE 94
101 0 : #define CACHE_CORE1_ACS_INTR_SOURCE 95
102 0 : #define USB_SERIAL_JTAG_INTR_SOURCE 96
103 0 : #define PREI_BACKUP_INTR_SOURCE 97
104 0 : #define DMA_EXTMEM_REJECT_SOURCE 98
105 0 : #define MAX_INTR_SOURCE 99 /* number of interrupt sources */
106 :
107 : /* For Xtensa architecture, zero will allocate low/medium
108 : * levels of priority (ESP_INTR_FLAG_LOWMED)
109 : */
110 0 : #define IRQ_DEFAULT_PRIORITY 0
111 :
112 0 : #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
113 :
114 : #endif
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