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1 0 : /* 2 : * Copyright (c) 2020 ITE Corporation. All Rights Reserved. 3 : * SPDX-License-Identifier: Apache-2.0 4 : */ 5 : 6 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ 7 : #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ 8 : 9 0 : #define IRQ_TYPE_NONE 0 10 0 : #define IRQ_TYPE_EDGE_RISING 1 11 0 : #define IRQ_TYPE_EDGE_FALLING 2 12 0 : #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 13 0 : #define IRQ_TYPE_LEVEL_HIGH 4 14 0 : #define IRQ_TYPE_LEVEL_LOW 8 15 : 16 : /* IRQ numbers of WUC */ 17 : /* Group 0 of INTC */ 18 0 : #define IT8XXX2_IRQ_WU20 1 19 0 : #define IT8XXX2_IRQ_KBC_OBE 2 20 0 : #define IT8XXX2_IRQ_SMB_D 4 21 0 : #define IT8XXX2_IRQ_WKINTD 5 22 0 : #define IT8XXX2_IRQ_WU23 6 23 : /* Group 1 */ 24 0 : #define IT8XXX2_IRQ_SMB_A 9 25 0 : #define IT8XXX2_IRQ_SMB_B 10 26 0 : #define IT8XXX2_IRQ_WU26 12 27 0 : #define IT8XXX2_IRQ_WKINTC 13 28 0 : #define IT8XXX2_IRQ_WU25 14 29 : /* Group 2 */ 30 0 : #define IT8XXX2_IRQ_SMB_C 16 31 0 : #define IT8XXX2_IRQ_WU24 17 32 0 : #define IT8XXX2_IRQ_WU22 21 33 0 : #define IT8XXX2_IRQ_USB 23 34 : /* Group 3 */ 35 0 : #define IT8XXX2_IRQ_KBC_IBF 24 36 0 : #define IT8XXX2_IRQ_PMC1_IBF 25 37 0 : #define IT8XXX2_IRQ_PMC2_IBF 27 38 0 : #define IT8XXX2_IRQ_TIMER1 30 39 0 : #define IT8XXX2_IRQ_WU21 31 40 : /* Group 5 */ 41 0 : #define IT8XXX2_IRQ_WU50 40 42 0 : #define IT8XXX2_IRQ_WU51 41 43 0 : #define IT8XXX2_IRQ_WU52 42 44 0 : #define IT8XXX2_IRQ_WU53 43 45 0 : #define IT8XXX2_IRQ_WU54 44 46 0 : #define IT8XXX2_IRQ_WU55 45 47 0 : #define IT8XXX2_IRQ_WU56 46 48 0 : #define IT8XXX2_IRQ_WU57 47 49 : /* Group 6 */ 50 0 : #define IT8XXX2_IRQ_WU60 48 51 0 : #define IT8XXX2_IRQ_WU61 49 52 0 : #define IT8XXX2_IRQ_WU62 50 53 0 : #define IT8XXX2_IRQ_WU63 51 54 0 : #define IT8XXX2_IRQ_WU64 52 55 0 : #define IT8XXX2_IRQ_WU65 53 56 0 : #define IT8XXX2_IRQ_WU66 54 57 0 : #define IT8XXX2_IRQ_WU67 55 58 : /* Group 7 */ 59 0 : #define IT8XXX2_IRQ_TIMER2 58 60 : /* Group 9 */ 61 0 : #define IT8XXX2_IRQ_WU70 72 62 0 : #define IT8XXX2_IRQ_WU71 73 63 0 : #define IT8XXX2_IRQ_WU72 74 64 0 : #define IT8XXX2_IRQ_WU73 75 65 0 : #define IT8XXX2_IRQ_WU74 76 66 0 : #define IT8XXX2_IRQ_WU75 77 67 0 : #define IT8XXX2_IRQ_WU76 78 68 0 : #define IT8XXX2_IRQ_WU77 79 69 : /* Group 10 */ 70 0 : #define IT8XXX2_IRQ_TIMER8 80 71 0 : #define IT8XXX2_IRQ_WU88 85 72 0 : #define IT8XXX2_IRQ_WU89 86 73 0 : #define IT8XXX2_IRQ_WU90 87 74 : /* Group 11 */ 75 0 : #define IT8XXX2_IRQ_WU80 88 76 0 : #define IT8XXX2_IRQ_WU81 89 77 0 : #define IT8XXX2_IRQ_WU82 90 78 0 : #define IT8XXX2_IRQ_WU83 91 79 0 : #define IT8XXX2_IRQ_WU84 92 80 0 : #define IT8XXX2_IRQ_WU85 93 81 0 : #define IT8XXX2_IRQ_WU86 94 82 0 : #define IT8XXX2_IRQ_WU87 95 83 : /* Group 12 */ 84 0 : #define IT8XXX2_IRQ_WU91 96 85 0 : #define IT8XXX2_IRQ_WU92 97 86 0 : #define IT8XXX2_IRQ_WU93 98 87 0 : #define IT8XXX2_IRQ_WU94 99 88 0 : #define IT8XXX2_IRQ_WU95 100 89 0 : #define IT8XXX2_IRQ_WU96 101 90 0 : #define IT8XXX2_IRQ_WU97 102 91 0 : #define IT8XXX2_IRQ_WU98 103 92 : /* Group 13 */ 93 0 : #define IT8XXX2_IRQ_WU99 104 94 0 : #define IT8XXX2_IRQ_WU100 105 95 0 : #define IT8XXX2_IRQ_WU101 106 96 0 : #define IT8XXX2_IRQ_WU102 107 97 0 : #define IT8XXX2_IRQ_WU103 108 98 0 : #define IT8XXX2_IRQ_WU104 109 99 0 : #define IT8XXX2_IRQ_WU105 110 100 0 : #define IT8XXX2_IRQ_WU106 111 101 : /* Group 14 */ 102 0 : #define IT8XXX2_IRQ_WU107 112 103 0 : #define IT8XXX2_IRQ_WU108 113 104 0 : #define IT8XXX2_IRQ_WU109 114 105 0 : #define IT8XXX2_IRQ_WU110 115 106 0 : #define IT8XXX2_IRQ_WU111 116 107 0 : #define IT8XXX2_IRQ_WU112 117 108 0 : #define IT8XXX2_IRQ_WU113 118 109 0 : #define IT8XXX2_IRQ_WU114 119 110 : /* Group 15 */ 111 0 : #define IT8XXX2_IRQ_WU115 120 112 0 : #define IT8XXX2_IRQ_WU116 121 113 0 : #define IT8XXX2_IRQ_WU117 122 114 0 : #define IT8XXX2_IRQ_WU118 123 115 0 : #define IT8XXX2_IRQ_WU119 124 116 0 : #define IT8XXX2_IRQ_WU120 125 117 0 : #define IT8XXX2_IRQ_WU121 126 118 0 : #define IT8XXX2_IRQ_WU122 127 119 : /* Group 16 */ 120 0 : #define IT8XXX2_IRQ_WU128 128 121 0 : #define IT8XXX2_IRQ_WU129 129 122 0 : #define IT8XXX2_IRQ_WU130 130 123 0 : #define IT8XXX2_IRQ_WU131 131 124 0 : #define IT8XXX2_IRQ_WU132 132 125 0 : #define IT8XXX2_IRQ_WU133 133 126 0 : #define IT8XXX2_IRQ_WU134 134 127 0 : #define IT8XXX2_IRQ_WU135 135 128 : /* Group 17 */ 129 0 : #define IT8XXX2_IRQ_WU136 136 130 0 : #define IT8XXX2_IRQ_WU137 137 131 0 : #define IT8XXX2_IRQ_WU138 138 132 0 : #define IT8XXX2_IRQ_WU139 139 133 0 : #define IT8XXX2_IRQ_WU140 140 134 0 : #define IT8XXX2_IRQ_WU141 141 135 0 : #define IT8XXX2_IRQ_WU142 142 136 0 : #define IT8XXX2_IRQ_WU143 143 137 : /* Group 18 */ 138 0 : #define IT8XXX2_IRQ_WU123 144 139 0 : #define IT8XXX2_IRQ_WU124 145 140 0 : #define IT8XXX2_IRQ_WU125 146 141 0 : #define IT8XXX2_IRQ_WU126 147 142 0 : #define IT8XXX2_IRQ_V_CMP 151 143 : /* Group 19 */ 144 0 : #define IT8XXX2_IRQ_SMB_E 152 145 0 : #define IT8XXX2_IRQ_SMB_F 153 146 0 : #define IT8XXX2_IRQ_TIMER3 155 147 0 : #define IT8XXX2_IRQ_TIMER4 156 148 0 : #define IT8XXX2_IRQ_TIMER5 157 149 0 : #define IT8XXX2_IRQ_TIMER6 158 150 0 : #define IT8XXX2_IRQ_TIMER7 159 151 : /* Group 20 */ 152 0 : #define IT8XXX2_IRQ_ESPI 162 153 0 : #define IT8XXX2_IRQ_ESPI_VW 163 154 0 : #define IT8XXX2_IRQ_PCH_P80 164 155 0 : #define IT8XXX2_IRQ_USBPD0 165 156 0 : #define IT8XXX2_IRQ_USBPD1 166 157 : /* Group 21 */ 158 0 : #define IT8XXX2_IRQ_USBPD2 174 159 : /* Group 22 */ 160 0 : #define IT8XXX2_IRQ_WU40 176 161 0 : #define IT8XXX2_IRQ_WU45 177 162 0 : #define IT8XXX2_IRQ_WU46 178 163 0 : #define IT8XXX2_IRQ_WU144 179 164 0 : #define IT8XXX2_IRQ_WU145 180 165 0 : #define IT8XXX2_IRQ_WU146 181 166 0 : #define IT8XXX2_IRQ_WU147 182 167 0 : #define IT8XXX2_IRQ_WU148 183 168 : /* Group 23 */ 169 0 : #define IT8XXX2_IRQ_WU149 184 170 0 : #define IT8XXX2_IRQ_WU150 185 171 : 172 0 : #define IT8XXX2_IRQ_COUNT (CONFIG_NUM_IRQS + 1) 173 : 174 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ */
