LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/interrupt-controller - ite-intc.h Coverage Total Hit
Test: new.info Lines: 0.0 % 143 0
Test Date: 2025-09-05 16:43:28

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
       3              :  * SPDX-License-Identifier: Apache-2.0
       4              :  */
       5              : 
       6              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
       7              : #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
       8              : 
       9            0 : #define IRQ_TYPE_NONE           0
      10            0 : #define IRQ_TYPE_EDGE_RISING    1
      11            0 : #define IRQ_TYPE_EDGE_FALLING   2
      12            0 : #define IRQ_TYPE_EDGE_BOTH      (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
      13            0 : #define IRQ_TYPE_LEVEL_HIGH     4
      14            0 : #define IRQ_TYPE_LEVEL_LOW      8
      15              : 
      16              : /* IRQ numbers of WUC */
      17              : /* Group 0 of INTC */
      18            0 : #define IT8XXX2_IRQ_WU20        1
      19            0 : #define IT8XXX2_IRQ_KBC_OBE     2
      20            0 : #define IT8XXX2_IRQ_SMB_D       4
      21            0 : #define IT8XXX2_IRQ_WKINTD      5
      22            0 : #define IT8XXX2_IRQ_WU23        6
      23              : /* Group 1 */
      24            0 : #define IT8XXX2_IRQ_SMB_A       9
      25            0 : #define IT8XXX2_IRQ_SMB_B       10
      26            0 : #define IT8XXX2_IRQ_WU26        12
      27            0 : #define IT8XXX2_IRQ_WKINTC      13
      28            0 : #define IT8XXX2_IRQ_WU25        14
      29              : /* Group 2 */
      30            0 : #define IT8XXX2_IRQ_SMB_C       16
      31            0 : #define IT8XXX2_IRQ_WU24        17
      32            0 : #define IT8XXX2_IRQ_WU22        21
      33            0 : #define IT8XXX2_IRQ_USB         23
      34              : /* Group 3 */
      35            0 : #define IT8XXX2_IRQ_KBC_IBF     24
      36            0 : #define IT8XXX2_IRQ_PMC1_IBF    25
      37            0 : #define IT8XXX2_IRQ_PMC2_IBF    27
      38            0 : #define IT8XXX2_IRQ_TIMER1      30
      39            0 : #define IT8XXX2_IRQ_WU21        31
      40              : /* Group 5 */
      41            0 : #define IT8XXX2_IRQ_WU50        40
      42            0 : #define IT8XXX2_IRQ_WU51        41
      43            0 : #define IT8XXX2_IRQ_WU52        42
      44            0 : #define IT8XXX2_IRQ_WU53        43
      45            0 : #define IT8XXX2_IRQ_WU54        44
      46            0 : #define IT8XXX2_IRQ_WU55        45
      47            0 : #define IT8XXX2_IRQ_WU56        46
      48            0 : #define IT8XXX2_IRQ_WU57        47
      49              : /* Group 6 */
      50            0 : #define IT8XXX2_IRQ_WU60        48
      51            0 : #define IT8XXX2_IRQ_WU61        49
      52            0 : #define IT8XXX2_IRQ_WU62        50
      53            0 : #define IT8XXX2_IRQ_WU63        51
      54            0 : #define IT8XXX2_IRQ_WU64        52
      55            0 : #define IT8XXX2_IRQ_WU65        53
      56            0 : #define IT8XXX2_IRQ_WU66        54
      57            0 : #define IT8XXX2_IRQ_WU67        55
      58              : /* Group 7 */
      59            0 : #define IT8XXX2_IRQ_TIMER2      58
      60              : /* Group 8 */
      61            0 : #define IT8XXX2_IRQ_PMC3_IBF    67
      62            0 : #define IT8XXX2_IRQ_PMC4_IBF    69
      63              : /* Group 9 */
      64            0 : #define IT8XXX2_IRQ_WU70        72
      65            0 : #define IT8XXX2_IRQ_WU71        73
      66            0 : #define IT8XXX2_IRQ_WU72        74
      67            0 : #define IT8XXX2_IRQ_WU73        75
      68            0 : #define IT8XXX2_IRQ_WU74        76
      69            0 : #define IT8XXX2_IRQ_WU75        77
      70            0 : #define IT8XXX2_IRQ_WU76        78
      71            0 : #define IT8XXX2_IRQ_WU77        79
      72              : /* Group 10 */
      73            0 : #define IT8XXX2_IRQ_TIMER8      80
      74            0 : #define IT8XXX2_IRQ_WU88        85
      75            0 : #define IT8XXX2_IRQ_WU89        86
      76            0 : #define IT8XXX2_IRQ_WU90        87
      77              : /* Group 11 */
      78            0 : #define IT8XXX2_IRQ_WU80        88
      79            0 : #define IT8XXX2_IRQ_WU81        89
      80            0 : #define IT8XXX2_IRQ_WU82        90
      81            0 : #define IT8XXX2_IRQ_WU83        91
      82            0 : #define IT8XXX2_IRQ_WU84        92
      83            0 : #define IT8XXX2_IRQ_WU85        93
      84            0 : #define IT8XXX2_IRQ_WU86        94
      85            0 : #define IT8XXX2_IRQ_WU87        95
      86              : /* Group 12 */
      87            0 : #define IT8XXX2_IRQ_WU91        96
      88            0 : #define IT8XXX2_IRQ_WU92        97
      89            0 : #define IT8XXX2_IRQ_WU93        98
      90            0 : #define IT8XXX2_IRQ_WU94        99
      91            0 : #define IT8XXX2_IRQ_WU95        100
      92            0 : #define IT8XXX2_IRQ_WU96        101
      93            0 : #define IT8XXX2_IRQ_WU97        102
      94            0 : #define IT8XXX2_IRQ_WU98        103
      95              : /* Group 13 */
      96            0 : #define IT8XXX2_IRQ_WU99        104
      97            0 : #define IT8XXX2_IRQ_WU100       105
      98            0 : #define IT8XXX2_IRQ_WU101       106
      99            0 : #define IT8XXX2_IRQ_WU102       107
     100            0 : #define IT8XXX2_IRQ_WU103       108
     101            0 : #define IT8XXX2_IRQ_WU104       109
     102            0 : #define IT8XXX2_IRQ_WU105       110
     103            0 : #define IT8XXX2_IRQ_WU106       111
     104              : /* Group 14 */
     105            0 : #define IT8XXX2_IRQ_WU107       112
     106            0 : #define IT8XXX2_IRQ_WU108       113
     107            0 : #define IT8XXX2_IRQ_WU109       114
     108            0 : #define IT8XXX2_IRQ_WU110       115
     109            0 : #define IT8XXX2_IRQ_WU111       116
     110            0 : #define IT8XXX2_IRQ_WU112       117
     111            0 : #define IT8XXX2_IRQ_WU113       118
     112            0 : #define IT8XXX2_IRQ_WU114       119
     113              : /* Group 15 */
     114            0 : #define IT8XXX2_IRQ_WU115       120
     115            0 : #define IT8XXX2_IRQ_WU116       121
     116            0 : #define IT8XXX2_IRQ_WU117       122
     117            0 : #define IT8XXX2_IRQ_WU118       123
     118            0 : #define IT8XXX2_IRQ_WU119       124
     119            0 : #define IT8XXX2_IRQ_WU120       125
     120            0 : #define IT8XXX2_IRQ_WU121       126
     121            0 : #define IT8XXX2_IRQ_WU122       127
     122              : /* Group 16 */
     123            0 : #define IT8XXX2_IRQ_WU128       128
     124            0 : #define IT8XXX2_IRQ_WU129       129
     125            0 : #define IT8XXX2_IRQ_WU130       130
     126            0 : #define IT8XXX2_IRQ_WU131       131
     127            0 : #define IT8XXX2_IRQ_WU132       132
     128            0 : #define IT8XXX2_IRQ_WU133       133
     129            0 : #define IT8XXX2_IRQ_WU134       134
     130            0 : #define IT8XXX2_IRQ_WU135       135
     131              : /* Group 17 */
     132            0 : #define IT8XXX2_IRQ_WU136       136
     133            0 : #define IT8XXX2_IRQ_WU137       137
     134            0 : #define IT8XXX2_IRQ_WU138       138
     135            0 : #define IT8XXX2_IRQ_WU139       139
     136            0 : #define IT8XXX2_IRQ_WU140       140
     137            0 : #define IT8XXX2_IRQ_WU141       141
     138            0 : #define IT8XXX2_IRQ_WU142       142
     139            0 : #define IT8XXX2_IRQ_WU143       143
     140              : /* Group 18 */
     141            0 : #define IT8XXX2_IRQ_WU123       144
     142            0 : #define IT8XXX2_IRQ_WU124       145
     143            0 : #define IT8XXX2_IRQ_WU125       146
     144            0 : #define IT8XXX2_IRQ_WU126       147
     145            0 : #define IT8XXX2_IRQ_PMC5_IBF    150
     146            0 : #define IT8XXX2_IRQ_V_CMP       151
     147              : /* Group 19 */
     148            0 : #define IT8XXX2_IRQ_SMB_E       152
     149            0 : #define IT8XXX2_IRQ_SMB_F       153
     150            0 : #define IT8XXX2_IRQ_TIMER3      155
     151            0 : #define IT8XXX2_IRQ_TIMER4      156
     152            0 : #define IT8XXX2_IRQ_TIMER5      157
     153            0 : #define IT8XXX2_IRQ_TIMER6      158
     154            0 : #define IT8XXX2_IRQ_TIMER7      159
     155              : /* Group 20 */
     156            0 : #define IT8XXX2_IRQ_ESPI        162
     157            0 : #define IT8XXX2_IRQ_ESPI_VW     163
     158            0 : #define IT8XXX2_IRQ_PCH_P80     164
     159            0 : #define IT8XXX2_IRQ_USBPD0      165
     160            0 : #define IT8XXX2_IRQ_USBPD1      166
     161              : /* Group 21 */
     162            0 : #define IT8XXX2_IRQ_USBPD2      174
     163              : /* Group 22 */
     164            0 : #define IT8XXX2_IRQ_WU40        176
     165            0 : #define IT8XXX2_IRQ_WU45        177
     166            0 : #define IT8XXX2_IRQ_WU46        178
     167            0 : #define IT8XXX2_IRQ_WU144       179
     168            0 : #define IT8XXX2_IRQ_WU145       180
     169            0 : #define IT8XXX2_IRQ_WU146       181
     170            0 : #define IT8XXX2_IRQ_WU147       182
     171            0 : #define IT8XXX2_IRQ_WU148       183
     172              : /* Group 23 */
     173            0 : #define IT8XXX2_IRQ_WU149       184
     174            0 : #define IT8XXX2_IRQ_WU150       185
     175              : 
     176            0 : #define IT8XXX2_IRQ_COUNT       (CONFIG_NUM_IRQS + 1)
     177              : 
     178              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ */
        

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