Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
9 :
10 0 : #define IRQ_TYPE_NONE 0
11 0 : #define IRQ_TYPE_EDGE_RISING 1
12 0 : #define IRQ_TYPE_EDGE_FALLING 2
13 0 : #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
14 0 : #define IRQ_TYPE_LEVEL_HIGH 4
15 0 : #define IRQ_TYPE_LEVEL_LOW 8
16 :
17 : /* IRQ numbers of WUC */
18 : /* Group 0 of INTC */
19 0 : #define IT51XXX_IRQ_WU20 1
20 0 : #define IT51XXX_IRQ_KBC_OBE 2
21 0 : #define IT51XXX_IRQ_SMB_D 4
22 0 : #define IT51XXX_IRQ_WKINTD 5
23 0 : #define IT51XXX_IRQ_WU23 6
24 : /* Group 1 */
25 0 : #define IT51XXX_IRQ_SMB_A 9
26 0 : #define IT51XXX_IRQ_SMB_B 10
27 0 : #define IT51XXX_IRQ_WU26 12
28 0 : #define IT51XXX_IRQ_WKINTC 13
29 0 : #define IT51XXX_IRQ_WU25 14
30 : /* Group 2 */
31 0 : #define IT51XXX_IRQ_SMB_C 16
32 0 : #define IT51XXX_IRQ_WU24 17
33 0 : #define IT51XXX_IRQ_WU22 21
34 : /* Group 3 */
35 0 : #define IT51XXX_IRQ_KBC_IBF 24
36 0 : #define IT51XXX_IRQ_PMC1_IBF 25
37 0 : #define IT51XXX_IRQ_PMC2_IBF 27
38 0 : #define IT51XXX_IRQ_TIMER1 30
39 0 : #define IT51XXX_IRQ_WU21 31
40 : /* Group 4 */
41 0 : #define IT51XXX_IRQ_SPI 37
42 : /* Group 5 */
43 0 : #define IT51XXX_IRQ_WU50 40
44 0 : #define IT51XXX_IRQ_WU51 41
45 0 : #define IT51XXX_IRQ_WU52 42
46 0 : #define IT51XXX_IRQ_WU53 43
47 0 : #define IT51XXX_IRQ_WU54 44
48 0 : #define IT51XXX_IRQ_WU55 45
49 0 : #define IT51XXX_IRQ_WU56 46
50 0 : #define IT51XXX_IRQ_WU57 47
51 : /* Group 6 */
52 0 : #define IT51XXX_IRQ_WU60 48
53 0 : #define IT51XXX_IRQ_WU61 49
54 0 : #define IT51XXX_IRQ_WU62 50
55 0 : #define IT51XXX_IRQ_WU63 51
56 0 : #define IT51XXX_IRQ_WU64 52
57 0 : #define IT51XXX_IRQ_WU65 53
58 0 : #define IT51XXX_IRQ_WU66 54
59 0 : #define IT51XXX_IRQ_WU67 55
60 : /* Group 7 */
61 0 : #define IT51XXX_IRQ_TIMER2 58
62 : /* Group 8 */
63 0 : #define IT51XXX_IRQ_PMC3_IBF 67
64 0 : #define IT51XXX_IRQ_PMC4_IBF 69
65 : /* Group 9 */
66 0 : #define IT51XXX_IRQ_WU70 72
67 0 : #define IT51XXX_IRQ_WU71 73
68 0 : #define IT51XXX_IRQ_WU72 74
69 0 : #define IT51XXX_IRQ_WU73 75
70 0 : #define IT51XXX_IRQ_WU74 76
71 0 : #define IT51XXX_IRQ_WU75 77
72 0 : #define IT51XXX_IRQ_WU76 78
73 0 : #define IT51XXX_IRQ_WU77 79
74 : /* Group 10 */
75 0 : #define IT51XXX_IRQ_WU88 85
76 0 : #define IT51XXX_IRQ_WU89 86
77 0 : #define IT51XXX_IRQ_WU90 87
78 : /* Group 11 */
79 0 : #define IT51XXX_IRQ_WU80 88
80 0 : #define IT51XXX_IRQ_WU81 89
81 0 : #define IT51XXX_IRQ_WU82 90
82 0 : #define IT51XXX_IRQ_WU83 91
83 0 : #define IT51XXX_IRQ_WU84 92
84 0 : #define IT51XXX_IRQ_WU85 93
85 0 : #define IT51XXX_IRQ_WU86 94
86 0 : #define IT51XXX_IRQ_WU87 95
87 : /* Group 12 */
88 0 : #define IT51XXX_IRQ_WU91 96
89 0 : #define IT51XXX_IRQ_WU92 97
90 0 : #define IT51XXX_IRQ_WU93 98
91 0 : #define IT51XXX_IRQ_WU95 100
92 0 : #define IT51XXX_IRQ_WU96 101
93 0 : #define IT51XXX_IRQ_WU97 102
94 0 : #define IT51XXX_IRQ_WU98 103
95 : /* Group 13 */
96 0 : #define IT51XXX_IRQ_WU99 104
97 0 : #define IT51XXX_IRQ_WU100 105
98 0 : #define IT51XXX_IRQ_WU101 106
99 0 : #define IT51XXX_IRQ_WU102 107
100 0 : #define IT51XXX_IRQ_WU103 108
101 0 : #define IT51XXX_IRQ_WU104 109
102 0 : #define IT51XXX_IRQ_WU105 110
103 0 : #define IT51XXX_IRQ_WU106 111
104 : /* Group 14 */
105 0 : #define IT51XXX_IRQ_WU107 112
106 0 : #define IT51XXX_IRQ_WU108 113
107 0 : #define IT51XXX_IRQ_WU109 114
108 0 : #define IT51XXX_IRQ_WU110 115
109 0 : #define IT51XXX_IRQ_WU111 116
110 0 : #define IT51XXX_IRQ_WU112 117
111 0 : #define IT51XXX_IRQ_WU113 118
112 0 : #define IT51XXX_IRQ_WU114 119
113 : /* Group 15 */
114 0 : #define IT51XXX_IRQ_WU115 120
115 0 : #define IT51XXX_IRQ_WU116 121
116 0 : #define IT51XXX_IRQ_WU117 122
117 0 : #define IT51XXX_IRQ_WU118 123
118 0 : #define IT51XXX_IRQ_WU119 124
119 0 : #define IT51XXX_IRQ_WU120 125
120 0 : #define IT51XXX_IRQ_WU121 126
121 0 : #define IT51XXX_IRQ_WU122 127
122 : /* Group 16 */
123 0 : #define IT51XXX_IRQ_WU128 128
124 0 : #define IT51XXX_IRQ_WU129 129
125 0 : #define IT51XXX_IRQ_WU131 131
126 0 : #define IT51XXX_IRQ_WU132 132
127 0 : #define IT51XXX_IRQ_WU133 133
128 0 : #define IT51XXX_IRQ_WU134 134
129 0 : #define IT51XXX_IRQ_WU135 135
130 : /* Group 17 */
131 0 : #define IT51XXX_IRQ_WU136 136
132 0 : #define IT51XXX_IRQ_WU137 137
133 0 : #define IT51XXX_IRQ_WU138 138
134 0 : #define IT51XXX_IRQ_WU139 139
135 0 : #define IT51XXX_IRQ_WU140 140
136 0 : #define IT51XXX_IRQ_WU141 141
137 0 : #define IT51XXX_IRQ_WU142 142
138 : /* Group 18 */
139 0 : #define IT51XXX_IRQ_WU127 148
140 0 : #define IT51XXX_IRQ_PMC5_IBF 150
141 0 : #define IT51XXX_IRQ_V_CMP 151
142 : /* Group 19 */
143 0 : #define IT51XXX_IRQ_PECI 152
144 0 : #define IT51XXX_IRQ_ESPI 153
145 0 : #define IT51XXX_IRQ_ESPI_VW 154
146 0 : #define IT51XXX_IRQ_PCH_P80 155
147 0 : #define IT51XXX_IRQ_TIMER3 157
148 0 : #define IT51XXX_IRQ_PLL_CHANGE 159
149 : /* Group 20 */
150 0 : #define IT51XXX_IRQ_SMB_E 160
151 0 : #define IT51XXX_IRQ_SMB_F 161
152 0 : #define IT51XXX_IRQ_WU40 163
153 0 : #define IT51XXX_IRQ_WU45 166
154 : /* Group 21 */
155 0 : #define IT51XXX_IRQ_WU46 168
156 0 : #define IT51XXX_IRQ_WU144 170
157 0 : #define IT51XXX_IRQ_WU145 171
158 0 : #define IT51XXX_IRQ_WU146 172
159 0 : #define IT51XXX_IRQ_WU147 173
160 0 : #define IT51XXX_IRQ_TIMER4 175
161 : /* Group 22 */
162 0 : #define IT51XXX_IRQ_WU148 176
163 0 : #define IT51XXX_IRQ_WU149 177
164 0 : #define IT51XXX_IRQ_WU150 178
165 0 : #define IT51XXX_IRQ_WU151 179
166 0 : #define IT51XXX_IRQ_I3C_M0 180
167 0 : #define IT51XXX_IRQ_I3C_M1 181
168 0 : #define IT51XXX_IRQ_I3C_S0 182
169 0 : #define IT51XXX_IRQ_I3C_S1 183
170 : /* Group 25 */
171 0 : #define IT51XXX_IRQ_SMB_SC 203
172 0 : #define IT51XXX_IRQ_SMB_SB 204
173 0 : #define IT51XXX_IRQ_SMB_SA 205
174 0 : #define IT51XXX_IRQ_TIMER1_DW 207
175 : /* Group 26 */
176 0 : #define IT51XXX_IRQ_TIMER2_DW 208
177 0 : #define IT51XXX_IRQ_TIMER3_DW 209
178 0 : #define IT51XXX_IRQ_TIMER4_DW 210
179 0 : #define IT51XXX_IRQ_TIMER5_DW 211
180 0 : #define IT51XXX_IRQ_TIMER6_DW 212
181 0 : #define IT51XXX_IRQ_TIMER7_DW 213
182 0 : #define IT51XXX_IRQ_TIMER8_DW 214
183 : /* Group 27 */
184 0 : #define IT51XXX_IRQ_PWM_TACH0 219
185 0 : #define IT51XXX_IRQ_PWM_TACH1 220
186 0 : #define IT51XXX_IRQ_PWM_TACH2 221
187 0 : #define IT51XXX_IRQ_SMB_G 222
188 0 : #define IT51XXX_IRQ_SMB_H 223
189 : /* Group 28 */
190 0 : #define IT51XXX_IRQ_SMB_I 224
191 :
192 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ */
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