Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef ZEPHYR_DT_BINDINGS_INTERRUPT_CONTROLLER_RENESAS_RA_ICU_H_
       8             : #define ZEPHYR_DT_BINDINGS_INTERRUPT_CONTROLLER_RENESAS_RA_ICU_H_
       9             : 
      10           0 : #define RA_ICU_IRQ_UNSPECIFIED (-1)
      11             : 
      12           0 : #define RA_ICU_PORT_IRQ0       (1 << 8)
      13           0 : #define RA_ICU_PORT_IRQ1       (2 << 8)
      14           0 : #define RA_ICU_PORT_IRQ2       (3 << 8)
      15           0 : #define RA_ICU_PORT_IRQ3       (4 << 8)
      16           0 : #define RA_ICU_PORT_IRQ4       (5 << 8)
      17           0 : #define RA_ICU_PORT_IRQ5       (6 << 8)
      18           0 : #define RA_ICU_PORT_IRQ6       (7 << 8)
      19           0 : #define RA_ICU_PORT_IRQ7       (8 << 8)
      20           0 : #define RA_ICU_PORT_IRQ8       (9 << 8)
      21           0 : #define RA_ICU_PORT_IRQ9       (10 << 8)
      22           0 : #define RA_ICU_PORT_IRQ10      (11 << 8)
      23           0 : #define RA_ICU_PORT_IRQ11      (12 << 8)
      24           0 : #define RA_ICU_PORT_IRQ12      (13 << 8)
      25           0 : #define RA_ICU_PORT_IRQ14      (15 << 8)
      26           0 : #define RA_ICU_PORT_IRQ15      (16 << 8)
      27           0 : #define RA_ICU_DMAC0_INT       (17 << 8)
      28           0 : #define RA_ICU_DMAC1_INT       (18 << 8)
      29           0 : #define RA_ICU_DMAC2_INT       (19 << 8)
      30           0 : #define RA_ICU_DMAC3_INT       (20 << 8)
      31           0 : #define RA_ICU_DTC_COMPLETE    (21 << 8)
      32           0 : #define RA_ICU_ICU_SNZCANCEL   (23 << 8)
      33           0 : #define RA_ICU_FCU_FRDYI       (24 << 8)
      34           0 : #define RA_ICU_LVD_LVD1        (25 << 8)
      35           0 : #define RA_ICU_LVD_LVD2        (26 << 8)
      36           0 : #define RA_ICU_VBATT_LVD       (27 << 8)
      37           0 : #define RA_ICU_MOSC_STOP       (28 << 8)
      38           0 : #define RA_ICU_SYSTEM_SNZREQ   (29 << 8)
      39           0 : #define RA_ICU_AGT0_AGTI       (30 << 8)
      40           0 : #define RA_ICU_AGT0_AGTCMAI    (31 << 8)
      41           0 : #define RA_ICU_AGT0_AGTCMBI    (32 << 8)
      42           0 : #define RA_ICU_AGT1_AGTI       (33 << 8)
      43           0 : #define RA_ICU_AGT1_AGTCMAI    (34 << 8)
      44           0 : #define RA_ICU_AGT1_AGTCMBI    (35 << 8)
      45           0 : #define RA_ICU_IWDT_NMIUNDF    (36 << 8)
      46           0 : #define RA_ICU_WDT_NMIUNDF     (37 << 8)
      47           0 : #define RA_ICU_RTC_ALM         (38 << 8)
      48           0 : #define RA_ICU_RTC_PRD         (39 << 8)
      49           0 : #define RA_ICU_RTC_CUP         (40 << 8)
      50           0 : #define RA_ICU_ADC140_ADI      (41 << 8)
      51           0 : #define RA_ICU_ADC140_GBADI    (42 << 8)
      52           0 : #define RA_ICU_ADC140_CMPAI    (43 << 8)
      53           0 : #define RA_ICU_ADC140_CMPBI    (44 << 8)
      54           0 : #define RA_ICU_ADC140_WCMPM    (45 << 8)
      55           0 : #define RA_ICU_ADC140_WCMPUM   (46 << 8)
      56           0 : #define RA_ICU_ACMP_LP0        (47 << 8)
      57           0 : #define RA_ICU_ACMP_LP1        (48 << 8)
      58           0 : #define RA_ICU_USBFS_D0FIFO    (49 << 8)
      59           0 : #define RA_ICU_USBFS_D1FIFO    (50 << 8)
      60           0 : #define RA_ICU_USBFS_USBI      (51 << 8)
      61           0 : #define RA_ICU_USBFS_USBR      (52 << 8)
      62           0 : #define RA_ICU_IIC0_RXI        (53 << 8)
      63           0 : #define RA_ICU_IIC0_TXI        (54 << 8)
      64           0 : #define RA_ICU_IIC0_TEI        (55 << 8)
      65           0 : #define RA_ICU_IIC0_EEI        (56 << 8)
      66           0 : #define RA_ICU_IIC0_WUI        (57 << 8)
      67           0 : #define RA_ICU_IIC1_RXI        (58 << 8)
      68           0 : #define RA_ICU_IIC1_TXI        (59 << 8)
      69           0 : #define RA_ICU_IIC1_TEI        (60 << 8)
      70           0 : #define RA_ICU_IIC1_EEI        (61 << 8)
      71           0 : #define RA_ICU_SSIE0_SSITXI    (62 << 8)
      72           0 : #define RA_ICU_SSIE0_SSIRXI    (63 << 8)
      73             : 
      74           0 : #define RA_ICU_SSIE0_SSIF      (65 << 8)
      75           0 : #define RA_ICU_CTSU_CTSUWR     (66 << 8)
      76           0 : #define RA_ICU_CTSU_CTSURD     (67 << 8)
      77           0 : #define RA_ICU_CTSU_CTSUFN     (68 << 8)
      78           0 : #define RA_ICU_KEY_INTKR       (69 << 8)
      79           0 : #define RA_ICU_DOC_DOPCI       (70 << 8)
      80           0 : #define RA_ICU_CAC_FERRI       (71 << 8)
      81           0 : #define RA_ICU_CAC_MENDI       (72 << 8)
      82           0 : #define RA_ICU_CAC_OVFI        (73 << 8)
      83           0 : #define RA_ICU_CAN0_ERS        (74 << 8)
      84           0 : #define RA_ICU_CAN0_RXF        (75 << 8)
      85           0 : #define RA_ICU_CAN0_TXF        (76 << 8)
      86           0 : #define RA_ICU_CAN0_RXM        (77 << 8)
      87           0 : #define RA_ICU_CAN0_TXM        (78 << 8)
      88           0 : #define RA_ICU_IOPORT_GROUP1   (70 << 8)
      89           0 : #define RA_ICU_IOPORT_GROUP2   (80 << 8)
      90           0 : #define RA_ICU_IOPORT_GROUP3   (81 << 8)
      91           0 : #define RA_ICU_IOPORT_GROUP4   (82 << 8)
      92           0 : #define RA_ICU_ELC_SWEVT0      (83 << 8)
      93           0 : #define RA_ICU_ELC_SWEVT1      (84 << 8)
      94           0 : #define RA_ICU_POEG_GROUP0     (85 << 8)
      95           0 : #define RA_ICU_POEG_GROUP1     (86 << 8)
      96           0 : #define RA_ICU_GPT0_CCMPA      (87 << 8)
      97           0 : #define RA_ICU_GPT0_CCMPB      (88 << 8)
      98           0 : #define RA_ICU_GPT0_CMPC       (89 << 8)
      99           0 : #define RA_ICU_GPT0_CMPD       (90 << 8)
     100           0 : #define RA_ICU_GPT0_CMPE       (91 << 8)
     101           0 : #define RA_ICU_GPT0_CMPF       (92 << 8)
     102           0 : #define RA_ICU_GPT0_OVF        (93 << 8)
     103           0 : #define RA_ICU_GPT0_UDF        (94 << 8)
     104           0 : #define RA_ICU_GPT1_CCMPA      (95 << 8)
     105           0 : #define RA_ICU_GPT1_CCMPB      (96 << 8)
     106           0 : #define RA_ICU_GPT1_CMPC       (97 << 8)
     107           0 : #define RA_ICU_GPT1_CMPD       (98 << 8)
     108           0 : #define RA_ICU_GPT1_CMPE       (99 << 8)
     109           0 : #define RA_ICU_GPT1_CMPF       (100 << 8)
     110           0 : #define RA_ICU_GPT1_OVF        (101 << 8)
     111           0 : #define RA_ICU_GPT1_UDF        (102 << 8)
     112           0 : #define RA_ICU_GPT2_CCMPA      (103 << 8)
     113           0 : #define RA_ICU_GPT2_CCMPB      (104 << 8)
     114           0 : #define RA_ICU_GPT2_CMPC       (105 << 8)
     115           0 : #define RA_ICU_GPT2_CMPD       (106 << 8)
     116           0 : #define RA_ICU_GPT2_CMPE       (107 << 8)
     117           0 : #define RA_ICU_GPT2_CMPF       (108 << 8)
     118           0 : #define RA_ICU_GPT2_OVF        (109 << 8)
     119           0 : #define RA_ICU_GPT2_UDF        (110 << 8)
     120           0 : #define RA_ICU_GPT3_CCMPA      (111 << 8)
     121           0 : #define RA_ICU_GPT3_CCMPB      (112 << 8)
     122           0 : #define RA_ICU_GPT3_CMPC       (113 << 8)
     123           0 : #define RA_ICU_GPT3_CMPD       (114 << 8)
     124           0 : #define RA_ICU_GPT3_CMPE       (115 << 8)
     125           0 : #define RA_ICU_GPT3_CMPF       (116 << 8)
     126           0 : #define RA_ICU_GPT3_OVF        (117 << 8)
     127           0 : #define RA_ICU_GPT3_UDF        (118 << 8)
     128           0 : #define RA_ICU_GPT4_CCMPA      (119 << 8)
     129           0 : #define RA_ICU_GPT4_CCMPB      (120 << 8)
     130           0 : #define RA_ICU_GPT4_CMPC       (121 << 8)
     131           0 : #define RA_ICU_GPT4_CMPD       (122 << 8)
     132           0 : #define RA_ICU_GPT4_CMPE       (123 << 8)
     133           0 : #define RA_ICU_GPT4_CMPF       (124 << 8)
     134           0 : #define RA_ICU_GPT4_OVF        (125 << 8)
     135           0 : #define RA_ICU_GPT4_UDF        (126 << 8)
     136           0 : #define RA_ICU_GPT5_CCMPA      (127 << 8)
     137           0 : #define RA_ICU_GPT5_CCMPB      (128 << 8)
     138           0 : #define RA_ICU_GPT5_CMPC       (129 << 8)
     139           0 : #define RA_ICU_GPT5_CMPD       (130 << 8)
     140           0 : #define RA_ICU_GPT5_CMPE       (131 << 8)
     141           0 : #define RA_ICU_GPT5_CMPF       (132 << 8)
     142           0 : #define RA_ICU_GPT5_OVF        (133 << 8)
     143           0 : #define RA_ICU_GPT5_UDF        (134 << 8)
     144           0 : #define RA_ICU_GPT6_CCMPA      (135 << 8)
     145           0 : #define RA_ICU_GPT6_CCMPB      (136 << 8)
     146           0 : #define RA_ICU_GPT6_CMPC       (137 << 8)
     147           0 : #define RA_ICU_GPT6_CMPD       (138 << 8)
     148           0 : #define RA_ICU_GPT6_CMPE       (139 << 8)
     149           0 : #define RA_ICU_GPT6_CMPF       (140 << 8)
     150           0 : #define RA_ICU_GPT6_OVF        (141 << 8)
     151           0 : #define RA_ICU_GPT6_UDF        (142 << 8)
     152           0 : #define RA_ICU_GPT7_CCMPA      (143 << 8)
     153           0 : #define RA_ICU_GPT7_CCMPB      (144 << 8)
     154           0 : #define RA_ICU_GPT7_CMPC       (145 << 8)
     155           0 : #define RA_ICU_GPT7_CMPD       (146 << 8)
     156           0 : #define RA_ICU_GPT7_CMPE       (147 << 8)
     157           0 : #define RA_ICU_GPT7_CMPF       (148 << 8)
     158           0 : #define RA_ICU_GPT7_OVF        (149 << 8)
     159           0 : #define RA_ICU_GPT7_UDF        (150 << 8)
     160           0 : #define RA_ICU_GPT_UVWEDGE     (151 << 8)
     161           0 : #define RA_ICU_SCI0_RXI        (152 << 8)
     162           0 : #define RA_ICU_SCI0_TXI        (153 << 8)
     163           0 : #define RA_ICU_SCI0_TEI        (154 << 8)
     164           0 : #define RA_ICU_SCI0_ERI        (155 << 8)
     165           0 : #define RA_ICU_SCI0_AM         (156 << 8)
     166           0 : #define RA_ICU_SCI0_RXI_OR_ERI (157 << 8)
     167           0 : #define RA_ICU_SCI1_RXI        (158 << 8)
     168           0 : #define RA_ICU_SCI1_TXI        (159 << 8)
     169           0 : #define RA_ICU_SCI1_TEI        (160 << 8)
     170           0 : #define RA_ICU_SCI1_ERI        (161 << 8)
     171           0 : #define RA_ICU_SCI1_AM         (162 << 8)
     172           0 : #define RA_ICU_SCI2_RXI        (163 << 8)
     173           0 : #define RA_ICU_SCI2_TXI        (164 << 8)
     174           0 : #define RA_ICU_SCI2_TEI        (165 << 8)
     175           0 : #define RA_ICU_SCI2_ERI        (166 << 8)
     176           0 : #define RA_ICU_SCI2_AM         (167 << 8)
     177           0 : #define RA_ICU_SCI9_RXI        (168 << 8)
     178           0 : #define RA_ICU_SCI9_TXI        (169 << 8)
     179           0 : #define RA_ICU_SCI9_TEI        (170 << 8)
     180           0 : #define RA_ICU_SCI9_ERI        (171 << 8)
     181           0 : #define RA_ICU_SCI9_AM         (172 << 8)
     182           0 : #define RA_ICU_SPI0_SPRI       (173 << 8)
     183           0 : #define RA_ICU_SPI0_SPTI       (174 << 8)
     184           0 : #define RA_ICU_SPI0_SPII       (175 << 8)
     185           0 : #define RA_ICU_SPI0_SPEI       (176 << 8)
     186           0 : #define RA_ICU_SPI0_SPTEND     (177 << 8)
     187           0 : #define RA_ICU_SPI1_SPRI       (178 << 8)
     188           0 : #define RA_ICU_SPI1_SPTI       (179 << 8)
     189           0 : #define RA_ICU_SPI1_SPII       (180 << 8)
     190           0 : #define RA_ICU_SPI1_SPEI       (181 << 8)
     191           0 : #define RA_ICU_SPI1_SPTEND     (182 << 8)
     192             : 
     193             : #endif /* ZEPHYR_DT_BINDINGS_INTERRUPT_CONTROLLER_RENESAS_RA_ICU_H_ */