Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2023 Carlo Caione <ccaione@baylibre.com>
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_XTENSA_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_XTENSA_H_
       8             : 
       9             : #include <zephyr/sys/util_macro.h>
      10             : #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
      11             : 
      12             : /*
      13             :  * Architecture specific Xtensa related attributes.
      14             :  */
      15           0 : #define DT_MEM_XTENSA_MASK              DT_MEM_ARCH_ATTR_MASK
      16           0 : #define DT_MEM_XTENSA_GET(x)            ((x) & DT_MEM_XTENSA_MASK)
      17           0 : #define DT_MEM_XTENSA(x)                ((x) << DT_MEM_ARCH_ATTR_SHIFT)
      18             : 
      19           0 : #define  ATTR_XTENSA_INSTR_ROM          BIT(0)
      20           0 : #define  ATTR_XTENSA_INSTR_RAM          BIT(1)
      21           0 : #define  ATTR_XTENSA_DATA_ROM           BIT(2)
      22           0 : #define  ATTR_XTENSA_DATA_RAM           BIT(3)
      23           0 : #define  ATTR_XTENSA_XLMI               BIT(4)
      24             : 
      25           0 : #define DT_MEM_XTENSA_INSTR_ROM         DT_MEM_XTENSA(ATTR_XTENSA_INSTR_ROM)
      26           0 : #define DT_MEM_XTENSA_INSTR_RAM         DT_MEM_XTENSA(ATTR_XTENSA_INSTR_RAM)
      27           0 : #define DT_MEM_XTENSA_DATA_ROM          DT_MEM_XTENSA(ATTR_XTENSA_DATA_ROM)
      28           0 : #define DT_MEM_XTENSA_DATA_RAM          DT_MEM_XTENSA(ATTR_XTENSA_DATA_RAM)
      29           0 : #define DT_MEM_XTENSA_XLMI              DT_MEM_XTENSA(ATTR_XTENSA_XLMI)
      30           0 : #define DT_MEM_XTENSA_UNKNOWN           DT_MEM_ARCH_ATTR_UNKNOWN
      31             : 
      32             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_XTENSA_H_ */