Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2024 Renesas Electronics Corporation
       3             :  * SPDX-License-Identifier: Apache-2.0
       4             :  */
       5             : 
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_
       8             : 
       9           0 : #define SDRAM_TRAS_1CYCLES (1)
      10           0 : #define SDRAM_TRAS_2CYCLES (2)
      11           0 : #define SDRAM_TRAS_3CYCLES (3)
      12           0 : #define SDRAM_TRAS_4CYCLES (4)
      13           0 : #define SDRAM_TRAS_5CYCLES (5)
      14           0 : #define SDRAM_TRAS_6CYCLES (6)
      15           0 : #define SDRAM_TRAS_7CYCLES (7)
      16             : 
      17           0 : #define SDRAM_TRCD_1CYCLES (1)
      18           0 : #define SDRAM_TRCD_2CYCLES (2)
      19           0 : #define SDRAM_TRCD_3CYCLES (3)
      20           0 : #define SDRAM_TRCD_4CYCLES (4)
      21             : 
      22           0 : #define SDRAM_TRP_1CYCLES (1)
      23           0 : #define SDRAM_TRP_2CYCLES (2)
      24           0 : #define SDRAM_TRP_3CYCLES (3)
      25           0 : #define SDRAM_TRP_4CYCLES (4)
      26           0 : #define SDRAM_TRP_5CYCLES (5)
      27           0 : #define SDRAM_TRP_6CYCLES (6)
      28           0 : #define SDRAM_TRP_7CYCLES (7)
      29           0 : #define SDRAM_TRP_8CYCLES (8)
      30             : 
      31           0 : #define SDRAM_TWR_1CYCLES (1)
      32           0 : #define SDRAM_TWR_2CYCLES (2)
      33             : 
      34           0 : #define SDRAM_TCL_1CYCLES (1)
      35           0 : #define SDRAM_TCL_2CYCLES (2)
      36           0 : #define SDRAM_TCL_3CYCLES (3)
      37             : 
      38           0 : #define SDRAM_TREFW_1CYCLES  (1)
      39           0 : #define SDRAM_TREFW_2CYCLES  (2)
      40           0 : #define SDRAM_TREFW_3CYCLES  (3)
      41           0 : #define SDRAM_TREFW_4CYCLES  (4)
      42           0 : #define SDRAM_TREFW_5CYCLES  (5)
      43           0 : #define SDRAM_TREFW_6CYCLES  (6)
      44           0 : #define SDRAM_TREFW_7CYCLES  (7)
      45           0 : #define SDRAM_TREFW_8CYCLES  (8)
      46           0 : #define SDRAM_TREFW_9CYCLES  (9)
      47           0 : #define SDRAM_TREFW_10CYCLES (10)
      48           0 : #define SDRAM_TREFW_11CYCLES (11)
      49           0 : #define SDRAM_TREFW_12CYCLES (12)
      50           0 : #define SDRAM_TREFW_13CYCLES (13)
      51           0 : #define SDRAM_TREFW_14CYCLES (14)
      52           0 : #define SDRAM_TREFW_15CYCLES (15)
      53           0 : #define SDRAM_TREFW_16CYCLES (16)
      54             : 
      55           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_3CYCLES  (3)
      56           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_4CYCLES  (4)
      57           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_5CYCLES  (5)
      58           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_6CYCLES  (6)
      59           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_7CYCLES  (7)
      60           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_8CYCLES  (8)
      61           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_9CYCLES  (9)
      62           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES (10)
      63           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_11CYCLES (11)
      64           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_12CYCLES (12)
      65           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_13CYCLES (13)
      66           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_14CYCLES (14)
      67           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_15CYCLES (15)
      68           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_16CYCLES (16)
      69           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_17CYCLES (17)
      70           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_18CYCLES (18)
      71           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_19CYCLES (19)
      72           0 : #define SDRAM_AUTO_REFREDSH_INTERVEL_20CYCLES (20)
      73             : 
      74           0 : #define SDRAM_AUTO_REFREDSH_COUNT_1TIMES  (1)
      75           0 : #define SDRAM_AUTO_REFREDSH_COUNT_2TIMES  (2)
      76           0 : #define SDRAM_AUTO_REFREDSH_COUNT_3TIMES  (3)
      77           0 : #define SDRAM_AUTO_REFREDSH_COUNT_4TIMES  (4)
      78           0 : #define SDRAM_AUTO_REFREDSH_COUNT_5TIMES  (5)
      79           0 : #define SDRAM_AUTO_REFREDSH_COUNT_6TIMES  (6)
      80           0 : #define SDRAM_AUTO_REFREDSH_COUNT_7TIMES  (7)
      81           0 : #define SDRAM_AUTO_REFREDSH_COUNT_8TIMES  (8)
      82           0 : #define SDRAM_AUTO_REFREDSH_COUNT_9TIMES  (9)
      83           0 : #define SDRAM_AUTO_REFREDSH_COUNT_10TIMES (10)
      84           0 : #define SDRAM_AUTO_REFREDSH_COUNT_11TIMES (11)
      85           0 : #define SDRAM_AUTO_REFREDSH_COUNT_12TIMES (12)
      86           0 : #define SDRAM_AUTO_REFREDSH_COUNT_13TIMES (13)
      87           0 : #define SDRAM_AUTO_REFREDSH_COUNT_14TIMES (14)
      88           0 : #define SDRAM_AUTO_REFREDSH_COUNT_15TIMES (15)
      89             : 
      90           0 : #define SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES  (3)
      91           0 : #define SDRAM_AUTO_PRECHARGE_CYCLE_4CYCLES  (4)
      92           0 : #define SDRAM_AUTO_PRECHARGE_CYCLE_5CYCLES  (5)
      93           0 : #define SDRAM_AUTO_PRECHARGE_CYCLE_6CYCLES  (6)
      94           0 : #define SDRAM_AUTO_PRECHARGE_CYCLE_7CYCLES  (7)
      95           0 : #define SDRAM_AUTO_PRECHARGE_CYCLE_8CYCLES  (8)
      96           0 : #define SDRAM_AUTO_PRECHARGE_CYCLE_9CYCLES  (9)
      97           0 : #define SDRAM_AUTO_PRECHARGE_CYCLE_10CYCLES (10)
      98             : 
      99             : #endif