Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 Georgij Cernysiov
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
       9              : 
      10              : /* NOR/SRAM Bank */
      11            0 : #define STM32_FMC_NORSRAM_BANK1                    0x00000000UL
      12            0 : #define STM32_FMC_NORSRAM_BANK2                    0x00000002UL
      13            0 : #define STM32_FMC_NORSRAM_BANK3                    0x00000004UL
      14            0 : #define STM32_FMC_NORSRAM_BANK4                    0x00000006UL
      15              : 
      16              : /* Data Address Bus Multiplexing */
      17            0 : #define STM32_FMC_DATA_ADDRESS_MUX_DISABLE         0x00000000UL
      18            0 : #define STM32_FMC_DATA_ADDRESS_MUX_ENABLE          0x00000002UL
      19              : 
      20              : /* Memory Type */
      21            0 : #define STM32_FMC_MEMORY_TYPE_SRAM                 0x00000000UL
      22            0 : #define STM32_FMC_MEMORY_TYPE_PSRAM                0x00000004UL
      23            0 : #define STM32_FMC_MEMORY_TYPE_NOR                  0x00000008UL
      24              : 
      25              : /* NORSRAM Data Width */
      26            0 : #define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_8          0x00000000UL
      27            0 : #define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_16         0x00000010UL
      28            0 : #define STM32_FMC_NORSRAM_MEM_BUS_WIDTH_32         0x00000020UL
      29              : 
      30              : /* Burst Access Mode */
      31            0 : #define STM32_FMC_BURST_ACCESS_MODE_DISABLE        0x00000000UL
      32            0 : #define STM32_FMC_BURST_ACCESS_MODE_ENABLE         0x00000100UL
      33              : 
      34              : /* Wait Signal Polarity */
      35            0 : #define STM32_FMC_WAIT_SIGNAL_POLARITY_LOW         0x00000000UL
      36            0 : #define STM32_FMC_WAIT_SIGNAL_POLARITY_HIGH        0x00000200UL
      37              : 
      38              : /* Wait Timing */
      39            0 : #define STM32_FMC_WAIT_TIMING_BEFORE_WS            0x00000000UL
      40            0 : #define STM32_FMC_WAIT_TIMING_DURING_WS            0x00000800UL
      41              : 
      42              : /* Write Operation */
      43            0 : #define STM32_FMC_WRITE_OPERATION_DISABLE          0x00000000UL
      44            0 : #define STM32_FMC_WRITE_OPERATION_ENABLE           0x00001000UL
      45              : 
      46              : /* Wait Signal */
      47            0 : #define STM32_FMC_WAIT_SIGNAL_DISABLE              0x00000000UL
      48            0 : #define STM32_FMC_WAIT_SIGNAL_ENABLE               0x00002000UL
      49              : 
      50              : /* Extended Mode */
      51            0 : #define STM32_FMC_EXTENDED_MODE_DISABLE            0x00000000UL
      52            0 : #define STM32_FMC_EXTENDED_MODE_ENABLE             0x00004000UL
      53              : 
      54              : /* Asynchronous Wait */
      55            0 : #define STM32_FMC_ASYNCHRONOUS_WAIT_DISABLE        0x00000000UL
      56            0 : #define STM32_FMC_ASYNCHRONOUS_WAIT_ENABLE         0x00008000UL
      57              : 
      58              : /* Write Burst */
      59            0 : #define STM32_FMC_WRITE_BURST_DISABLE              0x00000000UL
      60            0 : #define STM32_FMC_WRITE_BURST_ENABLE               0x00080000UL
      61              : 
      62              : /* Continuous Clock */
      63            0 : #define STM32_FMC_CONTINUOUS_CLOCK_SYNC_ONLY       0x00000000UL
      64            0 : #define STM32_FMC_CONTINUOUS_CLOCK_SYNC_ASYNC      0x00100000UL
      65              : 
      66              : /* Write FIFO */
      67              : /* Not every SoC can disable FIFO, refer to reference manual */
      68            0 : #define STM32_FMC_WRITE_FIFO_DISABLE               0x00200000UL
      69            0 : #define STM32_FMC_WRITE_FIFO_ENABLE                0x00000000UL
      70              : 
      71              : /* Page Size */
      72            0 : #define STM32_FMC_PAGE_SIZE_NONE                   0x00000000UL
      73            0 : #define STM32_FMC_PAGE_SIZE_128                    0x00010000UL
      74            0 : #define STM32_FMC_PAGE_SIZE_256                    0x00020000UL
      75            0 : #define STM32_FMC_PAGE_SIZE_512                    0x00030000UL
      76            0 : #define STM32_FMC_PAGE_SIZE_1024                   0x00040000UL
      77              : 
      78              : /* Access Mode */
      79            0 : #define STM32_FMC_ACCESS_MODE_A                    0x00000000UL
      80            0 : #define STM32_FMC_ACCESS_MODE_B                    0x10000000UL
      81            0 : #define STM32_FMC_ACCESS_MODE_C                    0x20000000UL
      82            0 : #define STM32_FMC_ACCESS_MODE_D                    0x30000000UL
      83              : 
      84              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_ */