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1 0 : /*
2 : * Copyright 2024,2025 NXP
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_
9 :
10 : /**
11 : * @addtogroup mipi_dbi_interface
12 : * @{
13 : */
14 :
15 : /**
16 : * SPI 3 wire (Type C1). Uses 9 write clocks to send a byte of data.
17 : * The bit sent on the 9th clock indicates whether the byte is a
18 : * command or data byte
19 : *
20 : *
21 : * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-
22 : * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-'
23 : *
24 : * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.-
25 : * DOUT |D/C| D7| D6| D5| D4| D3| D2| D1| D0|D/C| D7| D6| D5| D4|...|
26 : * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'-
27 : * | Word 1 | Word n
28 : *
29 : * -. .-
30 : * CS '-----------------------------------------------------------'
31 : */
32 1 : #define MIPI_DBI_MODE_SPI_3WIRE 0x1
33 : /**
34 : * SPI 4 wire (Type C3). Uses 8 write clocks to send a byte of data.
35 : * an additional C/D pin will be use to indicate whether the byte is a
36 : * command or data byte
37 : *
38 : * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-.
39 : * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '---
40 : *
41 : * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.-
42 : * DOUT | D7| D6| D5| D4| D3| D2| D1| D0| D7| D6| D5| D4| D3| D2| D1| D0|
43 : * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'-
44 : * | Word 1 | Word n
45 : *
46 : * -. .-
47 : * CS '---------------------------------------------------------------'
48 : *
49 : * -.-------------------------------.-------------------------------.-
50 : * CD | D/C | D/C |
51 : * -'-------------------------------'-------------------------------'-
52 : */
53 1 : #define MIPI_DBI_MODE_SPI_4WIRE 0x2
54 : /**
55 : * @name Parallel Bus protocol for MIPI DBI Type A based on Motorola 6800 bus.
56 : *
57 : * -. .--------. .------------------------
58 : * CS '---' '---'
59 : *
60 : * -------------------------------------------
61 : * RESX
62 : *
63 : * .--------------------------------
64 : * D/CX ----------'
65 : *
66 : *
67 : * R/WX -------------------------------------------
68 : *
69 : * -------------------------------------------
70 : * E
71 : *
72 : * .--------. .--------------------------.
73 : * D[15:0]/ -| COMMAND|---| DATA |
74 : * D[8:0]/ '--------' '--------------------------'
75 : * D[7:0]
76 : *
77 : * Please refer to the MIPI DBI specification for a detailed cycle diagram.
78 : *
79 : * @{
80 : */
81 1 : #define MIPI_DBI_MODE_6800_BUS_16_BIT 0x3 /**< Motorola 6800 parallel bus, 16-bit width */
82 1 : #define MIPI_DBI_MODE_6800_BUS_9_BIT 0x4 /**< Motorola 6800 parallel bus, 9-bit width */
83 1 : #define MIPI_DBI_MODE_6800_BUS_8_BIT 0x5 /**< Motorola 6800 parallel bus, 8-bit width */
84 : /** @} */
85 : /**
86 : * @name Parallel Bus protocol for MIPI DBI Type B based on Intel 8080 bus.
87 : *
88 : * -. .-
89 : * CS '---------------------------------------'
90 : *
91 : * -------------------------------------------
92 : * RESX
93 : *
94 : * --. .----------------------------
95 : * D/CX '-----------'
96 : *
97 : * ---. .--------. .----------------------
98 : * WRX '---' '---'
99 : *
100 : * -------------------------------------------
101 : * RDX
102 : *
103 : * .--------. .--------------------------.
104 : * D[15:0]/ ---| COMMAND|---| DATA |
105 : * D[8:0]/ '--------' '--------------------------'
106 : * D[7:0]
107 : *
108 : * Please refer to the MIPI DBI specification for a detailed cycle diagram.
109 : * @{
110 : */
111 1 : #define MIPI_DBI_MODE_8080_BUS_16_BIT 0x6 /**< Intel 8080 parallel bus, 16-bit width */
112 1 : #define MIPI_DBI_MODE_8080_BUS_9_BIT 0x7 /**< Intel 8080 parallel bus, 9-bit width */
113 1 : #define MIPI_DBI_MODE_8080_BUS_8_BIT 0x8 /**< Intel 8080 parallel bus, 8-bit width */
114 : /** @} */
115 :
116 : /**
117 : * @name Color coding for MIPI DBI Type A or Type B interface.
118 : * @{
119 : */
120 : /**
121 : * RGB332 (8 bpp).
122 : *
123 : * - For 8-bit data bus width, 1 pixel is sent in 1 cycle.
124 : * - For 16-bit data bus width, 2 pixels are sent in 1 cycle.
125 : */
126 1 : #define MIPI_DBI_MODE_RGB332 (0x1 << 4U)
127 : /**
128 : * RGB444 (12 bpp).
129 : *
130 : * - For 8-bit data bus width, 2 pixels are sent in 3 cycles.
131 : * - For 16-bit data bus width, 1 pixel is sent in 1 cycle, the high 4 bits are not used.
132 : */
133 1 : #define MIPI_DBI_MODE_RGB444 (0x2 << 4U)
134 : /**
135 : * RGB565 (16 bpp).
136 : *
137 : * - For 8-bit data bus width, 1 pixel is sent in 2 cycles.
138 : * - For 16-bit data bus width, 1 pixel is sent in 1 cycle.
139 : */
140 1 : #define MIPI_DBI_MODE_RGB565 (0x3 << 4U)
141 : /**
142 : * RGB666 (18 bpp).
143 : *
144 : * - For 8-bit data bus width, #MIPI_DBI_MODE_RGB666_1 and #MIPI_DBI_MODE_RGB666_2 are the same.
145 : * 1 pixel is sent in 3 cycles, R component first, and the low 2 bits are not used.
146 : * - For 9-bit data bus width, #MIPI_DBI_MODE_RGB666_1 and #MIPI_DBI_MODE_RGB666_2 are the same.
147 : * 1 pixel is sent in 2 cycles.
148 : * - For 16-bit data bus width, #MIPI_DBI_MODE_RGB666_1 is option 1, 2 pixels are sent in 3 cycles.
149 : * The first pixel's R/G/B components are sent in cycle 1 bits 10-15, cycle 1 bits 2-7 and cycle
150 : * 2 bits 10-15. The second pixel's R/G/B components are sent in cycle 2 bits 2-7, cycle 3 bits
151 : * 10-15 and cycle 3 bits 2-7. #MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles.
152 : * The pixel's R/G/B components are sent in cycle 1 bits 2-7, cycle 2 bits 10-15 and cycle 2 bits
153 : * 2-7.
154 : */
155 1 : #define MIPI_DBI_MODE_RGB666_1 (0x4 << 4U)
156 : /**
157 : * RGB666 (18 bpp).
158 : *
159 : * @see MIPI_DBI_MODE_RGB666_1
160 : */
161 1 : #define MIPI_DBI_MODE_RGB666_2 (0x5 << 4U)
162 : /**
163 : * RGB666 (18 bpp).
164 : *
165 : * - For 8-bit data bus width, #MIPI_DBI_MODE_RGB666_1 and #MIPI_DBI_MODE_RGB666_2 are the same.
166 : * 1 pixel is sent in 3 cycles, R component first.
167 : * - For 16-bit data bus width, #MIPI_DBI_MODE_RGB666_1 is option 1, 2 pixels are sent in 3 cycles.
168 : * The first pixel's R/G/B components are sent in cycle 1 bits 8-15, cycle 1 bits 0-7 and cycle 2
169 : * bits 0-15. The second pixel's R/G/B components are sent in cycle 2 bits 0-7, cycle 3 bits 8-15
170 : * and cycle 3 bits 0-7.
171 : * #MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles. The pixel's R/G/B components
172 : * are sent in cycle 1 bits 0-7, cycle 2 bits 8-15 and cycle 2 bits 0-7.
173 : */
174 1 : #define MIPI_DBI_MODE_RGB888_1 (0x6 << 4U)
175 : /**
176 : * RGB888 (24 bpp).
177 : * @see MIPI_DBI_MODE_RGB888_1
178 : */
179 1 : #define MIPI_DBI_MODE_RGB888_2 (0x7 << 4U)
180 : /** @} */
181 :
182 : /** MIPI DBI tearing enable synchronization is disabled. */
183 1 : #define MIPI_DBI_TE_NO_EDGE 0x0
184 :
185 : /**
186 : * MIPI DBI tearing enable synchronization on rising edge of TE signal.
187 : * The controller will only send display write data on a rising edge of TE.
188 : * This should be used when the controller can send a frame worth of data
189 : * data to the display panel faster than the display panel can read a frame
190 : * from its RAM
191 : *
192 : * .------. .------.
193 : * TE -----' '------------------------' '-------------
194 : * -----. .----------------------.
195 : * CS '--------' '--------------------
196 : */
197 1 : #define MIPI_DBI_TE_RISING_EDGE 0x1
198 :
199 : /**
200 : * MIPI DBI tearing enable synchronization on falling edge of TE signal.
201 : * The controller will only send display write data on a falling edge of TE.
202 : * This should be used when the controller sends a frame worth of data
203 : * data to the display panel slower than the display panel can read a frame
204 : * from its RAM. TE synchronization in this mode will only work if the
205 : * controller can complete the write before the display panel completes 2
206 : * read cycles, otherwise the read pointer will "catch up" with the write
207 : * pointer.
208 : *
209 : * .------. .------.
210 : * TE -----' '------------------------' '-------------
211 : * ------------. .-----
212 : * CS '---------------------------------------'
213 : */
214 1 : #define MIPI_DBI_TE_FALLING_EDGE 0x2
215 :
216 : /**
217 : * SPI transfer of DBI commands as 8-bit blocks, the default behaviour in
218 : * SPI 4 wire (Type C3) mode. The clocking diagram corresponds exactly to
219 : * the illustration of Type C3.
220 : */
221 1 : #define MIPI_DBI_SPI_XFR_8BIT 8
222 : /**
223 : * SPI transfer of DBI commands as 16-bit blocks, a rare and seldom behaviour
224 : * in SPI 4 wire (Type C3) mode. The corresponding clocking diagram is slightly
225 : * different to the illustration of Type C3.
226 : *
227 : * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-.
228 : * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '---
229 : *
230 : * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.-
231 : * DOUT |D15|D14|D13|D12|D11|D10| D9| D8| D7| D6| D5| D4| D3| D2| D1| D0|
232 : * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'-
233 : * | Word 1 (stuffing) : (byte) |
234 : *
235 : * -. .-
236 : * CS '---------------------------------------------------------------'
237 : *
238 : * -.---------------------------------------------------------------.-
239 : * CD | D/C |
240 : * -'---------------------------------------------------------------'-
241 : */
242 1 : #define MIPI_DBI_SPI_XFR_16BIT 16
243 :
244 : /**
245 : * @}
246 : */
247 :
248 :
249 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DBI_MIPI_DBI_H_ */
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