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1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2A1_ELC_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2A1_ELC_H_
9 :
10 : /* Sources of event signals to be linked to other peripherals or the CPU */
11 0 : #define RA_ELC_EVENT_NONE 0x0
12 0 : #define RA_ELC_EVENT_ICU_IRQ0 0x001
13 0 : #define RA_ELC_EVENT_ICU_IRQ1 0x002
14 0 : #define RA_ELC_EVENT_ICU_IRQ2 0x003
15 0 : #define RA_ELC_EVENT_ICU_IRQ3 0x004
16 0 : #define RA_ELC_EVENT_ICU_IRQ4 0x005
17 0 : #define RA_ELC_EVENT_ICU_IRQ5 0x006
18 0 : #define RA_ELC_EVENT_ICU_IRQ6 0x007
19 0 : #define RA_ELC_EVENT_ICU_IRQ7 0x008
20 0 : #define RA_ELC_EVENT_DTC_COMPLETE 0x009
21 0 : #define RA_ELC_EVENT_DTC_END 0x00A
22 0 : #define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x00B
23 0 : #define RA_ELC_EVENT_FCU_FRDYI 0x00C
24 0 : #define RA_ELC_EVENT_LVD_LVD1 0x00D
25 0 : #define RA_ELC_EVENT_LVD_LVD2 0x00E
26 0 : #define RA_ELC_EVENT_CGC_MOSC_STOP 0x00F
27 0 : #define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x010
28 0 : #define RA_ELC_EVENT_AGT0_INT 0x011
29 0 : #define RA_ELC_EVENT_AGT0_COMPARE_A 0x012
30 0 : #define RA_ELC_EVENT_AGT0_COMPARE_B 0x013
31 0 : #define RA_ELC_EVENT_AGT1_INT 0x014
32 0 : #define RA_ELC_EVENT_AGT1_COMPARE_A 0x015
33 0 : #define RA_ELC_EVENT_AGT1_COMPARE_B 0x016
34 0 : #define RA_ELC_EVENT_IWDT_UNDERFLOW 0x017
35 0 : #define RA_ELC_EVENT_WDT_UNDERFLOW 0x018
36 0 : #define RA_ELC_EVENT_RTC_ALARM 0x019
37 0 : #define RA_ELC_EVENT_RTC_PERIOD 0x01A
38 0 : #define RA_ELC_EVENT_RTC_CARRY 0x01B
39 0 : #define RA_ELC_EVENT_ADC0_SCAN_END 0x01C
40 0 : #define RA_ELC_EVENT_ADC0_SCAN_END_B 0x01D
41 0 : #define RA_ELC_EVENT_ADC0_WINDOW_A 0x01E
42 0 : #define RA_ELC_EVENT_ADC0_WINDOW_B 0x01F
43 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x020
44 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x021
45 0 : #define RA_ELC_EVENT_ACMPHS0_INT 0x022
46 0 : #define RA_ELC_EVENT_ACMPLP0_INT 0x023
47 0 : #define RA_ELC_EVENT_ACMPLP1_INT 0x024
48 0 : #define RA_ELC_EVENT_USBFS_INT 0x025
49 0 : #define RA_ELC_EVENT_USBFS_RESUME 0x026
50 0 : #define RA_ELC_EVENT_IIC0_RXI 0x027
51 0 : #define RA_ELC_EVENT_IIC0_TXI 0x028
52 0 : #define RA_ELC_EVENT_IIC0_TEI 0x029
53 0 : #define RA_ELC_EVENT_IIC0_ERI 0x02A
54 0 : #define RA_ELC_EVENT_IIC0_WUI 0x02B
55 0 : #define RA_ELC_EVENT_IIC1_RXI 0x02C
56 0 : #define RA_ELC_EVENT_IIC1_TXI 0x02D
57 0 : #define RA_ELC_EVENT_IIC1_TEI 0x02E
58 0 : #define RA_ELC_EVENT_IIC1_ERI 0x02F
59 0 : #define RA_ELC_EVENT_CTSU_WRITE 0x030
60 0 : #define RA_ELC_EVENT_CTSU_READ 0x031
61 0 : #define RA_ELC_EVENT_CTSU_END 0x032
62 0 : #define RA_ELC_EVENT_KEY_INT 0x033
63 0 : #define RA_ELC_EVENT_DOC_INT 0x034
64 0 : #define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x035
65 0 : #define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x036
66 0 : #define RA_ELC_EVENT_CAC_OVERFLOW 0x037
67 0 : #define RA_ELC_EVENT_CAN0_ERROR 0x038
68 0 : #define RA_ELC_EVENT_CAN0_FIFO_RX 0x039
69 0 : #define RA_ELC_EVENT_CAN0_FIFO_TX 0x03A
70 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x03B
71 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x03C
72 0 : #define RA_ELC_EVENT_IOPORT_EVENT_1 0x03D
73 0 : #define RA_ELC_EVENT_IOPORT_EVENT_2 0x03E
74 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x03F
75 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x040
76 0 : #define RA_ELC_EVENT_POEG0_EVENT 0x041
77 0 : #define RA_ELC_EVENT_POEG1_EVENT 0x042
78 0 : #define RA_ELC_EVENT_SDADC0_ADI 0x043
79 0 : #define RA_ELC_EVENT_SDADC0_SCANEND 0x044
80 0 : #define RA_ELC_EVENT_SDADC0_CALIEND 0x045
81 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x046
82 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x047
83 0 : #define RA_ELC_EVENT_GPT0_COMPARE_C 0x048
84 0 : #define RA_ELC_EVENT_GPT0_COMPARE_D 0x049
85 0 : #define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x04A
86 0 : #define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x04B
87 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x04C
88 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x04D
89 0 : #define RA_ELC_EVENT_GPT1_COMPARE_C 0x04E
90 0 : #define RA_ELC_EVENT_GPT1_COMPARE_D 0x04F
91 0 : #define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x050
92 0 : #define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x051
93 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x052
94 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x053
95 0 : #define RA_ELC_EVENT_GPT2_COMPARE_C 0x054
96 0 : #define RA_ELC_EVENT_GPT2_COMPARE_D 0x055
97 0 : #define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x056
98 0 : #define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x057
99 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x058
100 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x059
101 0 : #define RA_ELC_EVENT_GPT3_COMPARE_C 0x05A
102 0 : #define RA_ELC_EVENT_GPT3_COMPARE_D 0x05B
103 0 : #define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x05C
104 0 : #define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x05D
105 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x05E
106 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x05F
107 0 : #define RA_ELC_EVENT_GPT4_COMPARE_C 0x060
108 0 : #define RA_ELC_EVENT_GPT4_COMPARE_D 0x061
109 0 : #define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x062
110 0 : #define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x063
111 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x064
112 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x065
113 0 : #define RA_ELC_EVENT_GPT5_COMPARE_C 0x066
114 0 : #define RA_ELC_EVENT_GPT5_COMPARE_D 0x067
115 0 : #define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x068
116 0 : #define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x069
117 0 : #define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x06A
118 0 : #define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x06B
119 0 : #define RA_ELC_EVENT_GPT6_COMPARE_C 0x06C
120 0 : #define RA_ELC_EVENT_GPT6_COMPARE_D 0x06D
121 0 : #define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x06E
122 0 : #define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x06F
123 0 : #define RA_ELC_EVENT_OPS_UVW_EDGE 0x070
124 0 : #define RA_ELC_EVENT_SCI0_RXI 0x071
125 0 : #define RA_ELC_EVENT_SCI0_TXI 0x072
126 0 : #define RA_ELC_EVENT_SCI0_TEI 0x073
127 0 : #define RA_ELC_EVENT_SCI0_ERI 0x074
128 0 : #define RA_ELC_EVENT_SCI0_AM 0x075
129 0 : #define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x076
130 0 : #define RA_ELC_EVENT_SCI1_RXI 0x077
131 0 : #define RA_ELC_EVENT_SCI1_TXI 0x078
132 0 : #define RA_ELC_EVENT_SCI1_TEI 0x079
133 0 : #define RA_ELC_EVENT_SCI1_ERI 0x07A
134 0 : #define RA_ELC_EVENT_SCI1_AM 0x07B
135 0 : #define RA_ELC_EVENT_SCI9_RXI 0x07C
136 0 : #define RA_ELC_EVENT_SCI9_TXI 0x07D
137 0 : #define RA_ELC_EVENT_SCI9_TEI 0x07E
138 0 : #define RA_ELC_EVENT_SCI9_ERI 0x07F
139 0 : #define RA_ELC_EVENT_SCI9_AM 0x080
140 0 : #define RA_ELC_EVENT_SPI0_RXI 0x081
141 0 : #define RA_ELC_EVENT_SPI0_TXI 0x082
142 0 : #define RA_ELC_EVENT_SPI0_IDLE 0x083
143 0 : #define RA_ELC_EVENT_SPI0_ERI 0x084
144 0 : #define RA_ELC_EVENT_SPI0_TEI 0x085
145 0 : #define RA_ELC_EVENT_SPI1_RXI 0x086
146 0 : #define RA_ELC_EVENT_SPI1_TXI 0x087
147 0 : #define RA_ELC_EVENT_SPI1_IDLE 0x088
148 0 : #define RA_ELC_EVENT_SPI1_ERI 0x089
149 0 : #define RA_ELC_EVENT_SPI1_TEI 0x08A
150 0 : #define RA_ELC_EVENT_AES_WRREQ 0x08B
151 0 : #define RA_ELC_EVENT_AES_RDREQ 0x08C
152 0 : #define RA_ELC_EVENT_TRNG_RDREQ 0x08D
153 :
154 : /* Possible peripherals to be linked to event signals */
155 0 : #define RA_ELC_PERIPHERAL_GPT_A 0
156 0 : #define RA_ELC_PERIPHERAL_GPT_B 1
157 0 : #define RA_ELC_PERIPHERAL_GPT_C 2
158 0 : #define RA_ELC_PERIPHERAL_GPT_D 3
159 0 : #define RA_ELC_PERIPHERAL_ADC0 8
160 0 : #define RA_ELC_PERIPHERAL_ADC0_B 9
161 0 : #define RA_ELC_PERIPHERAL_DAC0 12
162 0 : #define RA_ELC_PERIPHERAL_IOPORT1 14
163 0 : #define RA_ELC_PERIPHERAL_IOPORT2 15
164 0 : #define RA_ELC_PERIPHERAL_CTSU 18
165 0 : #define RA_ELC_PERIPHERAL_DA8_0 19
166 0 : #define RA_ELC_PERIPHERAL_DA8_1 20
167 0 : #define RA_ELC_PERIPHERAL_SDADC0 22
168 :
169 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2A1_ELC_H_ */
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