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1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E1_ELC_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E1_ELC_H_
9 :
10 : /* Sources of event signals to be linked to other peripherals or the CPU */
11 0 : #define RA_ELC_EVENT_NONE 0x0
12 0 : #define RA_ELC_EVENT_ICU_IRQ0 0x001
13 0 : #define RA_ELC_EVENT_ICU_IRQ1 0x002
14 0 : #define RA_ELC_EVENT_ICU_IRQ2 0x003
15 0 : #define RA_ELC_EVENT_ICU_IRQ3 0x004
16 0 : #define RA_ELC_EVENT_ICU_IRQ4 0x005
17 0 : #define RA_ELC_EVENT_ICU_IRQ5 0x006
18 0 : #define RA_ELC_EVENT_ICU_IRQ6 0x007
19 0 : #define RA_ELC_EVENT_ICU_IRQ7 0x008
20 0 : #define RA_ELC_EVENT_ICU_IRQ8 0x009
21 0 : #define RA_ELC_EVENT_ICU_IRQ9 0x00A
22 0 : #define RA_ELC_EVENT_ICU_IRQ13 0x00E
23 0 : #define RA_ELC_EVENT_DMAC0_INT 0x020
24 0 : #define RA_ELC_EVENT_DMAC1_INT 0x021
25 0 : #define RA_ELC_EVENT_DMAC2_INT 0x022
26 0 : #define RA_ELC_EVENT_DMAC3_INT 0x023
27 0 : #define RA_ELC_EVENT_DMAC4_INT 0x024
28 0 : #define RA_ELC_EVENT_DMAC5_INT 0x025
29 0 : #define RA_ELC_EVENT_DMAC6_INT 0x026
30 0 : #define RA_ELC_EVENT_DMAC7_INT 0x027
31 0 : #define RA_ELC_EVENT_DTC_COMPLETE 0x029
32 0 : #define RA_ELC_EVENT_DTC_END 0x02A
33 0 : #define RA_ELC_EVENT_DMA_TRANSERR 0x02B
34 0 : #define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D
35 0 : #define RA_ELC_EVENT_FCU_FIFERR 0x030
36 0 : #define RA_ELC_EVENT_FCU_FRDYI 0x031
37 0 : #define RA_ELC_EVENT_LVD_LVD1 0x038
38 0 : #define RA_ELC_EVENT_LVD_LVD2 0x039
39 0 : #define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B
40 0 : #define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C
41 0 : #define RA_ELC_EVENT_AGT0_INT 0x040
42 0 : #define RA_ELC_EVENT_AGT0_COMPARE_A 0x041
43 0 : #define RA_ELC_EVENT_AGT0_COMPARE_B 0x042
44 0 : #define RA_ELC_EVENT_AGT1_INT 0x043
45 0 : #define RA_ELC_EVENT_AGT1_COMPARE_A 0x044
46 0 : #define RA_ELC_EVENT_AGT1_COMPARE_B 0x045
47 0 : #define RA_ELC_EVENT_AGT2_INT 0x046
48 0 : #define RA_ELC_EVENT_AGT2_COMPARE_A 0x047
49 0 : #define RA_ELC_EVENT_AGT2_COMPARE_B 0x048
50 0 : #define RA_ELC_EVENT_AGT3_INT 0x049
51 0 : #define RA_ELC_EVENT_AGT3_COMPARE_A 0x04A
52 0 : #define RA_ELC_EVENT_AGT3_COMPARE_B 0x04B
53 0 : #define RA_ELC_EVENT_AGT5_INT 0x04F
54 0 : #define RA_ELC_EVENT_AGT5_COMPARE_A 0x050
55 0 : #define RA_ELC_EVENT_AGT5_COMPARE_B 0x051
56 0 : #define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052
57 0 : #define RA_ELC_EVENT_WDT_UNDERFLOW 0x053
58 0 : #define RA_ELC_EVENT_RTC_ALARM 0x054
59 0 : #define RA_ELC_EVENT_RTC_PERIOD 0x055
60 0 : #define RA_ELC_EVENT_RTC_CARRY 0x056
61 0 : #define RA_ELC_EVENT_USBFS_FIFO_0 0x06B
62 0 : #define RA_ELC_EVENT_USBFS_FIFO_1 0x06C
63 0 : #define RA_ELC_EVENT_USBFS_INT 0x06D
64 0 : #define RA_ELC_EVENT_USBFS_RESUME 0x06E
65 0 : #define RA_ELC_EVENT_IIC0_RXI 0x073
66 0 : #define RA_ELC_EVENT_IIC0_TXI 0x074
67 0 : #define RA_ELC_EVENT_IIC0_TEI 0x075
68 0 : #define RA_ELC_EVENT_IIC0_ERI 0x076
69 0 : #define RA_ELC_EVENT_IIC0_WUI 0x077
70 0 : #define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E
71 0 : #define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F
72 0 : #define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0
73 0 : #define RA_ELC_EVENT_CAN0_ERROR 0x0A1
74 0 : #define RA_ELC_EVENT_CAN0_FIFO_RX 0x0A2
75 0 : #define RA_ELC_EVENT_CAN0_FIFO_TX 0x0A3
76 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x0A4
77 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x0A5
78 0 : #define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1
79 0 : #define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2
80 0 : #define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3
81 0 : #define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4
82 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5
83 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6
84 0 : #define RA_ELC_EVENT_POEG0_EVENT 0x0B7
85 0 : #define RA_ELC_EVENT_POEG1_EVENT 0x0B8
86 0 : #define RA_ELC_EVENT_POEG2_EVENT 0x0B9
87 0 : #define RA_ELC_EVENT_POEG3_EVENT 0x0BA
88 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0C9
89 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CA
90 0 : #define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CB
91 0 : #define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CC
92 0 : #define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CD
93 0 : #define RA_ELC_EVENT_GPT1_COMPARE_F 0x0CE
94 0 : #define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0CF
95 0 : #define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D0
96 0 : #define RA_ELC_EVENT_GPT1_PC 0x0D1
97 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0D2
98 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0D3
99 0 : #define RA_ELC_EVENT_GPT2_COMPARE_C 0x0D4
100 0 : #define RA_ELC_EVENT_GPT2_COMPARE_D 0x0D5
101 0 : #define RA_ELC_EVENT_GPT2_COMPARE_E 0x0D6
102 0 : #define RA_ELC_EVENT_GPT2_COMPARE_F 0x0D7
103 0 : #define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0D8
104 0 : #define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0D9
105 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0E4
106 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0E5
107 0 : #define RA_ELC_EVENT_GPT4_COMPARE_C 0x0E6
108 0 : #define RA_ELC_EVENT_GPT4_COMPARE_D 0x0E7
109 0 : #define RA_ELC_EVENT_GPT4_COMPARE_E 0x0E8
110 0 : #define RA_ELC_EVENT_GPT4_COMPARE_F 0x0E9
111 0 : #define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0EA
112 0 : #define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0EB
113 0 : #define RA_ELC_EVENT_GPT4_PC 0x0EC
114 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0ED
115 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0EE
116 0 : #define RA_ELC_EVENT_GPT5_COMPARE_C 0x0EF
117 0 : #define RA_ELC_EVENT_GPT5_COMPARE_D 0x0F0
118 0 : #define RA_ELC_EVENT_GPT5_COMPARE_E 0x0F1
119 0 : #define RA_ELC_EVENT_GPT5_COMPARE_F 0x0F2
120 0 : #define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0F3
121 0 : #define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0F4
122 0 : #define RA_ELC_EVENT_GPT5_PC 0x0F5
123 0 : #define RA_ELC_EVENT_ADC0_SCAN_END 0x160
124 0 : #define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161
125 0 : #define RA_ELC_EVENT_ADC0_WINDOW_A 0x162
126 0 : #define RA_ELC_EVENT_ADC0_WINDOW_B 0x163
127 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164
128 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165
129 0 : #define RA_ELC_EVENT_SCI0_RXI 0x180
130 0 : #define RA_ELC_EVENT_SCI0_TXI 0x181
131 0 : #define RA_ELC_EVENT_SCI0_TEI 0x182
132 0 : #define RA_ELC_EVENT_SCI0_ERI 0x183
133 0 : #define RA_ELC_EVENT_SCI0_AM 0x184
134 0 : #define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185
135 0 : #define RA_ELC_EVENT_SCI3_RXI 0x192
136 0 : #define RA_ELC_EVENT_SCI3_TXI 0x193
137 0 : #define RA_ELC_EVENT_SCI3_TEI 0x194
138 0 : #define RA_ELC_EVENT_SCI3_ERI 0x195
139 0 : #define RA_ELC_EVENT_SCI3_AM 0x196
140 0 : #define RA_ELC_EVENT_SCI4_RXI 0x198
141 0 : #define RA_ELC_EVENT_SCI4_TXI 0x199
142 0 : #define RA_ELC_EVENT_SCI4_TEI 0x19A
143 0 : #define RA_ELC_EVENT_SCI4_ERI 0x19B
144 0 : #define RA_ELC_EVENT_SCI4_AM 0x19C
145 0 : #define RA_ELC_EVENT_SCI9_RXI 0x1B6
146 0 : #define RA_ELC_EVENT_SCI9_TXI 0x1B7
147 0 : #define RA_ELC_EVENT_SCI9_TEI 0x1B8
148 0 : #define RA_ELC_EVENT_SCI9_ERI 0x1B9
149 0 : #define RA_ELC_EVENT_SCI9_AM 0x1BA
150 0 : #define RA_ELC_EVENT_SPI0_RXI 0x1C4
151 0 : #define RA_ELC_EVENT_SPI0_TXI 0x1C5
152 0 : #define RA_ELC_EVENT_SPI0_IDLE 0x1C6
153 0 : #define RA_ELC_EVENT_SPI0_ERI 0x1C7
154 0 : #define RA_ELC_EVENT_SPI0_TEI 0x1C8
155 0 : #define RA_ELC_EVENT_QSPI_INT 0x1DA
156 0 : #define RA_ELC_EVENT_DOC_INT 0x1DB
157 :
158 : /* Possible peripherals to be linked to event signals */
159 0 : #define RA_ELC_PERIPHERAL_GPT_A 0
160 0 : #define RA_ELC_PERIPHERAL_GPT_B 1
161 0 : #define RA_ELC_PERIPHERAL_GPT_C 2
162 0 : #define RA_ELC_PERIPHERAL_GPT_D 3
163 0 : #define RA_ELC_PERIPHERAL_GPT_E 4
164 0 : #define RA_ELC_PERIPHERAL_GPT_F 5
165 0 : #define RA_ELC_PERIPHERAL_GPT_G 6
166 0 : #define RA_ELC_PERIPHERAL_GPT_H 7
167 0 : #define RA_ELC_PERIPHERAL_ADC0 8
168 0 : #define RA_ELC_PERIPHERAL_ADC0_B 9
169 0 : #define RA_ELC_PERIPHERAL_DAC0 12
170 0 : #define RA_ELC_PERIPHERAL_IOPORT1 14
171 0 : #define RA_ELC_PERIPHERAL_IOPORT2 15
172 0 : #define RA_ELC_PERIPHERAL_IOPORT3 16
173 0 : #define RA_ELC_PERIPHERAL_IOPORT4 17
174 :
175 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E1_ELC_H_ */
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