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1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E2_ELC_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E2_ELC_H_
9 :
10 : /* Sources of event signals to be linked to other peripherals or the CPU */
11 0 : #define RA_ELC_EVENT_NONE 0x0
12 0 : #define RA_ELC_EVENT_ICU_IRQ0 0x001
13 0 : #define RA_ELC_EVENT_ICU_IRQ1 0x002
14 0 : #define RA_ELC_EVENT_ICU_IRQ2 0x003
15 0 : #define RA_ELC_EVENT_ICU_IRQ3 0x004
16 0 : #define RA_ELC_EVENT_ICU_IRQ4 0x005
17 0 : #define RA_ELC_EVENT_ICU_IRQ5 0x006
18 0 : #define RA_ELC_EVENT_ICU_IRQ6 0x007
19 0 : #define RA_ELC_EVENT_ICU_IRQ7 0x008
20 0 : #define RA_ELC_EVENT_ICU_IRQ8 0x009
21 0 : #define RA_ELC_EVENT_ICU_IRQ9 0x00A
22 0 : #define RA_ELC_EVENT_ICU_IRQ10 0x00B
23 0 : #define RA_ELC_EVENT_ICU_IRQ11 0x00C
24 0 : #define RA_ELC_EVENT_ICU_IRQ12 0x00D
25 0 : #define RA_ELC_EVENT_ICU_IRQ13 0x00E
26 0 : #define RA_ELC_EVENT_ICU_IRQ14 0x00F
27 0 : #define RA_ELC_EVENT_DMAC0_INT 0x020
28 0 : #define RA_ELC_EVENT_DMAC1_INT 0x021
29 0 : #define RA_ELC_EVENT_DMAC2_INT 0x022
30 0 : #define RA_ELC_EVENT_DMAC3_INT 0x023
31 0 : #define RA_ELC_EVENT_DMAC4_INT 0x024
32 0 : #define RA_ELC_EVENT_DMAC5_INT 0x025
33 0 : #define RA_ELC_EVENT_DMAC6_INT 0x026
34 0 : #define RA_ELC_EVENT_DMAC7_INT 0x027
35 0 : #define RA_ELC_EVENT_DTC_COMPLETE 0x029
36 0 : #define RA_ELC_EVENT_DMA_TRANSERR 0x02B
37 0 : #define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D
38 0 : #define RA_ELC_EVENT_FCU_FIFERR 0x030
39 0 : #define RA_ELC_EVENT_FCU_FRDYI 0x031
40 0 : #define RA_ELC_EVENT_LVD_LVD1 0x038
41 0 : #define RA_ELC_EVENT_LVD_LVD2 0x039
42 0 : #define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B
43 0 : #define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C
44 0 : #define RA_ELC_EVENT_AGT0_INT 0x040
45 0 : #define RA_ELC_EVENT_AGT0_COMPARE_A 0x041
46 0 : #define RA_ELC_EVENT_AGT0_COMPARE_B 0x042
47 0 : #define RA_ELC_EVENT_AGT1_INT 0x043
48 0 : #define RA_ELC_EVENT_AGT1_COMPARE_A 0x044
49 0 : #define RA_ELC_EVENT_AGT1_COMPARE_B 0x045
50 0 : #define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052
51 0 : #define RA_ELC_EVENT_WDT_UNDERFLOW 0x053
52 0 : #define RA_ELC_EVENT_RTC_ALARM 0x054
53 0 : #define RA_ELC_EVENT_RTC_PERIOD 0x055
54 0 : #define RA_ELC_EVENT_RTC_CARRY 0x056
55 0 : #define RA_ELC_EVENT_CAN_RXF 0x059
56 0 : #define RA_ELC_EVENT_CAN_GLERR 0x05A
57 0 : #define RA_ELC_EVENT_CAN_DMAREQ0 0x05B
58 0 : #define RA_ELC_EVENT_CAN_DMAREQ1 0x05C
59 0 : #define RA_ELC_EVENT_CAN0_TX 0x063
60 0 : #define RA_ELC_EVENT_CAN0_CHERR 0x064
61 0 : #define RA_ELC_EVENT_CAN0_COMFRX 0x065
62 0 : #define RA_ELC_EVENT_CAN0_CF_DMAREQ 0x066
63 0 : #define RA_ELC_EVENT_CAN0_RXMB 0x067
64 0 : #define RA_ELC_EVENT_USBFS_INT 0x06D
65 0 : #define RA_ELC_EVENT_USBFS_RESUME 0x06E
66 0 : #define RA_ELC_EVENT_SSI0_TXI 0x08A
67 0 : #define RA_ELC_EVENT_SSI0_RXI 0x08B
68 0 : #define RA_ELC_EVENT_SSI0_INT 0x08D
69 0 : #define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x09E
70 0 : #define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x09F
71 0 : #define RA_ELC_EVENT_CAC_OVERFLOW 0x0A0
72 0 : #define RA_ELC_EVENT_CEC_INTDA 0x0AB
73 0 : #define RA_ELC_EVENT_CEC_INTCE 0x0AC
74 0 : #define RA_ELC_EVENT_CEC_INTERR 0x0AD
75 0 : #define RA_ELC_EVENT_IOPORT_EVENT_1 0x0B1
76 0 : #define RA_ELC_EVENT_IOPORT_EVENT_2 0x0B2
77 0 : #define RA_ELC_EVENT_IOPORT_EVENT_3 0x0B3
78 0 : #define RA_ELC_EVENT_IOPORT_EVENT_4 0x0B4
79 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x0B5
80 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x0B6
81 0 : #define RA_ELC_EVENT_POEG0_EVENT 0x0B7
82 0 : #define RA_ELC_EVENT_POEG1_EVENT 0x0B8
83 0 : #define RA_ELC_EVENT_POEG2_EVENT 0x0B9
84 0 : #define RA_ELC_EVENT_POEG3_EVENT 0x0BA
85 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0C0
86 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0C1
87 0 : #define RA_ELC_EVENT_GPT0_COMPARE_C 0x0C2
88 0 : #define RA_ELC_EVENT_GPT0_COMPARE_D 0x0C3
89 0 : #define RA_ELC_EVENT_GPT0_COMPARE_E 0x0C4
90 0 : #define RA_ELC_EVENT_GPT0_COMPARE_F 0x0C5
91 0 : #define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0C6
92 0 : #define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0C7
93 0 : #define RA_ELC_EVENT_GPT0_PC 0x0C8
94 0 : #define RA_ELC_EVENT_GPT0_AD_TRIG_A 0x0C9
95 0 : #define RA_ELC_EVENT_GPT0_AD_TRIG_B 0x0CA
96 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0CB
97 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0CC
98 0 : #define RA_ELC_EVENT_GPT1_COMPARE_C 0x0CD
99 0 : #define RA_ELC_EVENT_GPT1_COMPARE_D 0x0CE
100 0 : #define RA_ELC_EVENT_GPT1_COMPARE_E 0x0CF
101 0 : #define RA_ELC_EVENT_GPT1_COMPARE_F 0x0D0
102 0 : #define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0D1
103 0 : #define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D2
104 0 : #define RA_ELC_EVENT_GPT1_PC 0x0D3
105 0 : #define RA_ELC_EVENT_GPT1_AD_TRIG_A 0x0D4
106 0 : #define RA_ELC_EVENT_GPT1_AD_TRIG_B 0x0D5
107 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0EC
108 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0ED
109 0 : #define RA_ELC_EVENT_GPT4_COMPARE_C 0x0EE
110 0 : #define RA_ELC_EVENT_GPT4_COMPARE_D 0x0EF
111 0 : #define RA_ELC_EVENT_GPT4_COMPARE_E 0x0F0
112 0 : #define RA_ELC_EVENT_GPT4_COMPARE_F 0x0F1
113 0 : #define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0F2
114 0 : #define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0F3
115 0 : #define RA_ELC_EVENT_GPT4_PC 0x0F4
116 0 : #define RA_ELC_EVENT_GPT4_AD_TRIG_A 0x0F5
117 0 : #define RA_ELC_EVENT_GPT4_AD_TRIG_B 0x0F6
118 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0F7
119 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0F8
120 0 : #define RA_ELC_EVENT_GPT5_COMPARE_C 0x0F9
121 0 : #define RA_ELC_EVENT_GPT5_COMPARE_D 0x0FA
122 0 : #define RA_ELC_EVENT_GPT5_COMPARE_E 0x0FB
123 0 : #define RA_ELC_EVENT_GPT5_COMPARE_F 0x0FC
124 0 : #define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0FD
125 0 : #define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0FE
126 0 : #define RA_ELC_EVENT_GPT5_PC 0x0FF
127 0 : #define RA_ELC_EVENT_GPT5_AD_TRIG_A 0x100
128 0 : #define RA_ELC_EVENT_GPT5_AD_TRIG_B 0x101
129 0 : #define RA_ELC_EVENT_OPS_UVW_EDGE 0x15C
130 0 : #define RA_ELC_EVENT_ADC0_SCAN_END 0x160
131 0 : #define RA_ELC_EVENT_ADC0_SCAN_END_B 0x161
132 0 : #define RA_ELC_EVENT_ADC0_WINDOW_A 0x162
133 0 : #define RA_ELC_EVENT_ADC0_WINDOW_B 0x163
134 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x164
135 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x165
136 0 : #define RA_ELC_EVENT_SCI0_RXI 0x180
137 0 : #define RA_ELC_EVENT_SCI0_TXI 0x181
138 0 : #define RA_ELC_EVENT_SCI0_TEI 0x182
139 0 : #define RA_ELC_EVENT_SCI0_ERI 0x183
140 0 : #define RA_ELC_EVENT_SCI0_AM 0x184
141 0 : #define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x185
142 0 : #define RA_ELC_EVENT_SCI9_RXI 0x1B6
143 0 : #define RA_ELC_EVENT_SCI9_TXI 0x1B7
144 0 : #define RA_ELC_EVENT_SCI9_TEI 0x1B8
145 0 : #define RA_ELC_EVENT_SCI9_ERI 0x1B9
146 0 : #define RA_ELC_EVENT_SCI9_AM 0x1BA
147 0 : #define RA_ELC_EVENT_SPI0_RXI 0x1C4
148 0 : #define RA_ELC_EVENT_SPI0_TXI 0x1C5
149 0 : #define RA_ELC_EVENT_SPI0_IDLE 0x1C6
150 0 : #define RA_ELC_EVENT_SPI0_ERI 0x1C7
151 0 : #define RA_ELC_EVENT_SPI0_TEI 0x1C8
152 0 : #define RA_ELC_EVENT_SPI1_RXI 0x1C9
153 0 : #define RA_ELC_EVENT_SPI1_TXI 0x1CA
154 0 : #define RA_ELC_EVENT_SPI1_IDLE 0x1CB
155 0 : #define RA_ELC_EVENT_SPI1_ERI 0x1CC
156 0 : #define RA_ELC_EVENT_SPI1_TEI 0x1CD
157 0 : #define RA_ELC_EVENT_CAN0_MRAM_ERI 0x1D0
158 0 : #define RA_ELC_EVENT_DOC_INT 0x1DB
159 0 : #define RA_ELC_EVENT_I3C0_RESPONSE 0x1DC
160 0 : #define RA_ELC_EVENT_I3C0_COMMAND 0x1DD
161 0 : #define RA_ELC_EVENT_I3C0_IBI 0x1DE
162 0 : #define RA_ELC_EVENT_I3C0_RX 0x1DF
163 0 : #define RA_ELC_EVENT_IICB0_RXI 0x1DF
164 0 : #define RA_ELC_EVENT_I3C0_TX 0x1E0
165 0 : #define RA_ELC_EVENT_IICB0_TXI 0x1E0
166 0 : #define RA_ELC_EVENT_I3C0_RCV_STATUS 0x1E1
167 0 : #define RA_ELC_EVENT_I3C0_HRESP 0x1E2
168 0 : #define RA_ELC_EVENT_I3C0_HCMD 0x1E3
169 0 : #define RA_ELC_EVENT_I3C0_HRX 0x1E4
170 0 : #define RA_ELC_EVENT_I3C0_HTX 0x1E5
171 0 : #define RA_ELC_EVENT_I3C0_TEND 0x1E6
172 0 : #define RA_ELC_EVENT_IICB0_TEI 0x1E6
173 0 : #define RA_ELC_EVENT_I3C0_EEI 0x1E7
174 0 : #define RA_ELC_EVENT_IICB0_ERI 0x1E7
175 0 : #define RA_ELC_EVENT_I3C0_STEV 0x1E8
176 0 : #define RA_ELC_EVENT_I3C0_MREFOVF 0x1E9
177 0 : #define RA_ELC_EVENT_I3C0_MREFCPT 0x1EA
178 0 : #define RA_ELC_EVENT_I3C0_AMEV 0x1EB
179 0 : #define RA_ELC_EVENT_I3C0_WU 0x1EC
180 0 : #define RA_ELC_EVENT_TRNG_RDREQ 0x1F3
181 :
182 : /* Possible peripherals to be linked to event signals */
183 0 : #define RA_ELC_PERIPHERAL_GPT_A 0
184 0 : #define RA_ELC_PERIPHERAL_GPT_B 1
185 0 : #define RA_ELC_PERIPHERAL_GPT_C 2
186 0 : #define RA_ELC_PERIPHERAL_GPT_D 3
187 0 : #define RA_ELC_PERIPHERAL_GPT_E 4
188 0 : #define RA_ELC_PERIPHERAL_GPT_F 5
189 0 : #define RA_ELC_PERIPHERAL_GPT_G 6
190 0 : #define RA_ELC_PERIPHERAL_GPT_H 7
191 0 : #define RA_ELC_PERIPHERAL_ADC0 8
192 0 : #define RA_ELC_PERIPHERAL_ADC0_B 9
193 0 : #define RA_ELC_PERIPHERAL_DAC0 12
194 0 : #define RA_ELC_PERIPHERAL_IOPORT1 14
195 0 : #define RA_ELC_PERIPHERAL_IOPORT2 15
196 0 : #define RA_ELC_PERIPHERAL_IOPORT3 16
197 0 : #define RA_ELC_PERIPHERAL_IOPORT4 17
198 0 : #define RA_ELC_PERIPHERAL_I3C 23
199 :
200 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4E2_ELC_H_ */
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