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1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M1_ELC_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M1_ELC_H_
9 :
10 : /* Sources of event signals to be linked to other peripherals or the CPU */
11 0 : #define RA_ELC_EVENT_NONE 0x0
12 0 : #define RA_ELC_EVENT_ICU_IRQ0 0x001
13 0 : #define RA_ELC_EVENT_ICU_IRQ1 0x002
14 0 : #define RA_ELC_EVENT_ICU_IRQ2 0x003
15 0 : #define RA_ELC_EVENT_ICU_IRQ3 0x004
16 0 : #define RA_ELC_EVENT_ICU_IRQ4 0x005
17 0 : #define RA_ELC_EVENT_ICU_IRQ5 0x006
18 0 : #define RA_ELC_EVENT_ICU_IRQ6 0x007
19 0 : #define RA_ELC_EVENT_ICU_IRQ7 0x008
20 0 : #define RA_ELC_EVENT_ICU_IRQ8 0x009
21 0 : #define RA_ELC_EVENT_ICU_IRQ9 0x00A
22 0 : #define RA_ELC_EVENT_ICU_IRQ10 0x00B
23 0 : #define RA_ELC_EVENT_ICU_IRQ11 0x00C
24 0 : #define RA_ELC_EVENT_ICU_IRQ12 0x00D
25 0 : #define RA_ELC_EVENT_ICU_IRQ14 0x00F
26 0 : #define RA_ELC_EVENT_ICU_IRQ15 0x010
27 0 : #define RA_ELC_EVENT_DMAC0_INT 0x011
28 0 : #define RA_ELC_EVENT_DMAC1_INT 0x012
29 0 : #define RA_ELC_EVENT_DMAC2_INT 0x013
30 0 : #define RA_ELC_EVENT_DMAC3_INT 0x014
31 0 : #define RA_ELC_EVENT_DTC_COMPLETE 0x015
32 0 : #define RA_ELC_EVENT_DTC_END 0x016
33 0 : #define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x017
34 0 : #define RA_ELC_EVENT_FCU_FRDYI 0x018
35 0 : #define RA_ELC_EVENT_LVD_LVD1 0x019
36 0 : #define RA_ELC_EVENT_LVD_LVD2 0x01A
37 0 : #define RA_ELC_EVENT_LVD_VBATT 0x01B
38 0 : #define RA_ELC_EVENT_CGC_MOSC_STOP 0x01C
39 0 : #define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x01D
40 0 : #define RA_ELC_EVENT_AGT0_INT 0x01E
41 0 : #define RA_ELC_EVENT_AGT0_COMPARE_A 0x01F
42 0 : #define RA_ELC_EVENT_AGT0_COMPARE_B 0x020
43 0 : #define RA_ELC_EVENT_AGT1_INT 0x021
44 0 : #define RA_ELC_EVENT_AGT1_COMPARE_A 0x022
45 0 : #define RA_ELC_EVENT_AGT1_COMPARE_B 0x023
46 0 : #define RA_ELC_EVENT_IWDT_UNDERFLOW 0x024
47 0 : #define RA_ELC_EVENT_WDT_UNDERFLOW 0x025
48 0 : #define RA_ELC_EVENT_RTC_ALARM 0x026
49 0 : #define RA_ELC_EVENT_RTC_PERIOD 0x027
50 0 : #define RA_ELC_EVENT_RTC_CARRY 0x028
51 0 : #define RA_ELC_EVENT_ADC0_SCAN_END 0x029
52 0 : #define RA_ELC_EVENT_ADC0_SCAN_END_B 0x02A
53 0 : #define RA_ELC_EVENT_ADC0_WINDOW_A 0x02B
54 0 : #define RA_ELC_EVENT_ADC0_WINDOW_B 0x02C
55 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x02D
56 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x02E
57 0 : #define RA_ELC_EVENT_ACMPLP0_INT 0x02F
58 0 : #define RA_ELC_EVENT_ACMPLP1_INT 0x030
59 0 : #define RA_ELC_EVENT_USBFS_FIFO_0 0x031
60 0 : #define RA_ELC_EVENT_USBFS_FIFO_1 0x032
61 0 : #define RA_ELC_EVENT_USBFS_INT 0x033
62 0 : #define RA_ELC_EVENT_USBFS_RESUME 0x034
63 0 : #define RA_ELC_EVENT_IIC0_RXI 0x035
64 0 : #define RA_ELC_EVENT_IIC0_TXI 0x036
65 0 : #define RA_ELC_EVENT_IIC0_TEI 0x037
66 0 : #define RA_ELC_EVENT_IIC0_ERI 0x038
67 0 : #define RA_ELC_EVENT_IIC0_WUI 0x039
68 0 : #define RA_ELC_EVENT_IIC1_RXI 0x03A
69 0 : #define RA_ELC_EVENT_IIC1_TXI 0x03B
70 0 : #define RA_ELC_EVENT_IIC1_TEI 0x03C
71 0 : #define RA_ELC_EVENT_IIC1_ERI 0x03D
72 0 : #define RA_ELC_EVENT_SSI0_TXI 0x03E
73 0 : #define RA_ELC_EVENT_SSI0_RXI 0x03F
74 0 : #define RA_ELC_EVENT_SSI0_INT 0x041
75 0 : #define RA_ELC_EVENT_CTSU_WRITE 0x042
76 0 : #define RA_ELC_EVENT_CTSU_READ 0x043
77 0 : #define RA_ELC_EVENT_CTSU_END 0x044
78 0 : #define RA_ELC_EVENT_KEY_INT 0x045
79 0 : #define RA_ELC_EVENT_DOC_INT 0x046
80 0 : #define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x047
81 0 : #define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x048
82 0 : #define RA_ELC_EVENT_CAC_OVERFLOW 0x049
83 0 : #define RA_ELC_EVENT_CAN0_ERROR 0x04A
84 0 : #define RA_ELC_EVENT_CAN0_FIFO_RX 0x04B
85 0 : #define RA_ELC_EVENT_CAN0_FIFO_TX 0x04C
86 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x04D
87 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x04E
88 0 : #define RA_ELC_EVENT_IOPORT_EVENT_1 0x04F
89 0 : #define RA_ELC_EVENT_IOPORT_EVENT_2 0x050
90 0 : #define RA_ELC_EVENT_IOPORT_EVENT_3 0x051
91 0 : #define RA_ELC_EVENT_IOPORT_EVENT_4 0x052
92 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x053
93 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x054
94 0 : #define RA_ELC_EVENT_POEG0_EVENT 0x055
95 0 : #define RA_ELC_EVENT_POEG1_EVENT 0x056
96 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x057
97 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x058
98 0 : #define RA_ELC_EVENT_GPT0_COMPARE_C 0x059
99 0 : #define RA_ELC_EVENT_GPT0_COMPARE_D 0x05A
100 0 : #define RA_ELC_EVENT_GPT0_COMPARE_E 0x05B
101 0 : #define RA_ELC_EVENT_GPT0_COMPARE_F 0x05C
102 0 : #define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x05D
103 0 : #define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x05E
104 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x05F
105 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x060
106 0 : #define RA_ELC_EVENT_GPT1_COMPARE_C 0x061
107 0 : #define RA_ELC_EVENT_GPT1_COMPARE_D 0x062
108 0 : #define RA_ELC_EVENT_GPT1_COMPARE_E 0x063
109 0 : #define RA_ELC_EVENT_GPT1_COMPARE_F 0x064
110 0 : #define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x065
111 0 : #define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x066
112 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x067
113 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x068
114 0 : #define RA_ELC_EVENT_GPT2_COMPARE_C 0x069
115 0 : #define RA_ELC_EVENT_GPT2_COMPARE_D 0x06A
116 0 : #define RA_ELC_EVENT_GPT2_COMPARE_E 0x06B
117 0 : #define RA_ELC_EVENT_GPT2_COMPARE_F 0x06C
118 0 : #define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x06D
119 0 : #define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x06E
120 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x06F
121 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x070
122 0 : #define RA_ELC_EVENT_GPT3_COMPARE_C 0x071
123 0 : #define RA_ELC_EVENT_GPT3_COMPARE_D 0x072
124 0 : #define RA_ELC_EVENT_GPT3_COMPARE_E 0x073
125 0 : #define RA_ELC_EVENT_GPT3_COMPARE_F 0x074
126 0 : #define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x075
127 0 : #define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x076
128 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x077
129 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x078
130 0 : #define RA_ELC_EVENT_GPT4_COMPARE_C 0x079
131 0 : #define RA_ELC_EVENT_GPT4_COMPARE_D 0x07A
132 0 : #define RA_ELC_EVENT_GPT4_COMPARE_E 0x07B
133 0 : #define RA_ELC_EVENT_GPT4_COMPARE_F 0x07C
134 0 : #define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x07D
135 0 : #define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x07E
136 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x07F
137 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x080
138 0 : #define RA_ELC_EVENT_GPT5_COMPARE_C 0x081
139 0 : #define RA_ELC_EVENT_GPT5_COMPARE_D 0x082
140 0 : #define RA_ELC_EVENT_GPT5_COMPARE_E 0x083
141 0 : #define RA_ELC_EVENT_GPT5_COMPARE_F 0x084
142 0 : #define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x085
143 0 : #define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x086
144 0 : #define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x087
145 0 : #define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x088
146 0 : #define RA_ELC_EVENT_GPT6_COMPARE_C 0x089
147 0 : #define RA_ELC_EVENT_GPT6_COMPARE_D 0x08A
148 0 : #define RA_ELC_EVENT_GPT6_COMPARE_E 0x08B
149 0 : #define RA_ELC_EVENT_GPT6_COMPARE_F 0x08C
150 0 : #define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x08D
151 0 : #define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x08E
152 0 : #define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x08F
153 0 : #define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x090
154 0 : #define RA_ELC_EVENT_GPT7_COMPARE_C 0x091
155 0 : #define RA_ELC_EVENT_GPT7_COMPARE_D 0x092
156 0 : #define RA_ELC_EVENT_GPT7_COMPARE_E 0x093
157 0 : #define RA_ELC_EVENT_GPT7_COMPARE_F 0x094
158 0 : #define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x095
159 0 : #define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x096
160 0 : #define RA_ELC_EVENT_OPS_UVW_EDGE 0x097
161 0 : #define RA_ELC_EVENT_SCI0_RXI 0x098
162 0 : #define RA_ELC_EVENT_SCI0_TXI 0x099
163 0 : #define RA_ELC_EVENT_SCI0_TEI 0x09A
164 0 : #define RA_ELC_EVENT_SCI0_ERI 0x09B
165 0 : #define RA_ELC_EVENT_SCI0_AM 0x09C
166 0 : #define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x09D
167 0 : #define RA_ELC_EVENT_SCI1_RXI 0x09E
168 0 : #define RA_ELC_EVENT_SCI1_TXI 0x09F
169 0 : #define RA_ELC_EVENT_SCI1_TEI 0x0A0
170 0 : #define RA_ELC_EVENT_SCI1_ERI 0x0A1
171 0 : #define RA_ELC_EVENT_SCI1_AM 0x0A2
172 0 : #define RA_ELC_EVENT_SCI2_RXI 0x0A3
173 0 : #define RA_ELC_EVENT_SCI2_TXI 0x0A4
174 0 : #define RA_ELC_EVENT_SCI2_TEI 0x0A5
175 0 : #define RA_ELC_EVENT_SCI2_ERI 0x0A6
176 0 : #define RA_ELC_EVENT_SCI2_AM 0x0A7
177 0 : #define RA_ELC_EVENT_SCI9_RXI 0x0A8
178 0 : #define RA_ELC_EVENT_SCI9_TXI 0x0A9
179 0 : #define RA_ELC_EVENT_SCI9_TEI 0x0AA
180 0 : #define RA_ELC_EVENT_SCI9_ERI 0x0AB
181 0 : #define RA_ELC_EVENT_SCI9_AM 0x0AC
182 0 : #define RA_ELC_EVENT_SPI0_RXI 0x0AD
183 0 : #define RA_ELC_EVENT_SPI0_TXI 0x0AE
184 0 : #define RA_ELC_EVENT_SPI0_IDLE 0x0AF
185 0 : #define RA_ELC_EVENT_SPI0_ERI 0x0B0
186 0 : #define RA_ELC_EVENT_SPI0_TEI 0x0B1
187 0 : #define RA_ELC_EVENT_SPI1_RXI 0x0B2
188 0 : #define RA_ELC_EVENT_SPI1_TXI 0x0B3
189 0 : #define RA_ELC_EVENT_SPI1_IDLE 0x0B4
190 0 : #define RA_ELC_EVENT_SPI1_ERI 0x0B5
191 0 : #define RA_ELC_EVENT_SPI1_TEI 0x0B6
192 :
193 : /* Possible peripherals to be linked to event signals */
194 0 : #define RA_ELC_PERIPHERAL_GPT_A 0
195 0 : #define RA_ELC_PERIPHERAL_GPT_B 1
196 0 : #define RA_ELC_PERIPHERAL_GPT_C 2
197 0 : #define RA_ELC_PERIPHERAL_GPT_D 3
198 0 : #define RA_ELC_PERIPHERAL_GPT_E 4
199 0 : #define RA_ELC_PERIPHERAL_GPT_F 5
200 0 : #define RA_ELC_PERIPHERAL_GPT_G 6
201 0 : #define RA_ELC_PERIPHERAL_GPT_H 7
202 0 : #define RA_ELC_PERIPHERAL_ADC0 8
203 0 : #define RA_ELC_PERIPHERAL_ADC0_B 9
204 0 : #define RA_ELC_PERIPHERAL_DAC0 12
205 0 : #define RA_ELC_PERIPHERAL_IOPORT1 14
206 0 : #define RA_ELC_PERIPHERAL_IOPORT2 15
207 0 : #define RA_ELC_PERIPHERAL_IOPORT3 16
208 0 : #define RA_ELC_PERIPHERAL_IOPORT4 17
209 0 : #define RA_ELC_PERIPHERAL_CTSU 18
210 :
211 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M1_ELC_H_ */
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