Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4W1_ELC_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4W1_ELC_H_
9 :
10 : /* Sources of event signals to be linked to other peripherals or the CPU */
11 0 : #define RA_ELC_EVENT_NONE 0x0
12 0 : #define RA_ELC_EVENT_ICU_IRQ0 0x001
13 0 : #define RA_ELC_EVENT_ICU_IRQ1 0x002
14 0 : #define RA_ELC_EVENT_ICU_IRQ2 0x003
15 0 : #define RA_ELC_EVENT_ICU_IRQ3 0x004
16 0 : #define RA_ELC_EVENT_ICU_IRQ4 0x005
17 0 : #define RA_ELC_EVENT_ICU_IRQ6 0x007
18 0 : #define RA_ELC_EVENT_ICU_IRQ7 0x008
19 0 : #define RA_ELC_EVENT_ICU_IRQ8 0x009
20 0 : #define RA_ELC_EVENT_ICU_IRQ9 0x00A
21 0 : #define RA_ELC_EVENT_ICU_IRQ11 0x00C
22 0 : #define RA_ELC_EVENT_ICU_IRQ14 0x00F
23 0 : #define RA_ELC_EVENT_ICU_IRQ15 0x010
24 0 : #define RA_ELC_EVENT_DMAC0_INT 0x011
25 0 : #define RA_ELC_EVENT_DMAC1_INT 0x012
26 0 : #define RA_ELC_EVENT_DMAC2_INT 0x013
27 0 : #define RA_ELC_EVENT_DMAC3_INT 0x014
28 0 : #define RA_ELC_EVENT_DTC_COMPLETE 0x015
29 0 : #define RA_ELC_EVENT_DTC_END 0x016
30 0 : #define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x017
31 0 : #define RA_ELC_EVENT_FCU_FRDYI 0x018
32 0 : #define RA_ELC_EVENT_LVD_LVD1 0x019
33 0 : #define RA_ELC_EVENT_LVD_VBATT 0x01B
34 0 : #define RA_ELC_EVENT_CGC_MOSC_STOP 0x01C
35 0 : #define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x01D
36 0 : #define RA_ELC_EVENT_AGT0_INT 0x01E
37 0 : #define RA_ELC_EVENT_AGT0_COMPARE_A 0x01F
38 0 : #define RA_ELC_EVENT_AGT0_COMPARE_B 0x020
39 0 : #define RA_ELC_EVENT_AGT1_INT 0x021
40 0 : #define RA_ELC_EVENT_AGT1_COMPARE_A 0x022
41 0 : #define RA_ELC_EVENT_AGT1_COMPARE_B 0x023
42 0 : #define RA_ELC_EVENT_IWDT_UNDERFLOW 0x024
43 0 : #define RA_ELC_EVENT_WDT_UNDERFLOW 0x025
44 0 : #define RA_ELC_EVENT_RTC_ALARM 0x026
45 0 : #define RA_ELC_EVENT_RTC_PERIOD 0x027
46 0 : #define RA_ELC_EVENT_RTC_CARRY 0x028
47 0 : #define RA_ELC_EVENT_ADC0_SCAN_END 0x029
48 0 : #define RA_ELC_EVENT_ADC0_SCAN_END_B 0x02A
49 0 : #define RA_ELC_EVENT_ADC0_WINDOW_A 0x02B
50 0 : #define RA_ELC_EVENT_ADC0_WINDOW_B 0x02C
51 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x02D
52 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x02E
53 0 : #define RA_ELC_EVENT_ACMPLP0_INT 0x02F
54 0 : #define RA_ELC_EVENT_ACMPLP1_INT 0x030
55 0 : #define RA_ELC_EVENT_USBFS_FIFO_0 0x031
56 0 : #define RA_ELC_EVENT_USBFS_FIFO_1 0x032
57 0 : #define RA_ELC_EVENT_USBFS_INT 0x033
58 0 : #define RA_ELC_EVENT_USBFS_RESUME 0x034
59 0 : #define RA_ELC_EVENT_IIC0_RXI 0x035
60 0 : #define RA_ELC_EVENT_IIC0_TXI 0x036
61 0 : #define RA_ELC_EVENT_IIC0_TEI 0x037
62 0 : #define RA_ELC_EVENT_IIC0_ERI 0x038
63 0 : #define RA_ELC_EVENT_IIC0_WUI 0x039
64 0 : #define RA_ELC_EVENT_IIC1_RXI 0x03A
65 0 : #define RA_ELC_EVENT_IIC1_TXI 0x03B
66 0 : #define RA_ELC_EVENT_IIC1_TEI 0x03C
67 0 : #define RA_ELC_EVENT_IIC1_ERI 0x03D
68 0 : #define RA_ELC_EVENT_CTSU_WRITE 0x046
69 0 : #define RA_ELC_EVENT_CTSU_READ 0x047
70 0 : #define RA_ELC_EVENT_CTSU_END 0x048
71 0 : #define RA_ELC_EVENT_KEY_INT 0x049
72 0 : #define RA_ELC_EVENT_DOC_INT 0x04A
73 0 : #define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x04B
74 0 : #define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x04C
75 0 : #define RA_ELC_EVENT_CAC_OVERFLOW 0x04D
76 0 : #define RA_ELC_EVENT_CAN0_ERROR 0x04E
77 0 : #define RA_ELC_EVENT_CAN0_FIFO_RX 0x04F
78 0 : #define RA_ELC_EVENT_CAN0_FIFO_TX 0x050
79 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x051
80 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x052
81 0 : #define RA_ELC_EVENT_IOPORT_EVENT_1 0x053
82 0 : #define RA_ELC_EVENT_IOPORT_EVENT_2 0x054
83 0 : #define RA_ELC_EVENT_IOPORT_EVENT_3 0x055
84 0 : #define RA_ELC_EVENT_IOPORT_EVENT_4 0x056
85 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x057
86 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x058
87 0 : #define RA_ELC_EVENT_POEG0_EVENT 0x059
88 0 : #define RA_ELC_EVENT_POEG1_EVENT 0x05A
89 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x05B
90 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x05C
91 0 : #define RA_ELC_EVENT_GPT0_COMPARE_C 0x05D
92 0 : #define RA_ELC_EVENT_GPT0_COMPARE_D 0x05E
93 0 : #define RA_ELC_EVENT_GPT0_COMPARE_E 0x05F
94 0 : #define RA_ELC_EVENT_GPT0_COMPARE_F 0x060
95 0 : #define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x061
96 0 : #define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x062
97 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x063
98 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x064
99 0 : #define RA_ELC_EVENT_GPT1_COMPARE_C 0x065
100 0 : #define RA_ELC_EVENT_GPT1_COMPARE_D 0x066
101 0 : #define RA_ELC_EVENT_GPT1_COMPARE_E 0x067
102 0 : #define RA_ELC_EVENT_GPT1_COMPARE_F 0x068
103 0 : #define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x069
104 0 : #define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x06A
105 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x06B
106 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x06C
107 0 : #define RA_ELC_EVENT_GPT2_COMPARE_C 0x06D
108 0 : #define RA_ELC_EVENT_GPT2_COMPARE_D 0x06E
109 0 : #define RA_ELC_EVENT_GPT2_COMPARE_E 0x06F
110 0 : #define RA_ELC_EVENT_GPT2_COMPARE_F 0x070
111 0 : #define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x071
112 0 : #define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x072
113 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x073
114 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x074
115 0 : #define RA_ELC_EVENT_GPT3_COMPARE_C 0x075
116 0 : #define RA_ELC_EVENT_GPT3_COMPARE_D 0x076
117 0 : #define RA_ELC_EVENT_GPT3_COMPARE_E 0x077
118 0 : #define RA_ELC_EVENT_GPT3_COMPARE_F 0x078
119 0 : #define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x079
120 0 : #define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x07A
121 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x07B
122 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x07C
123 0 : #define RA_ELC_EVENT_GPT4_COMPARE_C 0x07D
124 0 : #define RA_ELC_EVENT_GPT4_COMPARE_D 0x07E
125 0 : #define RA_ELC_EVENT_GPT4_COMPARE_E 0x07F
126 0 : #define RA_ELC_EVENT_GPT4_COMPARE_F 0x080
127 0 : #define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x081
128 0 : #define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x082
129 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x083
130 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x084
131 0 : #define RA_ELC_EVENT_GPT5_COMPARE_C 0x085
132 0 : #define RA_ELC_EVENT_GPT5_COMPARE_D 0x086
133 0 : #define RA_ELC_EVENT_GPT5_COMPARE_E 0x087
134 0 : #define RA_ELC_EVENT_GPT5_COMPARE_F 0x088
135 0 : #define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x089
136 0 : #define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x08A
137 0 : #define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x09B
138 0 : #define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x09C
139 0 : #define RA_ELC_EVENT_GPT8_COMPARE_C 0x09D
140 0 : #define RA_ELC_EVENT_GPT8_COMPARE_D 0x09E
141 0 : #define RA_ELC_EVENT_GPT8_COMPARE_E 0x09F
142 0 : #define RA_ELC_EVENT_GPT8_COMPARE_F 0x0A0
143 0 : #define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x0A1
144 0 : #define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x0A2
145 0 : #define RA_ELC_EVENT_OPS_UVW_EDGE 0x0AB
146 0 : #define RA_ELC_EVENT_SCI0_RXI 0x0AC
147 0 : #define RA_ELC_EVENT_SCI0_TXI 0x0AD
148 0 : #define RA_ELC_EVENT_SCI0_TEI 0x0AE
149 0 : #define RA_ELC_EVENT_SCI0_ERI 0x0AF
150 0 : #define RA_ELC_EVENT_SCI0_AM 0x0B0
151 0 : #define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x0B1
152 0 : #define RA_ELC_EVENT_SCI1_RXI 0x0B2
153 0 : #define RA_ELC_EVENT_SCI1_TXI 0x0B3
154 0 : #define RA_ELC_EVENT_SCI1_TEI 0x0B4
155 0 : #define RA_ELC_EVENT_SCI1_ERI 0x0B5
156 0 : #define RA_ELC_EVENT_SCI1_AM 0x0B6
157 0 : #define RA_ELC_EVENT_SCI4_RXI 0x0C1
158 0 : #define RA_ELC_EVENT_SCI4_TXI 0x0C2
159 0 : #define RA_ELC_EVENT_SCI4_TEI 0x0C3
160 0 : #define RA_ELC_EVENT_SCI4_ERI 0x0C4
161 0 : #define RA_ELC_EVENT_SCI4_AM 0x0C5
162 0 : #define RA_ELC_EVENT_SCI9_RXI 0x0C6
163 0 : #define RA_ELC_EVENT_SCI9_TXI 0x0C7
164 0 : #define RA_ELC_EVENT_SCI9_TEI 0x0C8
165 0 : #define RA_ELC_EVENT_SCI9_ERI 0x0C9
166 0 : #define RA_ELC_EVENT_SCI9_AM 0x0CA
167 0 : #define RA_ELC_EVENT_SPI0_RXI 0x0CB
168 0 : #define RA_ELC_EVENT_SPI0_TXI 0x0CC
169 0 : #define RA_ELC_EVENT_SPI0_IDLE 0x0CD
170 0 : #define RA_ELC_EVENT_SPI0_ERI 0x0CE
171 0 : #define RA_ELC_EVENT_SPI0_TEI 0x0CF
172 0 : #define RA_ELC_EVENT_SPI1_RXI 0x0D0
173 0 : #define RA_ELC_EVENT_SPI1_TXI 0x0D1
174 0 : #define RA_ELC_EVENT_SPI1_IDLE 0x0D2
175 0 : #define RA_ELC_EVENT_SPI1_ERI 0x0D3
176 0 : #define RA_ELC_EVENT_SPI1_TEI 0x0D4
177 :
178 : /* Possible peripherals to be linked to event signals */
179 0 : #define RA_ELC_PERIPHERAL_GPT_A 0
180 0 : #define RA_ELC_PERIPHERAL_GPT_B 1
181 0 : #define RA_ELC_PERIPHERAL_GPT_C 2
182 0 : #define RA_ELC_PERIPHERAL_GPT_D 3
183 0 : #define RA_ELC_PERIPHERAL_GPT_E 4
184 0 : #define RA_ELC_PERIPHERAL_GPT_F 5
185 0 : #define RA_ELC_PERIPHERAL_GPT_G 6
186 0 : #define RA_ELC_PERIPHERAL_GPT_H 7
187 0 : #define RA_ELC_PERIPHERAL_ADC0 8
188 0 : #define RA_ELC_PERIPHERAL_ADC0_B 9
189 0 : #define RA_ELC_PERIPHERAL_DAC0 12
190 0 : #define RA_ELC_PERIPHERAL_IOPORT1 14
191 0 : #define RA_ELC_PERIPHERAL_IOPORT2 15
192 0 : #define RA_ELC_PERIPHERAL_IOPORT3 16
193 0 : #define RA_ELC_PERIPHERAL_IOPORT4 17
194 0 : #define RA_ELC_PERIPHERAL_CTSU 18
195 :
196 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4W1_ELC_H_ */
|
