Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M1_ELC_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M1_ELC_H_
9 :
10 : /* Sources of event signals to be linked to other peripherals or the CPU */
11 0 : #define RA_ELC_EVENT_NONE 0x0
12 0 : #define RA_ELC_EVENT_ICU_IRQ0 0x001
13 0 : #define RA_ELC_EVENT_ICU_IRQ1 0x002
14 0 : #define RA_ELC_EVENT_ICU_IRQ2 0x003
15 0 : #define RA_ELC_EVENT_ICU_IRQ3 0x004
16 0 : #define RA_ELC_EVENT_ICU_IRQ4 0x005
17 0 : #define RA_ELC_EVENT_ICU_IRQ5 0x006
18 0 : #define RA_ELC_EVENT_ICU_IRQ6 0x007
19 0 : #define RA_ELC_EVENT_ICU_IRQ7 0x008
20 0 : #define RA_ELC_EVENT_ICU_IRQ8 0x009
21 0 : #define RA_ELC_EVENT_ICU_IRQ9 0x00A
22 0 : #define RA_ELC_EVENT_ICU_IRQ10 0x00B
23 0 : #define RA_ELC_EVENT_ICU_IRQ11 0x00C
24 0 : #define RA_ELC_EVENT_ICU_IRQ12 0x00D
25 0 : #define RA_ELC_EVENT_ICU_IRQ13 0x00E
26 0 : #define RA_ELC_EVENT_DMAC0_INT 0x020
27 0 : #define RA_ELC_EVENT_DMAC1_INT 0x021
28 0 : #define RA_ELC_EVENT_DMAC2_INT 0x022
29 0 : #define RA_ELC_EVENT_DMAC3_INT 0x023
30 0 : #define RA_ELC_EVENT_DMAC4_INT 0x024
31 0 : #define RA_ELC_EVENT_DMAC5_INT 0x025
32 0 : #define RA_ELC_EVENT_DMAC6_INT 0x026
33 0 : #define RA_ELC_EVENT_DMAC7_INT 0x027
34 0 : #define RA_ELC_EVENT_DTC_COMPLETE 0x029
35 0 : #define RA_ELC_EVENT_DTC_END 0x02A
36 0 : #define RA_ELC_EVENT_ICU_SNOOZE_CANCEL 0x02D
37 0 : #define RA_ELC_EVENT_FCU_FIFERR 0x030
38 0 : #define RA_ELC_EVENT_FCU_FRDYI 0x031
39 0 : #define RA_ELC_EVENT_LVD_LVD1 0x038
40 0 : #define RA_ELC_EVENT_LVD_LVD2 0x039
41 0 : #define RA_ELC_EVENT_CGC_MOSC_STOP 0x03B
42 0 : #define RA_ELC_EVENT_LPM_SNOOZE_REQUEST 0x03C
43 0 : #define RA_ELC_EVENT_AGT0_INT 0x040
44 0 : #define RA_ELC_EVENT_AGT0_COMPARE_A 0x041
45 0 : #define RA_ELC_EVENT_AGT0_COMPARE_B 0x042
46 0 : #define RA_ELC_EVENT_AGT1_INT 0x043
47 0 : #define RA_ELC_EVENT_AGT1_COMPARE_A 0x044
48 0 : #define RA_ELC_EVENT_AGT1_COMPARE_B 0x045
49 0 : #define RA_ELC_EVENT_IWDT_UNDERFLOW 0x046
50 0 : #define RA_ELC_EVENT_WDT_UNDERFLOW 0x047
51 0 : #define RA_ELC_EVENT_RTC_ALARM 0x048
52 0 : #define RA_ELC_EVENT_RTC_PERIOD 0x049
53 0 : #define RA_ELC_EVENT_RTC_CARRY 0x04A
54 0 : #define RA_ELC_EVENT_ADC0_SCAN_END 0x04B
55 0 : #define RA_ELC_EVENT_ADC0_SCAN_END_B 0x04C
56 0 : #define RA_ELC_EVENT_ADC0_WINDOW_A 0x04D
57 0 : #define RA_ELC_EVENT_ADC0_WINDOW_B 0x04E
58 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x04F
59 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x050
60 0 : #define RA_ELC_EVENT_ADC1_SCAN_END 0x051
61 0 : #define RA_ELC_EVENT_ADC1_SCAN_END_B 0x052
62 0 : #define RA_ELC_EVENT_ADC1_WINDOW_A 0x053
63 0 : #define RA_ELC_EVENT_ADC1_WINDOW_B 0x054
64 0 : #define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x055
65 0 : #define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x056
66 0 : #define RA_ELC_EVENT_ACMPHS0_INT 0x057
67 0 : #define RA_ELC_EVENT_ACMPHS1_INT 0x058
68 0 : #define RA_ELC_EVENT_ACMPHS2_INT 0x059
69 0 : #define RA_ELC_EVENT_ACMPHS3_INT 0x05A
70 0 : #define RA_ELC_EVENT_ACMPHS4_INT 0x05B
71 0 : #define RA_ELC_EVENT_ACMPHS5_INT 0x05C
72 0 : #define RA_ELC_EVENT_USBFS_FIFO_0 0x05F
73 0 : #define RA_ELC_EVENT_USBFS_FIFO_1 0x060
74 0 : #define RA_ELC_EVENT_USBFS_INT 0x061
75 0 : #define RA_ELC_EVENT_USBFS_RESUME 0x062
76 0 : #define RA_ELC_EVENT_IIC0_RXI 0x063
77 0 : #define RA_ELC_EVENT_IIC0_TXI 0x064
78 0 : #define RA_ELC_EVENT_IIC0_TEI 0x065
79 0 : #define RA_ELC_EVENT_IIC0_ERI 0x066
80 0 : #define RA_ELC_EVENT_IIC0_WUI 0x067
81 0 : #define RA_ELC_EVENT_IIC1_RXI 0x068
82 0 : #define RA_ELC_EVENT_IIC1_TXI 0x069
83 0 : #define RA_ELC_EVENT_IIC1_TEI 0x06A
84 0 : #define RA_ELC_EVENT_IIC1_ERI 0x06B
85 0 : #define RA_ELC_EVENT_SSI0_TXI 0x072
86 0 : #define RA_ELC_EVENT_SSI0_RXI 0x073
87 0 : #define RA_ELC_EVENT_SSI0_INT 0x075
88 0 : #define RA_ELC_EVENT_SRC_INPUT_FIFO_EMPTY 0x07A
89 0 : #define RA_ELC_EVENT_SRC_OUTPUT_FIFO_FULL 0x07B
90 0 : #define RA_ELC_EVENT_SRC_OUTPUT_FIFO_OVERFLOW 0x07C
91 0 : #define RA_ELC_EVENT_SRC_OUTPUT_FIFO_UNDERFLOW 0x07D
92 0 : #define RA_ELC_EVENT_SRC_CONVERSION_END 0x07E
93 0 : #define RA_ELC_EVENT_CTSU_WRITE 0x082
94 0 : #define RA_ELC_EVENT_CTSU_READ 0x083
95 0 : #define RA_ELC_EVENT_CTSU_END 0x084
96 0 : #define RA_ELC_EVENT_KEY_INT 0x085
97 0 : #define RA_ELC_EVENT_DOC_INT 0x086
98 0 : #define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x087
99 0 : #define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x088
100 0 : #define RA_ELC_EVENT_CAC_OVERFLOW 0x089
101 0 : #define RA_ELC_EVENT_CAN0_ERROR 0x08A
102 0 : #define RA_ELC_EVENT_CAN0_FIFO_RX 0x08B
103 0 : #define RA_ELC_EVENT_CAN0_FIFO_TX 0x08C
104 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_RX 0x08D
105 0 : #define RA_ELC_EVENT_CAN0_MAILBOX_TX 0x08E
106 0 : #define RA_ELC_EVENT_CAN1_ERROR 0x08F
107 0 : #define RA_ELC_EVENT_CAN1_FIFO_RX 0x090
108 0 : #define RA_ELC_EVENT_CAN1_FIFO_TX 0x091
109 0 : #define RA_ELC_EVENT_CAN1_MAILBOX_RX 0x092
110 0 : #define RA_ELC_EVENT_CAN1_MAILBOX_TX 0x093
111 0 : #define RA_ELC_EVENT_IOPORT_EVENT_1 0x094
112 0 : #define RA_ELC_EVENT_IOPORT_EVENT_2 0x095
113 0 : #define RA_ELC_EVENT_IOPORT_EVENT_3 0x096
114 0 : #define RA_ELC_EVENT_IOPORT_EVENT_4 0x097
115 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x098
116 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x099
117 0 : #define RA_ELC_EVENT_POEG0_EVENT 0x09A
118 0 : #define RA_ELC_EVENT_POEG1_EVENT 0x09B
119 0 : #define RA_ELC_EVENT_POEG2_EVENT 0x09C
120 0 : #define RA_ELC_EVENT_POEG3_EVENT 0x09D
121 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0B0
122 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0B1
123 0 : #define RA_ELC_EVENT_GPT0_COMPARE_C 0x0B2
124 0 : #define RA_ELC_EVENT_GPT0_COMPARE_D 0x0B3
125 0 : #define RA_ELC_EVENT_GPT0_COMPARE_E 0x0B4
126 0 : #define RA_ELC_EVENT_GPT0_COMPARE_F 0x0B5
127 0 : #define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0B6
128 0 : #define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0B7
129 0 : #define RA_ELC_EVENT_GPT0_AD_TRIG_A 0x0B8
130 0 : #define RA_ELC_EVENT_GPT0_AD_TRIG_B 0x0B9
131 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0BA
132 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0BB
133 0 : #define RA_ELC_EVENT_GPT1_COMPARE_C 0x0BC
134 0 : #define RA_ELC_EVENT_GPT1_COMPARE_D 0x0BD
135 0 : #define RA_ELC_EVENT_GPT1_COMPARE_E 0x0BE
136 0 : #define RA_ELC_EVENT_GPT1_COMPARE_F 0x0BF
137 0 : #define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0C0
138 0 : #define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0C1
139 0 : #define RA_ELC_EVENT_GPT1_AD_TRIG_A 0x0C2
140 0 : #define RA_ELC_EVENT_GPT1_AD_TRIG_B 0x0C3
141 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0C4
142 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0C5
143 0 : #define RA_ELC_EVENT_GPT2_COMPARE_C 0x0C6
144 0 : #define RA_ELC_EVENT_GPT2_COMPARE_D 0x0C7
145 0 : #define RA_ELC_EVENT_GPT2_COMPARE_E 0x0C8
146 0 : #define RA_ELC_EVENT_GPT2_COMPARE_F 0x0C9
147 0 : #define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0CA
148 0 : #define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0CB
149 0 : #define RA_ELC_EVENT_GPT2_AD_TRIG_A 0x0CC
150 0 : #define RA_ELC_EVENT_GPT2_AD_TRIG_B 0x0CD
151 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0CE
152 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0CF
153 0 : #define RA_ELC_EVENT_GPT3_COMPARE_C 0x0D0
154 0 : #define RA_ELC_EVENT_GPT3_COMPARE_D 0x0D1
155 0 : #define RA_ELC_EVENT_GPT3_COMPARE_E 0x0D2
156 0 : #define RA_ELC_EVENT_GPT3_COMPARE_F 0x0D3
157 0 : #define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0D4
158 0 : #define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0D5
159 0 : #define RA_ELC_EVENT_GPT3_AD_TRIG_A 0x0D6
160 0 : #define RA_ELC_EVENT_GPT3_AD_TRIG_B 0x0D7
161 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0D8
162 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0D9
163 0 : #define RA_ELC_EVENT_GPT4_COMPARE_C 0x0DA
164 0 : #define RA_ELC_EVENT_GPT4_COMPARE_D 0x0DB
165 0 : #define RA_ELC_EVENT_GPT4_COMPARE_E 0x0DC
166 0 : #define RA_ELC_EVENT_GPT4_COMPARE_F 0x0DD
167 0 : #define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0DE
168 0 : #define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0DF
169 0 : #define RA_ELC_EVENT_GPT4_AD_TRIG_A 0x0E0
170 0 : #define RA_ELC_EVENT_GPT4_AD_TRIG_B 0x0E1
171 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0E2
172 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0E3
173 0 : #define RA_ELC_EVENT_GPT5_COMPARE_C 0x0E4
174 0 : #define RA_ELC_EVENT_GPT5_COMPARE_D 0x0E5
175 0 : #define RA_ELC_EVENT_GPT5_COMPARE_E 0x0E6
176 0 : #define RA_ELC_EVENT_GPT5_COMPARE_F 0x0E7
177 0 : #define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0E8
178 0 : #define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0E9
179 0 : #define RA_ELC_EVENT_GPT5_AD_TRIG_A 0x0EA
180 0 : #define RA_ELC_EVENT_GPT5_AD_TRIG_B 0x0EB
181 0 : #define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0EC
182 0 : #define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0ED
183 0 : #define RA_ELC_EVENT_GPT6_COMPARE_C 0x0EE
184 0 : #define RA_ELC_EVENT_GPT6_COMPARE_D 0x0EF
185 0 : #define RA_ELC_EVENT_GPT6_COMPARE_E 0x0F0
186 0 : #define RA_ELC_EVENT_GPT6_COMPARE_F 0x0F1
187 0 : #define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0F2
188 0 : #define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0F3
189 0 : #define RA_ELC_EVENT_GPT6_AD_TRIG_A 0x0F4
190 0 : #define RA_ELC_EVENT_GPT6_AD_TRIG_B 0x0F5
191 0 : #define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0F6
192 0 : #define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x0F7
193 0 : #define RA_ELC_EVENT_GPT7_COMPARE_C 0x0F8
194 0 : #define RA_ELC_EVENT_GPT7_COMPARE_D 0x0F9
195 0 : #define RA_ELC_EVENT_GPT7_COMPARE_E 0x0FA
196 0 : #define RA_ELC_EVENT_GPT7_COMPARE_F 0x0FB
197 0 : #define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x0FC
198 0 : #define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x0FD
199 0 : #define RA_ELC_EVENT_GPT7_AD_TRIG_A 0x0FE
200 0 : #define RA_ELC_EVENT_GPT7_AD_TRIG_B 0x0FF
201 0 : #define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x100
202 0 : #define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x101
203 0 : #define RA_ELC_EVENT_GPT8_COMPARE_C 0x102
204 0 : #define RA_ELC_EVENT_GPT8_COMPARE_D 0x103
205 0 : #define RA_ELC_EVENT_GPT8_COMPARE_E 0x104
206 0 : #define RA_ELC_EVENT_GPT8_COMPARE_F 0x105
207 0 : #define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x106
208 0 : #define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x107
209 0 : #define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x10A
210 0 : #define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x10B
211 0 : #define RA_ELC_EVENT_GPT9_COMPARE_C 0x10C
212 0 : #define RA_ELC_EVENT_GPT9_COMPARE_D 0x10D
213 0 : #define RA_ELC_EVENT_GPT9_COMPARE_E 0x10E
214 0 : #define RA_ELC_EVENT_GPT9_COMPARE_F 0x10F
215 0 : #define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x110
216 0 : #define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x111
217 0 : #define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_A 0x114
218 0 : #define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_B 0x115
219 0 : #define RA_ELC_EVENT_GPT10_COMPARE_C 0x116
220 0 : #define RA_ELC_EVENT_GPT10_COMPARE_D 0x117
221 0 : #define RA_ELC_EVENT_GPT10_COMPARE_E 0x118
222 0 : #define RA_ELC_EVENT_GPT10_COMPARE_F 0x119
223 0 : #define RA_ELC_EVENT_GPT10_COUNTER_OVERFLOW 0x11A
224 0 : #define RA_ELC_EVENT_GPT10_COUNTER_UNDERFLOW 0x11B
225 0 : #define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_A 0x11E
226 0 : #define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_B 0x11F
227 0 : #define RA_ELC_EVENT_GPT11_COMPARE_C 0x120
228 0 : #define RA_ELC_EVENT_GPT11_COMPARE_D 0x121
229 0 : #define RA_ELC_EVENT_GPT11_COMPARE_E 0x122
230 0 : #define RA_ELC_EVENT_GPT11_COMPARE_F 0x123
231 0 : #define RA_ELC_EVENT_GPT11_COUNTER_OVERFLOW 0x124
232 0 : #define RA_ELC_EVENT_GPT11_COUNTER_UNDERFLOW 0x125
233 0 : #define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_A 0x128
234 0 : #define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_B 0x129
235 0 : #define RA_ELC_EVENT_GPT12_COMPARE_C 0x12A
236 0 : #define RA_ELC_EVENT_GPT12_COMPARE_D 0x12B
237 0 : #define RA_ELC_EVENT_GPT12_COMPARE_E 0x12C
238 0 : #define RA_ELC_EVENT_GPT12_COMPARE_F 0x12D
239 0 : #define RA_ELC_EVENT_GPT12_COUNTER_OVERFLOW 0x12E
240 0 : #define RA_ELC_EVENT_GPT12_COUNTER_UNDERFLOW 0x12F
241 0 : #define RA_ELC_EVENT_OPS_UVW_EDGE 0x150
242 0 : #define RA_ELC_EVENT_SCI0_RXI 0x174
243 0 : #define RA_ELC_EVENT_SCI0_TXI 0x175
244 0 : #define RA_ELC_EVENT_SCI0_TEI 0x176
245 0 : #define RA_ELC_EVENT_SCI0_ERI 0x177
246 0 : #define RA_ELC_EVENT_SCI0_AM 0x178
247 0 : #define RA_ELC_EVENT_SCI0_RXI_OR_ERI 0x179
248 0 : #define RA_ELC_EVENT_SCI1_RXI 0x17A
249 0 : #define RA_ELC_EVENT_SCI1_TXI 0x17B
250 0 : #define RA_ELC_EVENT_SCI1_TEI 0x17C
251 0 : #define RA_ELC_EVENT_SCI1_ERI 0x17D
252 0 : #define RA_ELC_EVENT_SCI1_AM 0x17E
253 0 : #define RA_ELC_EVENT_SCI2_RXI 0x180
254 0 : #define RA_ELC_EVENT_SCI2_TXI 0x181
255 0 : #define RA_ELC_EVENT_SCI2_TEI 0x182
256 0 : #define RA_ELC_EVENT_SCI2_ERI 0x183
257 0 : #define RA_ELC_EVENT_SCI2_AM 0x184
258 0 : #define RA_ELC_EVENT_SCI3_RXI 0x186
259 0 : #define RA_ELC_EVENT_SCI3_TXI 0x187
260 0 : #define RA_ELC_EVENT_SCI3_TEI 0x188
261 0 : #define RA_ELC_EVENT_SCI3_ERI 0x189
262 0 : #define RA_ELC_EVENT_SCI3_AM 0x18A
263 0 : #define RA_ELC_EVENT_SCI4_RXI 0x18C
264 0 : #define RA_ELC_EVENT_SCI4_TXI 0x18D
265 0 : #define RA_ELC_EVENT_SCI4_TEI 0x18E
266 0 : #define RA_ELC_EVENT_SCI4_ERI 0x18F
267 0 : #define RA_ELC_EVENT_SCI4_AM 0x190
268 0 : #define RA_ELC_EVENT_SCI8_RXI 0x1A4
269 0 : #define RA_ELC_EVENT_SCI8_TXI 0x1A5
270 0 : #define RA_ELC_EVENT_SCI8_TEI 0x1A6
271 0 : #define RA_ELC_EVENT_SCI8_ERI 0x1A7
272 0 : #define RA_ELC_EVENT_SCI8_AM 0x1A8
273 0 : #define RA_ELC_EVENT_SCI9_RXI 0x1AA
274 0 : #define RA_ELC_EVENT_SCI9_TXI 0x1AB
275 0 : #define RA_ELC_EVENT_SCI9_TEI 0x1AC
276 0 : #define RA_ELC_EVENT_SCI9_ERI 0x1AD
277 0 : #define RA_ELC_EVENT_SCI9_AM 0x1AE
278 0 : #define RA_ELC_EVENT_SPI0_RXI 0x1BC
279 0 : #define RA_ELC_EVENT_SPI0_TXI 0x1BD
280 0 : #define RA_ELC_EVENT_SPI0_IDLE 0x1BE
281 0 : #define RA_ELC_EVENT_SPI0_ERI 0x1BF
282 0 : #define RA_ELC_EVENT_SPI0_TEI 0x1C0
283 0 : #define RA_ELC_EVENT_SPI1_RXI 0x1C1
284 0 : #define RA_ELC_EVENT_SPI1_TXI 0x1C2
285 0 : #define RA_ELC_EVENT_SPI1_IDLE 0x1C3
286 0 : #define RA_ELC_EVENT_SPI1_ERI 0x1C4
287 0 : #define RA_ELC_EVENT_SPI1_TEI 0x1C5
288 0 : #define RA_ELC_EVENT_QSPI_INT 0x1C6
289 0 : #define RA_ELC_EVENT_SDHIMMC0_ACCS 0x1C7
290 0 : #define RA_ELC_EVENT_SDHIMMC0_SDIO 0x1C8
291 0 : #define RA_ELC_EVENT_SDHIMMC0_CARD 0x1C9
292 0 : #define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x1CA
293 0 : #define RA_ELC_EVENT_SDHIMMC1_ACCS 0x1CB
294 0 : #define RA_ELC_EVENT_SDHIMMC1_SDIO 0x1CC
295 0 : #define RA_ELC_EVENT_SDHIMMC1_CARD 0x1CD
296 0 : #define RA_ELC_EVENT_SDHIMMC1_DMA_REQ 0x1CE
297 :
298 : /* Possible peripherals to be linked to event signals */
299 0 : #define RA_ELC_PERIPHERAL_GPT_A 0
300 0 : #define RA_ELC_PERIPHERAL_GPT_B 1
301 0 : #define RA_ELC_PERIPHERAL_GPT_C 2
302 0 : #define RA_ELC_PERIPHERAL_GPT_D 3
303 0 : #define RA_ELC_PERIPHERAL_GPT_E 4
304 0 : #define RA_ELC_PERIPHERAL_GPT_F 5
305 0 : #define RA_ELC_PERIPHERAL_GPT_G 6
306 0 : #define RA_ELC_PERIPHERAL_GPT_H 7
307 0 : #define RA_ELC_PERIPHERAL_ADC0 8
308 0 : #define RA_ELC_PERIPHERAL_ADC0_B 9
309 0 : #define RA_ELC_PERIPHERAL_ADC1 10
310 0 : #define RA_ELC_PERIPHERAL_ADC1_B 11
311 0 : #define RA_ELC_PERIPHERAL_DAC0 12
312 0 : #define RA_ELC_PERIPHERAL_DAC1 13
313 0 : #define RA_ELC_PERIPHERAL_IOPORT1 14
314 0 : #define RA_ELC_PERIPHERAL_IOPORT2 15
315 0 : #define RA_ELC_PERIPHERAL_IOPORT3 16
316 0 : #define RA_ELC_PERIPHERAL_IOPORT4 17
317 0 : #define RA_ELC_PERIPHERAL_CTSU 18
318 :
319 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M1_ELC_H_ */
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