Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8D1_ELC_H_
8 : #define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8D1_ELC_H_
9 :
10 : /* Sources of event signals to be linked to other peripherals or the CPU */
11 0 : #define RA_ELC_EVENT_NONE 0x0
12 0 : #define RA_ELC_EVENT_ICU_IRQ0 0x001
13 0 : #define RA_ELC_EVENT_ICU_IRQ1 0x002
14 0 : #define RA_ELC_EVENT_ICU_IRQ2 0x003
15 0 : #define RA_ELC_EVENT_ICU_IRQ3 0x004
16 0 : #define RA_ELC_EVENT_ICU_IRQ4 0x005
17 0 : #define RA_ELC_EVENT_ICU_IRQ5 0x006
18 0 : #define RA_ELC_EVENT_ICU_IRQ6 0x007
19 0 : #define RA_ELC_EVENT_ICU_IRQ7 0x008
20 0 : #define RA_ELC_EVENT_ICU_IRQ8 0x009
21 0 : #define RA_ELC_EVENT_ICU_IRQ9 0x00A
22 0 : #define RA_ELC_EVENT_ICU_IRQ10 0x00B
23 0 : #define RA_ELC_EVENT_ICU_IRQ11 0x00C
24 0 : #define RA_ELC_EVENT_ICU_IRQ12 0x00D
25 0 : #define RA_ELC_EVENT_ICU_IRQ13 0x00E
26 0 : #define RA_ELC_EVENT_ICU_IRQ14 0x00F
27 0 : #define RA_ELC_EVENT_ICU_IRQ15 0x010
28 0 : #define RA_ELC_EVENT_DMAC0_INT 0x011
29 0 : #define RA_ELC_EVENT_DMAC1_INT 0x012
30 0 : #define RA_ELC_EVENT_DMAC2_INT 0x013
31 0 : #define RA_ELC_EVENT_DMAC3_INT 0x014
32 0 : #define RA_ELC_EVENT_DMAC4_INT 0x015
33 0 : #define RA_ELC_EVENT_DMAC5_INT 0x016
34 0 : #define RA_ELC_EVENT_DMAC6_INT 0x017
35 0 : #define RA_ELC_EVENT_DMAC7_INT 0x018
36 0 : #define RA_ELC_EVENT_DTC_END 0x021
37 0 : #define RA_ELC_EVENT_DTC_COMPLETE 0x022
38 0 : #define RA_ELC_EVENT_DMA_TRANSERR 0x027
39 0 : #define RA_ELC_EVENT_DBG_CTIIRQ0 0x029
40 0 : #define RA_ELC_EVENT_DBG_CTIIRQ1 0x02A
41 0 : #define RA_ELC_EVENT_DBG_JBRXI 0x02B
42 0 : #define RA_ELC_EVENT_FCU_FIFERR 0x030
43 0 : #define RA_ELC_EVENT_FCU_FRDYI 0x031
44 0 : #define RA_ELC_EVENT_LVD_LVD1 0x038
45 0 : #define RA_ELC_EVENT_LVD_LVD2 0x039
46 0 : #define RA_ELC_EVENT_VBATT_TADI 0x03D
47 0 : #define RA_ELC_EVENT_CGC_MOSC_STOP 0x03E
48 0 : #define RA_ELC_EVENT_ULPT0_INT 0x040
49 0 : #define RA_ELC_EVENT_ULPT0_COMPARE_A 0x041
50 0 : #define RA_ELC_EVENT_ULPT0_COMPARE_B 0x042
51 0 : #define RA_ELC_EVENT_ULPT1_INT 0x043
52 0 : #define RA_ELC_EVENT_ULPT1_COMPARE_A 0x044
53 0 : #define RA_ELC_EVENT_ULPT1_COMPARE_B 0x045
54 0 : #define RA_ELC_EVENT_AGT0_INT 0x046
55 0 : #define RA_ELC_EVENT_AGT0_COMPARE_A 0x047
56 0 : #define RA_ELC_EVENT_AGT0_COMPARE_B 0x048
57 0 : #define RA_ELC_EVENT_AGT1_INT 0x049
58 0 : #define RA_ELC_EVENT_AGT1_COMPARE_A 0x04A
59 0 : #define RA_ELC_EVENT_AGT1_COMPARE_B 0x04B
60 0 : #define RA_ELC_EVENT_IWDT_UNDERFLOW 0x052
61 0 : #define RA_ELC_EVENT_WDT0_UNDERFLOW 0x053
62 0 : #define RA_ELC_EVENT_RTC_ALARM 0x055
63 0 : #define RA_ELC_EVENT_RTC_PERIOD 0x056
64 0 : #define RA_ELC_EVENT_RTC_CARRY 0x057
65 0 : #define RA_ELC_EVENT_USBFS_FIFO_0 0x058
66 0 : #define RA_ELC_EVENT_USBFS_FIFO_1 0x059
67 0 : #define RA_ELC_EVENT_USBFS_INT 0x05A
68 0 : #define RA_ELC_EVENT_USBFS_RESUME 0x05B
69 0 : #define RA_ELC_EVENT_IIC0_RXI 0x05C
70 0 : #define RA_ELC_EVENT_IIC0_TXI 0x05D
71 0 : #define RA_ELC_EVENT_IIC0_TEI 0x05E
72 0 : #define RA_ELC_EVENT_IIC0_ERI 0x05F
73 0 : #define RA_ELC_EVENT_IIC0_WUI 0x060
74 0 : #define RA_ELC_EVENT_IIC1_RXI 0x061
75 0 : #define RA_ELC_EVENT_IIC1_TXI 0x062
76 0 : #define RA_ELC_EVENT_IIC1_TEI 0x063
77 0 : #define RA_ELC_EVENT_IIC1_ERI 0x064
78 0 : #define RA_ELC_EVENT_SDHIMMC0_ACCS 0x06B
79 0 : #define RA_ELC_EVENT_SDHIMMC0_SDIO 0x06C
80 0 : #define RA_ELC_EVENT_SDHIMMC0_CARD 0x06D
81 0 : #define RA_ELC_EVENT_SDHIMMC0_DMA_REQ 0x06E
82 0 : #define RA_ELC_EVENT_SDHIMMC1_ACCS 0x06F
83 0 : #define RA_ELC_EVENT_SDHIMMC1_SDIO 0x070
84 0 : #define RA_ELC_EVENT_SDHIMMC1_CARD 0x071
85 0 : #define RA_ELC_EVENT_SDHIMMC1_DMA_REQ 0x072
86 0 : #define RA_ELC_EVENT_SSI0_TXI 0x073
87 0 : #define RA_ELC_EVENT_SSI0_RXI 0x074
88 0 : #define RA_ELC_EVENT_SSI0_INT 0x076
89 0 : #define RA_ELC_EVENT_SSI1_TXI_RXI 0x079
90 0 : #define RA_ELC_EVENT_SSI1_TXI 0x079
91 0 : #define RA_ELC_EVENT_SSI1_RXI 0x079
92 0 : #define RA_ELC_EVENT_SSI1_INT 0x07A
93 0 : #define RA_ELC_EVENT_ACMPHS0_INT 0x07B
94 0 : #define RA_ELC_EVENT_ACMPHS1_INT 0x07C
95 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_0 0x083
96 0 : #define RA_ELC_EVENT_ELC_SOFTWARE_EVENT_1 0x084
97 0 : #define RA_ELC_EVENT_IOPORT_EVENT_1 0x088
98 0 : #define RA_ELC_EVENT_IOPORT_EVENT_2 0x089
99 0 : #define RA_ELC_EVENT_IOPORT_EVENT_3 0x08A
100 0 : #define RA_ELC_EVENT_IOPORT_EVENT_4 0x08B
101 0 : #define RA_ELC_EVENT_CAC_FREQUENCY_ERROR 0x08C
102 0 : #define RA_ELC_EVENT_CAC_MEASUREMENT_END 0x08D
103 0 : #define RA_ELC_EVENT_CAC_OVERFLOW 0x08E
104 0 : #define RA_ELC_EVENT_POEG0_EVENT 0x08F
105 0 : #define RA_ELC_EVENT_POEG1_EVENT 0x090
106 0 : #define RA_ELC_EVENT_POEG2_EVENT 0x091
107 0 : #define RA_ELC_EVENT_POEG3_EVENT 0x092
108 0 : #define RA_ELC_EVENT_OPS_UVW_EDGE 0x0A0
109 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_A 0x0A1
110 0 : #define RA_ELC_EVENT_GPT0_CAPTURE_COMPARE_B 0x0A2
111 0 : #define RA_ELC_EVENT_GPT0_COMPARE_C 0x0A3
112 0 : #define RA_ELC_EVENT_GPT0_COMPARE_D 0x0A4
113 0 : #define RA_ELC_EVENT_GPT0_COMPARE_E 0x0A5
114 0 : #define RA_ELC_EVENT_GPT0_COMPARE_F 0x0A6
115 0 : #define RA_ELC_EVENT_GPT0_COUNTER_OVERFLOW 0x0A7
116 0 : #define RA_ELC_EVENT_GPT0_COUNTER_UNDERFLOW 0x0A8
117 0 : #define RA_ELC_EVENT_GPT0_PC 0x0A9
118 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_A 0x0AA
119 0 : #define RA_ELC_EVENT_GPT1_CAPTURE_COMPARE_B 0x0AB
120 0 : #define RA_ELC_EVENT_GPT1_COMPARE_C 0x0AC
121 0 : #define RA_ELC_EVENT_GPT1_COMPARE_D 0x0AD
122 0 : #define RA_ELC_EVENT_GPT1_COMPARE_E 0x0AE
123 0 : #define RA_ELC_EVENT_GPT1_COMPARE_F 0x0AF
124 0 : #define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0B0
125 0 : #define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0B1
126 0 : #define RA_ELC_EVENT_GPT1_PC 0x0B2
127 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_A 0x0B3
128 0 : #define RA_ELC_EVENT_GPT2_CAPTURE_COMPARE_B 0x0B4
129 0 : #define RA_ELC_EVENT_GPT2_COMPARE_C 0x0B5
130 0 : #define RA_ELC_EVENT_GPT2_COMPARE_D 0x0B6
131 0 : #define RA_ELC_EVENT_GPT2_COMPARE_E 0x0B7
132 0 : #define RA_ELC_EVENT_GPT2_COMPARE_F 0x0B8
133 0 : #define RA_ELC_EVENT_GPT2_COUNTER_OVERFLOW 0x0B9
134 0 : #define RA_ELC_EVENT_GPT2_COUNTER_UNDERFLOW 0x0BA
135 0 : #define RA_ELC_EVENT_GPT2_PC 0x0BB
136 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_A 0x0BC
137 0 : #define RA_ELC_EVENT_GPT3_CAPTURE_COMPARE_B 0x0BD
138 0 : #define RA_ELC_EVENT_GPT3_COMPARE_C 0x0BE
139 0 : #define RA_ELC_EVENT_GPT3_COMPARE_D 0x0BF
140 0 : #define RA_ELC_EVENT_GPT3_COMPARE_E 0x0C0
141 0 : #define RA_ELC_EVENT_GPT3_COMPARE_F 0x0C1
142 0 : #define RA_ELC_EVENT_GPT3_COUNTER_OVERFLOW 0x0C2
143 0 : #define RA_ELC_EVENT_GPT3_COUNTER_UNDERFLOW 0x0C3
144 0 : #define RA_ELC_EVENT_GPT3_PC 0x0C4
145 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_A 0x0C5
146 0 : #define RA_ELC_EVENT_GPT4_CAPTURE_COMPARE_B 0x0C6
147 0 : #define RA_ELC_EVENT_GPT4_COMPARE_C 0x0C7
148 0 : #define RA_ELC_EVENT_GPT4_COMPARE_D 0x0C8
149 0 : #define RA_ELC_EVENT_GPT4_COMPARE_E 0x0C9
150 0 : #define RA_ELC_EVENT_GPT4_COMPARE_F 0x0CA
151 0 : #define RA_ELC_EVENT_GPT4_COUNTER_OVERFLOW 0x0CB
152 0 : #define RA_ELC_EVENT_GPT4_COUNTER_UNDERFLOW 0x0CC
153 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_A 0x0CE
154 0 : #define RA_ELC_EVENT_GPT5_CAPTURE_COMPARE_B 0x0CF
155 0 : #define RA_ELC_EVENT_GPT5_COMPARE_C 0x0D0
156 0 : #define RA_ELC_EVENT_GPT5_COMPARE_D 0x0D1
157 0 : #define RA_ELC_EVENT_GPT5_COMPARE_E 0x0D2
158 0 : #define RA_ELC_EVENT_GPT5_COMPARE_F 0x0D3
159 0 : #define RA_ELC_EVENT_GPT5_COUNTER_OVERFLOW 0x0D4
160 0 : #define RA_ELC_EVENT_GPT5_COUNTER_UNDERFLOW 0x0D5
161 0 : #define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_A 0x0D7
162 0 : #define RA_ELC_EVENT_GPT6_CAPTURE_COMPARE_B 0x0D8
163 0 : #define RA_ELC_EVENT_GPT6_COMPARE_C 0x0D9
164 0 : #define RA_ELC_EVENT_GPT6_COMPARE_D 0x0DA
165 0 : #define RA_ELC_EVENT_GPT6_COMPARE_E 0x0DB
166 0 : #define RA_ELC_EVENT_GPT6_COMPARE_F 0x0DC
167 0 : #define RA_ELC_EVENT_GPT6_COUNTER_OVERFLOW 0x0DD
168 0 : #define RA_ELC_EVENT_GPT6_COUNTER_UNDERFLOW 0x0DE
169 0 : #define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_A 0x0E0
170 0 : #define RA_ELC_EVENT_GPT7_CAPTURE_COMPARE_B 0x0E1
171 0 : #define RA_ELC_EVENT_GPT7_COMPARE_C 0x0E2
172 0 : #define RA_ELC_EVENT_GPT7_COMPARE_D 0x0E3
173 0 : #define RA_ELC_EVENT_GPT7_COMPARE_E 0x0E4
174 0 : #define RA_ELC_EVENT_GPT7_COMPARE_F 0x0E5
175 0 : #define RA_ELC_EVENT_GPT7_COUNTER_OVERFLOW 0x0E6
176 0 : #define RA_ELC_EVENT_GPT7_COUNTER_UNDERFLOW 0x0E7
177 0 : #define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_A 0x0E9
178 0 : #define RA_ELC_EVENT_GPT8_CAPTURE_COMPARE_B 0x0EA
179 0 : #define RA_ELC_EVENT_GPT8_COMPARE_C 0x0EB
180 0 : #define RA_ELC_EVENT_GPT8_COMPARE_D 0x0EC
181 0 : #define RA_ELC_EVENT_GPT8_COMPARE_E 0x0ED
182 0 : #define RA_ELC_EVENT_GPT8_COMPARE_F 0x0EE
183 0 : #define RA_ELC_EVENT_GPT8_COUNTER_OVERFLOW 0x0EF
184 0 : #define RA_ELC_EVENT_GPT8_COUNTER_UNDERFLOW 0x0F0
185 0 : #define RA_ELC_EVENT_GPT8_PC 0x0F1
186 0 : #define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_A 0x0F2
187 0 : #define RA_ELC_EVENT_GPT9_CAPTURE_COMPARE_B 0x0F3
188 0 : #define RA_ELC_EVENT_GPT9_COMPARE_C 0x0F4
189 0 : #define RA_ELC_EVENT_GPT9_COMPARE_D 0x0F5
190 0 : #define RA_ELC_EVENT_GPT9_COMPARE_E 0x0F6
191 0 : #define RA_ELC_EVENT_GPT9_COMPARE_F 0x0F7
192 0 : #define RA_ELC_EVENT_GPT9_COUNTER_OVERFLOW 0x0F8
193 0 : #define RA_ELC_EVENT_GPT9_COUNTER_UNDERFLOW 0x0F9
194 0 : #define RA_ELC_EVENT_GPT9_PC 0x0FA
195 0 : #define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_A 0x0FB
196 0 : #define RA_ELC_EVENT_GPT10_CAPTURE_COMPARE_B 0x0FC
197 0 : #define RA_ELC_EVENT_GPT10_COMPARE_C 0x0FD
198 0 : #define RA_ELC_EVENT_GPT10_COMPARE_D 0x0FE
199 0 : #define RA_ELC_EVENT_GPT10_COMPARE_E 0x0FF
200 0 : #define RA_ELC_EVENT_GPT10_COMPARE_F 0x100
201 0 : #define RA_ELC_EVENT_GPT10_COUNTER_OVERFLOW 0x101
202 0 : #define RA_ELC_EVENT_GPT10_COUNTER_UNDERFLOW 0x102
203 0 : #define RA_ELC_EVENT_GPT10_PC 0x103
204 0 : #define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_A 0x104
205 0 : #define RA_ELC_EVENT_GPT11_CAPTURE_COMPARE_B 0x105
206 0 : #define RA_ELC_EVENT_GPT11_COMPARE_C 0x106
207 0 : #define RA_ELC_EVENT_GPT11_COMPARE_D 0x107
208 0 : #define RA_ELC_EVENT_GPT11_COMPARE_E 0x108
209 0 : #define RA_ELC_EVENT_GPT11_COMPARE_F 0x109
210 0 : #define RA_ELC_EVENT_GPT11_COUNTER_OVERFLOW 0x10A
211 0 : #define RA_ELC_EVENT_GPT11_COUNTER_UNDERFLOW 0x10B
212 0 : #define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_A 0x10D
213 0 : #define RA_ELC_EVENT_GPT12_CAPTURE_COMPARE_B 0x10E
214 0 : #define RA_ELC_EVENT_GPT12_COMPARE_C 0x10F
215 0 : #define RA_ELC_EVENT_GPT12_COMPARE_D 0x110
216 0 : #define RA_ELC_EVENT_GPT12_COMPARE_E 0x111
217 0 : #define RA_ELC_EVENT_GPT12_COMPARE_F 0x112
218 0 : #define RA_ELC_EVENT_GPT12_COUNTER_OVERFLOW 0x113
219 0 : #define RA_ELC_EVENT_GPT12_COUNTER_UNDERFLOW 0x114
220 0 : #define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_A 0x116
221 0 : #define RA_ELC_EVENT_GPT13_CAPTURE_COMPARE_B 0x117
222 0 : #define RA_ELC_EVENT_GPT13_COMPARE_C 0x118
223 0 : #define RA_ELC_EVENT_GPT13_COMPARE_D 0x119
224 0 : #define RA_ELC_EVENT_GPT13_COMPARE_E 0x11A
225 0 : #define RA_ELC_EVENT_GPT13_COMPARE_F 0x11B
226 0 : #define RA_ELC_EVENT_GPT13_COUNTER_OVERFLOW 0x11C
227 0 : #define RA_ELC_EVENT_GPT13_COUNTER_UNDERFLOW 0x11D
228 0 : #define RA_ELC_EVENT_EDMAC0_EINT 0x120
229 0 : #define RA_ELC_EVENT_USBHS_FIFO_0 0x121
230 0 : #define RA_ELC_EVENT_USBHS_FIFO_1 0x122
231 0 : #define RA_ELC_EVENT_USBHS_USB_INT_RESUME 0x123
232 0 : #define RA_ELC_EVENT_SCI0_RXI 0x124
233 0 : #define RA_ELC_EVENT_SCI0_TXI 0x125
234 0 : #define RA_ELC_EVENT_SCI0_TEI 0x126
235 0 : #define RA_ELC_EVENT_SCI0_ERI 0x127
236 0 : #define RA_ELC_EVENT_SCI0_AED 0x128
237 0 : #define RA_ELC_EVENT_SCI0_BFD 0x129
238 0 : #define RA_ELC_EVENT_SCI0_AM 0x12A
239 0 : #define RA_ELC_EVENT_SCI1_RXI 0x12B
240 0 : #define RA_ELC_EVENT_SCI1_TXI 0x12C
241 0 : #define RA_ELC_EVENT_SCI1_TEI 0x12D
242 0 : #define RA_ELC_EVENT_SCI1_ERI 0x12E
243 0 : #define RA_ELC_EVENT_SCI1_AED 0x12F
244 0 : #define RA_ELC_EVENT_SCI1_BFD 0x130
245 0 : #define RA_ELC_EVENT_SCI1_AM 0x131
246 0 : #define RA_ELC_EVENT_SCI2_RXI 0x132
247 0 : #define RA_ELC_EVENT_SCI2_TXI 0x133
248 0 : #define RA_ELC_EVENT_SCI2_TEI 0x134
249 0 : #define RA_ELC_EVENT_SCI2_ERI 0x135
250 0 : #define RA_ELC_EVENT_SCI2_AM 0x138
251 0 : #define RA_ELC_EVENT_SCI3_RXI 0x139
252 0 : #define RA_ELC_EVENT_SCI3_TXI 0x13A
253 0 : #define RA_ELC_EVENT_SCI3_TEI 0x13B
254 0 : #define RA_ELC_EVENT_SCI3_ERI 0x13C
255 0 : #define RA_ELC_EVENT_SCI3_AM 0x13F
256 0 : #define RA_ELC_EVENT_SCI4_RXI 0x140
257 0 : #define RA_ELC_EVENT_SCI4_TXI 0x141
258 0 : #define RA_ELC_EVENT_SCI4_TEI 0x142
259 0 : #define RA_ELC_EVENT_SCI4_ERI 0x143
260 0 : #define RA_ELC_EVENT_SCI4_AM 0x146
261 0 : #define RA_ELC_EVENT_SCI9_RXI 0x163
262 0 : #define RA_ELC_EVENT_SCI9_TXI 0x164
263 0 : #define RA_ELC_EVENT_SCI9_TEI 0x165
264 0 : #define RA_ELC_EVENT_SCI9_ERI 0x166
265 0 : #define RA_ELC_EVENT_SCI9_AM 0x169
266 0 : #define RA_ELC_EVENT_SPI0_RXI 0x178
267 0 : #define RA_ELC_EVENT_SPI0_TXI 0x179
268 0 : #define RA_ELC_EVENT_SPI0_IDLE 0x17A
269 0 : #define RA_ELC_EVENT_SPI0_ERI 0x17B
270 0 : #define RA_ELC_EVENT_SPI0_TEI 0x17C
271 0 : #define RA_ELC_EVENT_SPI1_RXI 0x17D
272 0 : #define RA_ELC_EVENT_SPI1_TXI 0x17E
273 0 : #define RA_ELC_EVENT_SPI1_IDLE 0x17F
274 0 : #define RA_ELC_EVENT_SPI1_ERI 0x180
275 0 : #define RA_ELC_EVENT_SPI1_TEI 0x181
276 0 : #define RA_ELC_EVENT_XSPI_ERR 0x182
277 0 : #define RA_ELC_EVENT_XSPI_CMP 0x183
278 0 : #define RA_ELC_EVENT_CAN_RXF 0x185
279 0 : #define RA_ELC_EVENT_CAN_GLERR 0x186
280 0 : #define RA_ELC_EVENT_CAN0_DMAREQ0 0x187
281 0 : #define RA_ELC_EVENT_CAN0_DMAREQ1 0x188
282 0 : #define RA_ELC_EVENT_CAN1_DMAREQ0 0x18B
283 0 : #define RA_ELC_EVENT_CAN1_DMAREQ1 0x18C
284 0 : #define RA_ELC_EVENT_CAN0_TX 0x18F
285 0 : #define RA_ELC_EVENT_CAN0_CHERR 0x190
286 0 : #define RA_ELC_EVENT_CAN0_COMFRX 0x191
287 0 : #define RA_ELC_EVENT_CAN0_CF_DMAREQ 0x192
288 0 : #define RA_ELC_EVENT_CAN0_RXMB 0x193
289 0 : #define RA_ELC_EVENT_CAN1_TX 0x194
290 0 : #define RA_ELC_EVENT_CAN1_CHERR 0x195
291 0 : #define RA_ELC_EVENT_CAN1_COMFRX 0x196
292 0 : #define RA_ELC_EVENT_CAN1_CF_DMAREQ 0x197
293 0 : #define RA_ELC_EVENT_CAN1_RXMB 0x198
294 0 : #define RA_ELC_EVENT_CAN0_MRAM_ERI 0x19B
295 0 : #define RA_ELC_EVENT_CAN1_MRAM_ERI 0x19C
296 0 : #define RA_ELC_EVENT_I3C0_RESPONSE 0x19D
297 0 : #define RA_ELC_EVENT_I3C0_COMMAND 0x19E
298 0 : #define RA_ELC_EVENT_I3C0_IBI 0x19F
299 0 : #define RA_ELC_EVENT_I3C0_RX 0x1A0
300 0 : #define RA_ELC_EVENT_IICB0_RXI 0x1A0
301 0 : #define RA_ELC_EVENT_I3C0_TX 0x1A1
302 0 : #define RA_ELC_EVENT_IICB0_TXI 0x1A1
303 0 : #define RA_ELC_EVENT_I3C0_RCV_STATUS 0x1A2
304 0 : #define RA_ELC_EVENT_I3C0_HRESP 0x1A3
305 0 : #define RA_ELC_EVENT_I3C0_HCMD 0x1A4
306 0 : #define RA_ELC_EVENT_I3C0_HRX 0x1A5
307 0 : #define RA_ELC_EVENT_I3C0_HTX 0x1A6
308 0 : #define RA_ELC_EVENT_I3C0_TEND 0x1A7
309 0 : #define RA_ELC_EVENT_IICB0_TEI 0x1A7
310 0 : #define RA_ELC_EVENT_I3C0_EEI 0x1A8
311 0 : #define RA_ELC_EVENT_IICB0_ERI 0x1A8
312 0 : #define RA_ELC_EVENT_I3C0_STEV 0x1A9
313 0 : #define RA_ELC_EVENT_I3C0_MREFOVF 0x1AA
314 0 : #define RA_ELC_EVENT_I3C0_MREFCPT 0x1AB
315 0 : #define RA_ELC_EVENT_I3C0_AMEV 0x1AC
316 0 : #define RA_ELC_EVENT_I3C0_WU 0x1AD
317 0 : #define RA_ELC_EVENT_ADC0_SCAN_END 0x1AE
318 0 : #define RA_ELC_EVENT_ADC0_SCAN_END_B 0x1AF
319 0 : #define RA_ELC_EVENT_ADC0_WINDOW_A 0x1B0
320 0 : #define RA_ELC_EVENT_ADC0_WINDOW_B 0x1B1
321 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MATCH 0x1B2
322 0 : #define RA_ELC_EVENT_ADC0_COMPARE_MISMATCH 0x1B3
323 0 : #define RA_ELC_EVENT_ADC1_SCAN_END 0x1B4
324 0 : #define RA_ELC_EVENT_ADC1_SCAN_END_B 0x1B5
325 0 : #define RA_ELC_EVENT_ADC1_WINDOW_A 0x1B6
326 0 : #define RA_ELC_EVENT_ADC1_WINDOW_B 0x1B7
327 0 : #define RA_ELC_EVENT_ADC1_COMPARE_MATCH 0x1B8
328 0 : #define RA_ELC_EVENT_ADC1_COMPARE_MISMATCH 0x1B9
329 0 : #define RA_ELC_EVENT_DOC_INT 0x1BA
330 0 : #define RA_ELC_EVENT_RSIP_TADI 0x1BC
331 0 : #define RA_ELC_EVENT_GLCDC_LINE_DETECT 0x1CD
332 0 : #define RA_ELC_EVENT_GLCDC_UNDERFLOW_1 0x1CE
333 0 : #define RA_ELC_EVENT_GLCDC_UNDERFLOW_2 0x1CF
334 0 : #define RA_ELC_EVENT_DRW_INT 0x1D0
335 0 : #define RA_ELC_EVENT_MIPIDSI_SEQ0 0x1D3
336 0 : #define RA_ELC_EVENT_MIPIDSI_SEQ1 0x1D4
337 0 : #define RA_ELC_EVENT_MIPIDSI_VIN1 0x1D5
338 0 : #define RA_ELC_EVENT_MIPIDSI_RCV 0x1D6
339 0 : #define RA_ELC_EVENT_MIPIDSI_FERR 0x1D7
340 0 : #define RA_ELC_EVENT_MIPIDSI_PPI 0x1D8
341 0 : #define RA_ELC_EVENT_CEU_CEUI 0x1DA
342 :
343 : /* Possible peripherals to be linked to event signals */
344 0 : #define RA_ELC_PERIPHERAL_GPT_A 0
345 0 : #define RA_ELC_PERIPHERAL_GPT_B 1
346 0 : #define RA_ELC_PERIPHERAL_GPT_C 2
347 0 : #define RA_ELC_PERIPHERAL_GPT_D 3
348 0 : #define RA_ELC_PERIPHERAL_GPT_E 4
349 0 : #define RA_ELC_PERIPHERAL_GPT_F 5
350 0 : #define RA_ELC_PERIPHERAL_GPT_G 6
351 0 : #define RA_ELC_PERIPHERAL_GPT_H 7
352 0 : #define RA_ELC_PERIPHERAL_ADC0 8
353 0 : #define RA_ELC_PERIPHERAL_ADC0_B 9
354 0 : #define RA_ELC_PERIPHERAL_ADC1 10
355 0 : #define RA_ELC_PERIPHERAL_ADC1_B 11
356 0 : #define RA_ELC_PERIPHERAL_DAC0 12
357 0 : #define RA_ELC_PERIPHERAL_DAC1 13
358 0 : #define RA_ELC_PERIPHERAL_IOPORT1 14
359 0 : #define RA_ELC_PERIPHERAL_IOPORT2 15
360 0 : #define RA_ELC_PERIPHERAL_IOPORT3 16
361 0 : #define RA_ELC_PERIPHERAL_IOPORT4 17
362 0 : #define RA_ELC_PERIPHERAL_I3C 30
363 :
364 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8D1_ELC_H_ */
|
