LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/pinctrl - ch32v003-pinctrl.h Coverage Total Hit
Test: new.info Lines: 0.0 % 116 0
Test Date: 2025-09-05 16:43:28

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2024 Michael Hope
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CH32V003_PINCTRL_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CH32V003_PINCTRL_H_
       9              : 
      10            0 : #define CH32V003_PINMUX_PORT_PA 0
      11            0 : #define CH32V003_PINMUX_PORT_PC 1
      12            0 : #define CH32V003_PINMUX_PORT_PD 2
      13              : 
      14              : /*
      15              :  * Defines the starting bit for the remap field. Note that the I2C1 and USART1 fields are not
      16              :  * contigious.
      17              :  */
      18            0 : #define CH32V003_PINMUX_SPI1_RM    0
      19            0 : #define CH32V003_PINMUX_I2C1_RM    1
      20            0 : #define CH32V003_PINMUX_I2C1_RM1   22
      21            0 : #define CH32V003_PINMUX_USART1_RM  2
      22            0 : #define CH32V003_PINMUX_USART1_RM1 21
      23            0 : #define CH32V003_PINMUX_TIM1_RM    6
      24            0 : #define CH32V003_PINMUX_TIM1_RM1   23
      25            0 : #define CH32V003_PINMUX_TIM2_RM    8
      26              : /*
      27              :  * ADC1 is not remappable but re-uses the remap field to encode that the pin needs to use
      28              :  * analog input mode.
      29              :  */
      30            0 : #define CH32V003_PINMUX_ADC1_RM    3
      31              : 
      32              : /* Port number with 0-2 */
      33            0 : #define CH32V003_PINCTRL_PORT_SHIFT    0
      34              : /* Pin number 0-15 */
      35            0 : #define CH32V003_PINCTRL_PIN_SHIFT     2
      36              : /* Base remap bit 0-31 */
      37            0 : #define CH32V003_PINCTRL_RM_BASE_SHIFT 6
      38              : /* Function remapping ID 0-3 */
      39            0 : #define CH32V003_PINCTRL_RM_SHIFT      11
      40              : 
      41            0 : #define CH32V003_PINMUX_DEFINE(port, pin, rm, remapping)                                           \
      42              :         ((CH32V003_PINMUX_PORT_##port << CH32V003_PINCTRL_PORT_SHIFT) |                            \
      43              :          (pin << CH32V003_PINCTRL_PIN_SHIFT) |                                                     \
      44              :          (CH32V003_PINMUX_##rm##_RM << CH32V003_PINCTRL_RM_BASE_SHIFT) |                           \
      45              :          (remapping << CH32V003_PINCTRL_RM_SHIFT))
      46              : 
      47            0 : #define TIM1_ETR_PC5_0  CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 0)
      48            0 : #define TIM1_ETR_PC5_1  CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 1)
      49            0 : #define TIM1_ETR_PD4_2  CH32V003_PINMUX_DEFINE(PD, 4, TIM1, 2)
      50            0 : #define TIM1_ETR_PC2_3  CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 3)
      51            0 : #define TIM1_CH1_PD2_0  CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 0)
      52            0 : #define TIM1_CH1_PC6_1  CH32V003_PINMUX_DEFINE(PC, 6, TIM1, 1)
      53            0 : #define TIM1_CH1_PD2_2  CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 2)
      54            0 : #define TIM1_CH1_PC4_3  CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 3)
      55            0 : #define TIM1_CH2_PA1_0  CH32V003_PINMUX_DEFINE(PA, 1, TIM1, 0)
      56            0 : #define TIM1_CH2_PC7_1  CH32V003_PINMUX_DEFINE(PC, 7, TIM1, 1)
      57            0 : #define TIM1_CH2_PA1_2  CH32V003_PINMUX_DEFINE(PA, 1, TIM1, 2)
      58            0 : #define TIM1_CH2_PC7_3  CH32V003_PINMUX_DEFINE(PC, 7, TIM1, 3)
      59            0 : #define TIM1_CH3_PC3_0  CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 0)
      60            0 : #define TIM1_CH3_PC0_1  CH32V003_PINMUX_DEFINE(PC, 0, TIM1, 1)
      61            0 : #define TIM1_CH3_PC3_2  CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 2)
      62            0 : #define TIM1_CH3_PC5_3  CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 3)
      63            0 : #define TIM1_CH4_PC4_0  CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 0)
      64            0 : #define TIM1_CH4_PD3_1  CH32V003_PINMUX_DEFINE(PD, 3, TIM1, 1)
      65            0 : #define TIM1_CH4_PC4_2  CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 2)
      66            0 : #define TIM1_CH4_PD4_3  CH32V003_PINMUX_DEFINE(PD, 4, TIM1, 3)
      67            0 : #define TIM1_BKIN_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 0)
      68            0 : #define TIM1_BKIN_PC1_1 CH32V003_PINMUX_DEFINE(PC, 1, TIM1, 1)
      69            0 : #define TIM1_BKIN_PC2_2 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 2)
      70            0 : #define TIM1_BKIN_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM1, 3)
      71            0 : #define TIM1_CH1N_PD0_0 CH32V003_PINMUX_DEFINE(PD, 0, TIM1, 0)
      72            0 : #define TIM1_CH1N_PC3_1 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 1)
      73            0 : #define TIM1_CH1N_PD0_2 CH32V003_PINMUX_DEFINE(PD, 0, TIM1, 2)
      74            0 : #define TIM1_CH1N_PC3_3 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 3)
      75            0 : #define TIM1_CH2N_PA2_0 CH32V003_PINMUX_DEFINE(PA, 2, TIM1, 0)
      76            0 : #define TIM1_CH2N_PC4_1 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 1)
      77            0 : #define TIM1_CH2N_PA2_2 CH32V003_PINMUX_DEFINE(PA, 2, TIM1, 2)
      78            0 : #define TIM1_CH2N_PD2_3 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 3)
      79            0 : #define TIM1_CH3N_PD1_0 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 0)
      80            0 : #define TIM1_CH3N_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 1)
      81            0 : #define TIM1_CH3N_PD1_2 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 2)
      82            0 : #define TIM1_CH3N_PC6_3 CH32V003_PINMUX_DEFINE(PC, 6, TIM1, 3)
      83              : 
      84            0 : #define TIM2_ETR_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, TIM2, 0)
      85            0 : #define TIM2_ETR_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM2, 1)
      86            0 : #define TIM2_ETR_PC1_2 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 2)
      87            0 : #define TIM2_ETR_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 3)
      88            0 : #define TIM2_CH1_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, TIM2, 0)
      89            0 : #define TIM2_CH1_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM2, 1)
      90            0 : #define TIM2_CH1_PC1_2 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 2)
      91            0 : #define TIM2_CH1_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 3)
      92            0 : #define TIM2_CH2_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, TIM2, 0)
      93            0 : #define TIM2_CH2_PC2_1 CH32V003_PINMUX_DEFINE(PC, 2, TIM2, 1)
      94            0 : #define TIM2_CH2_PD3_2 CH32V003_PINMUX_DEFINE(PD, 3, TIM2, 2)
      95            0 : #define TIM2_CH2_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, TIM2, 3)
      96            0 : #define TIM2_CH3_PC0_0 CH32V003_PINMUX_DEFINE(PC, 0, TIM2, 0)
      97            0 : #define TIM2_CH3_PD2_1 CH32V003_PINMUX_DEFINE(PD, 2, TIM2, 1)
      98            0 : #define TIM2_CH3_PC0_2 CH32V003_PINMUX_DEFINE(PC, 0, TIM2, 2)
      99            0 : #define TIM2_CH3_PD6_3 CH32V003_PINMUX_DEFINE(PD, 6, TIM2, 3)
     100            0 : #define TIM2_CH4_PD7_0 CH32V003_PINMUX_DEFINE(PD, 7, TIM2, 0)
     101            0 : #define TIM2_CH4_PC1_1 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 1)
     102            0 : #define TIM2_CH4_PD7_2 CH32V003_PINMUX_DEFINE(PD, 7, TIM2, 2)
     103            0 : #define TIM2_CH4_PD5_3 CH32V003_PINMUX_DEFINE(PD, 5, TIM2, 3)
     104              : 
     105            0 : #define USART1_CK_PD4_0  CH32V003_PINMUX_DEFINE(PD, 4, USART1, 0)
     106            0 : #define USART1_CK_PD7_1  CH32V003_PINMUX_DEFINE(PD, 7, USART1, 1)
     107            0 : #define USART1_CK_PD7_2  CH32V003_PINMUX_DEFINE(PD, 7, USART1, 2)
     108            0 : #define USART1_CK_PC5_3  CH32V003_PINMUX_DEFINE(PC, 5, USART1, 3)
     109            0 : #define USART1_TX_PD5_0  CH32V003_PINMUX_DEFINE(PD, 5, USART1, 0)
     110            0 : #define USART1_TX_PD0_1  CH32V003_PINMUX_DEFINE(PD, 0, USART1, 1)
     111            0 : #define USART1_TX_PD6_2  CH32V003_PINMUX_DEFINE(PD, 6, USART1, 2)
     112            0 : #define USART1_TX_PC0_3  CH32V003_PINMUX_DEFINE(PC, 0, USART1, 3)
     113            0 : #define USART1_RX_PD6_0  CH32V003_PINMUX_DEFINE(PD, 6, USART1, 0)
     114            0 : #define USART1_RX_PD1_1  CH32V003_PINMUX_DEFINE(PD, 1, USART1, 1)
     115            0 : #define USART1_RX_PD5_2  CH32V003_PINMUX_DEFINE(PD, 5, USART1, 2)
     116            0 : #define USART1_RX_PC1_3  CH32V003_PINMUX_DEFINE(PC, 1, USART1, 3)
     117            0 : #define USART1_CTS_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, USART1, 0)
     118            0 : #define USART1_CTS_PC3_1 CH32V003_PINMUX_DEFINE(PC, 3, USART1, 1)
     119            0 : #define USART1_CTS_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, USART1, 2)
     120            0 : #define USART1_CTS_PC6_3 CH32V003_PINMUX_DEFINE(PC, 6, USART1, 3)
     121            0 : #define USART1_RTS_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, USART1, 0)
     122            0 : #define USART1_RTS_PC2_1 CH32V003_PINMUX_DEFINE(PC, 2, USART1, 1)
     123            0 : #define USART1_RTS_PC7_2 CH32V003_PINMUX_DEFINE(PC, 7, USART1, 2)
     124            0 : #define USART1_RTS_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, USART1, 3)
     125              : 
     126            0 : #define SPI1_NSS_PC1_0  CH32V003_PINMUX_DEFINE(PC, 1, SPI1, 0)
     127            0 : #define SPI1_NSS_PC0_1  CH32V003_PINMUX_DEFINE(PC, 0, SPI1, 1)
     128            0 : #define SPI1_SCK_PC5_0  CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 0)
     129            0 : #define SPI1_SCK_PC5_1  CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 1)
     130            0 : #define SPI1_MISO_PC7_0 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 0)
     131            0 : #define SPI1_MISO_PC7_1 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 1)
     132            0 : #define SPI1_MOSI_PC6_0 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 0)
     133            0 : #define SPI1_MOSI_PC6_1 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 1)
     134              : 
     135            0 : #define I2C1_SCL_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, I2C1, 0)
     136            0 : #define I2C1_SCL_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, I2C1, 1)
     137            0 : #define I2C1_SCL_PC5_2 CH32V003_PINMUX_DEFINE(PC, 5, I2C1, 2)
     138            0 : #define I2C1_SDA_PC1_0 CH32V003_PINMUX_DEFINE(PC, 1, I2C1, 0)
     139            0 : #define I2C1_SDA_PD0_1 CH32V003_PINMUX_DEFINE(PD, 0, I2C1, 1)
     140            0 : #define I2C1_SDA_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, I2C1, 2)
     141              : 
     142            0 : #define ADC1_A0_PA2_0 CH32V003_PINMUX_DEFINE(PA, 2, ADC1, 0)
     143            0 : #define ADC1_A1_PA1_0 CH32V003_PINMUX_DEFINE(PA, 1, ADC1, 0)
     144            0 : #define ADC1_A2_PC4_0 CH32V003_PINMUX_DEFINE(PC, 4, ADC1, 0)
     145            0 : #define ADC1_A4_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, ADC1, 0)
     146            0 : #define ADC1_A3_PD2_0 CH32V003_PINMUX_DEFINE(PD, 2, ADC1, 0)
     147            0 : #define ADC1_A5_PD5_0 CH32V003_PINMUX_DEFINE(PD, 5, ADC1, 0)
     148            0 : #define ADC1_A7_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, ADC1, 0)
     149            0 : #define ADC1_A6_PD6_0 CH32V003_PINMUX_DEFINE(PD, 6, ADC1, 0)
     150              : 
     151              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CH32V003_PINCTRL_H_ */
        

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