Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Michael Hope <michaelh@juju.nz>
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef __CH32V00X_PINCTRL_H__
8 : #define __CH32V00X_PINCTRL_H__
9 :
10 0 : #define CH32V00X_PINMUX_PORT_PA 0
11 0 : #define CH32V00X_PINMUX_PORT_PB 1
12 0 : #define CH32V00X_PINMUX_PORT_PC 2
13 0 : #define CH32V00X_PINMUX_PORT_PD 3
14 :
15 : /* Starting bit for the remap field in PCFR1 */
16 0 : #define CH32V00X_PINMUX_SPI1_RM 0
17 0 : #define CH32V00X_PINMUX_I2C1_RM 3
18 0 : #define CH32V00X_PINMUX_USART1_RM 6
19 0 : #define CH32V00X_PINMUX_TIM1_RM 10
20 0 : #define CH32V00X_PINMUX_TIM2_RM 14
21 0 : #define CH32V00X_PINMUX_PA1PA2_RM 17
22 0 : #define CH32V00X_PINMUX_ADC_DTR_GINJ_RM 18
23 0 : #define CH32V00X_PINMUX_ADC_DTR_GREG_RM 19
24 0 : #define CH32V00X_PINMUX_USART2_RM 20
25 :
26 : /* Port number with 0-3 */
27 0 : #define CH32V00X_PINCTRL_PORT_SHIFT 0
28 0 : #define CH32V00X_PINCTRL_PORT_MASK GENMASK(1, 0)
29 : /* Pin number 0-7 */
30 0 : #define CH32V00X_PINCTRL_PIN_SHIFT 2
31 0 : #define CH32V00X_PINCTRL_PIN_MASK GENMASK(4, 2)
32 : /* Base remap bit 0-31 */
33 0 : #define CH32V00X_PINCTRL_BASE_SHIFT 5
34 0 : #define CH32V00X_PINCTRL_BASE_MASK GENMASK(9, 5)
35 : /* Function remapping ID 0-7 */
36 0 : #define CH32V00X_PINCTRL_RM_SHIFT 10
37 0 : #define CH32V00X_PINCTRL_RM_MASK GENMASK(12, 10)
38 :
39 0 : #define CH32V00X_PINMUX_DEFINE(port, pin, rm, remapping) \
40 : ((CH32V00X_PINMUX_PORT_##port << CH32V00X_PINCTRL_PORT_SHIFT) | \
41 : (pin << CH32V00X_PINCTRL_PIN_SHIFT) | \
42 : (CH32V00X_PINMUX_##rm##_RM << CH32V00X_PINCTRL_BASE_SHIFT) | \
43 : (remapping << CH32V00X_PINCTRL_RM_SHIFT))
44 :
45 0 : #define TIM1_ETR_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 0)
46 0 : #define TIM1_ETR_PD4_1 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 1)
47 0 : #define TIM1_ETR_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 2)
48 0 : #define TIM1_ETR_PC2_3 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 3)
49 0 : #define TIM1_ETR_PD4_4 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 4)
50 0 : #define TIM1_ETR_PD4_5 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 5)
51 0 : #define TIM1_ETR_PD4_6 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 6)
52 0 : #define TIM1_ETR_PB4_7 CH32V00X_PINMUX_DEFINE(PB, 4, TIM1, 7)
53 0 : #define TIM1_ETR_PB4_8 CH32V00X_PINMUX_DEFINE(PB, 4, TIM1, 8)
54 0 : #define TIM1_ETR_PB4_9 CH32V00X_PINMUX_DEFINE(PB, 4, TIM1, 9)
55 0 : #define TIM1_CH1_PD2_0 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 0)
56 0 : #define TIM1_CH1_PD2_1 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 1)
57 0 : #define TIM1_CH1_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 2)
58 0 : #define TIM1_CH1_PC4_3 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 3)
59 0 : #define TIM1_CH1_PA3_4 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 4)
60 0 : #define TIM1_CH1_PA3_5 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 5)
61 0 : #define TIM1_CH1_PA3_6 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 6)
62 0 : #define TIM1_CH1_PC4_7 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 7)
63 0 : #define TIM1_CH1_PC4_8 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 8)
64 0 : #define TIM1_CH1_PA0_9 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 9)
65 0 : #define TIM1_CH2_PA1_0 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 0)
66 0 : #define TIM1_CH2_PA1_1 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 1)
67 0 : #define TIM1_CH2_PC7_2 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 2)
68 0 : #define TIM1_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 3)
69 0 : #define TIM1_CH2_PB0_4 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 4)
70 0 : #define TIM1_CH2_PB0_5 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 5)
71 0 : #define TIM1_CH2_PB0_6 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 6)
72 0 : #define TIM1_CH2_PC5_7 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 7)
73 0 : #define TIM1_CH2_PC5_8 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 8)
74 0 : #define TIM1_CH2_PA1_9 CH32V00X_PINMUX_DEFINE(PA, 1, TIM1, 9)
75 0 : #define TIM1_CH3_PC3_0 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 0)
76 0 : #define TIM1_CH3_PC3_1 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 1)
77 0 : #define TIM1_CH3_PC0_2 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 2)
78 0 : #define TIM1_CH3_PC5_3 CH32V00X_PINMUX_DEFINE(PC, 5, TIM1, 3)
79 0 : #define TIM1_CH3_PB1_4 CH32V00X_PINMUX_DEFINE(PB, 1, TIM1, 4)
80 0 : #define TIM1_CH3_PC3_5 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 5)
81 0 : #define TIM1_CH3_PB1_6 CH32V00X_PINMUX_DEFINE(PB, 1, TIM1, 6)
82 0 : #define TIM1_CH3_PC6_7 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 7)
83 0 : #define TIM1_CH3_PC6_8 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 8)
84 0 : #define TIM1_CH3_PA2_9 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 9)
85 0 : #define TIM1_CH4_PC4_0 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 0)
86 0 : #define TIM1_CH4_PC4_1 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 1)
87 0 : #define TIM1_CH4_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, TIM1, 2)
88 0 : #define TIM1_CH4_PD4_3 CH32V00X_PINMUX_DEFINE(PD, 4, TIM1, 3)
89 0 : #define TIM1_CH4_PD1_4 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 4)
90 0 : #define TIM1_CH4_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 5)
91 0 : #define TIM1_CH4_PB2_6 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 6)
92 0 : #define TIM1_CH4_PC7_7 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 7)
93 0 : #define TIM1_CH4_PC7_8 CH32V00X_PINMUX_DEFINE(PC, 7, TIM1, 8)
94 0 : #define TIM1_CH4_PA3_9 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 9)
95 0 : #define TIM1_BKIN_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 0)
96 0 : #define TIM1_BKIN_PC2_1 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 1)
97 0 : #define TIM1_BKIN_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 2)
98 0 : #define TIM1_BKIN_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 3)
99 0 : #define TIM1_BKIN_PB3_4 CH32V00X_PINMUX_DEFINE(PB, 3, TIM1, 4)
100 0 : #define TIM1_BKIN_PB3_5 CH32V00X_PINMUX_DEFINE(PB, 3, TIM1, 5)
101 0 : #define TIM1_BKIN_PA7_6 CH32V00X_PINMUX_DEFINE(PA, 7, TIM1, 6)
102 0 : #define TIM1_BKIN_PB2_7 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 7)
103 0 : #define TIM1_BKIN_PB2_8 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 8)
104 0 : #define TIM1_BKIN_PB2_9 CH32V00X_PINMUX_DEFINE(PB, 2, TIM1, 9)
105 0 : #define TIM1_CH1N_PD0_0 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 0)
106 0 : #define TIM1_CH1N_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 1)
107 0 : #define TIM1_CH1N_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 2)
108 0 : #define TIM1_CH1N_PC3_3 CH32V00X_PINMUX_DEFINE(PC, 3, TIM1, 3)
109 0 : #define TIM1_CH1N_PA0_4 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 4)
110 0 : #define TIM1_CH1N_PA0_5 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 5)
111 0 : #define TIM1_CH1N_PA0_6 CH32V00X_PINMUX_DEFINE(PA, 0, TIM1, 6)
112 0 : #define TIM1_CH1N_PC0_7 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 7)
113 0 : #define TIM1_CH1N_PA3_8 CH32V00X_PINMUX_DEFINE(PA, 3, TIM1, 8)
114 0 : #define TIM1_CH1N_PC0_9 CH32V00X_PINMUX_DEFINE(PC, 0, TIM1, 9)
115 0 : #define TIM1_CH2N_PA2_0 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 0)
116 0 : #define TIM1_CH2N_PA2_1 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 1)
117 0 : #define TIM1_CH2N_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, TIM1, 2)
118 0 : #define TIM1_CH2N_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, TIM1, 3)
119 0 : #define TIM1_CH2N_PA2_4 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 4)
120 0 : #define TIM1_CH2N_PA2_5 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 5)
121 0 : #define TIM1_CH2N_PA2_6 CH32V00X_PINMUX_DEFINE(PA, 2, TIM1, 6)
122 0 : #define TIM1_CH2N_PC1_7 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 7)
123 0 : #define TIM1_CH2N_PB0_8 CH32V00X_PINMUX_DEFINE(PB, 0, TIM1, 8)
124 0 : #define TIM1_CH2N_PC1_9 CH32V00X_PINMUX_DEFINE(PC, 1, TIM1, 9)
125 0 : #define TIM1_CH3N_PD1_0 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 0)
126 0 : #define TIM1_CH3N_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 1)
127 0 : #define TIM1_CH3N_PD1_2 CH32V00X_PINMUX_DEFINE(PD, 1, TIM1, 2)
128 0 : #define TIM1_CH3N_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, TIM1, 3)
129 0 : #define TIM1_CH3N_PD0_4 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 4)
130 0 : #define TIM1_CH3N_PD0_5 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 5)
131 0 : #define TIM1_CH3N_PD0_6 CH32V00X_PINMUX_DEFINE(PD, 0, TIM1, 6)
132 0 : #define TIM1_CH3N_PC2_7 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 7)
133 0 : #define TIM1_CH3N_PB1_8 CH32V00X_PINMUX_DEFINE(PB, 1, TIM1, 8)
134 0 : #define TIM1_CH3N_PC2_9 CH32V00X_PINMUX_DEFINE(PC, 2, TIM1, 9)
135 :
136 0 : #define TIM2_ETR_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0)
137 0 : #define TIM2_ETR_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1)
138 0 : #define TIM2_ETR_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 2)
139 0 : #define TIM2_ETR_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3)
140 0 : #define TIM2_ETR_PC0_4 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 4)
141 0 : #define TIM2_ETR_PA0_5 CH32V00X_PINMUX_DEFINE(PA, 0, TIM2, 5)
142 0 : #define TIM2_ETR_PB1_6 CH32V00X_PINMUX_DEFINE(PB, 1, TIM2, 6)
143 0 : #define TIM2_ETR_PD3_7 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 7)
144 0 : #define TIM2_CH1_PD4_0 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 0)
145 0 : #define TIM2_CH1_PC1_1 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 1)
146 0 : #define TIM2_CH1_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, TIM2, 2)
147 0 : #define TIM2_CH1_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 3)
148 0 : #define TIM2_CH1_PC0_4 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 4)
149 0 : #define TIM2_CH1_PA0_5 CH32V00X_PINMUX_DEFINE(PA, 0, TIM2, 5)
150 0 : #define TIM2_CH1_PB1_6 CH32V00X_PINMUX_DEFINE(PB, 1, TIM2, 6)
151 0 : #define TIM2_CH1_PD3_7 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 7)
152 0 : #define TIM2_CH2_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 0)
153 0 : #define TIM2_CH2_PD3_1 CH32V00X_PINMUX_DEFINE(PD, 3, TIM2, 1)
154 0 : #define TIM2_CH2_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, TIM2, 2)
155 : /* CH32V007 specific remap */
156 0 : #define TIM2_CH2_PB3_2 CH32V00X_PINMUX_DEFINE(PB, 3, TIM2, 2)
157 0 : #define TIM2_CH2_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, TIM2, 3)
158 0 : #define TIM2_CH2_PC1_4 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 4)
159 0 : #define TIM2_CH2_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, TIM2, 5)
160 0 : #define TIM2_CH2_PA1_6 CH32V00X_PINMUX_DEFINE(PA, 1, TIM2, 6)
161 0 : #define TIM2_CH2_PD4_7 CH32V00X_PINMUX_DEFINE(PD, 4, TIM2, 7)
162 0 : #define TIM2_CH3_PC0_0 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 0)
163 0 : #define TIM2_CH3_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, TIM2, 1)
164 0 : #define TIM2_CH3_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, TIM2, 2)
165 0 : #define TIM2_CH3_PD6_3 CH32V00X_PINMUX_DEFINE(PD, 6, TIM2, 3)
166 0 : #define TIM2_CH3_PC3_4 CH32V00X_PINMUX_DEFINE(PC, 3, TIM2, 4)
167 0 : #define TIM2_CH3_PA2_5 CH32V00X_PINMUX_DEFINE(PA, 2, TIM2, 5)
168 0 : #define TIM2_CH3_PA2_6 CH32V00X_PINMUX_DEFINE(PA, 2, TIM2, 6)
169 0 : #define TIM2_CH3_PA2_7 CH32V00X_PINMUX_DEFINE(PA, 2, TIM2, 7)
170 0 : #define TIM2_CH4_PD7_0 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 0)
171 0 : #define TIM2_CH4_PD7_1 CH32V00X_PINMUX_DEFINE(PD, 7, TIM2, 1)
172 0 : #define TIM2_CH4_PC1_2 CH32V00X_PINMUX_DEFINE(PC, 1, TIM2, 2)
173 0 : #define TIM2_CH4_PD5_3 CH32V00X_PINMUX_DEFINE(PD, 5, TIM2, 3)
174 0 : #define TIM2_CH4_PB6_4 CH32V00X_PINMUX_DEFINE(PB, 6, TIM2, 4)
175 0 : #define TIM2_CH4_PA3_5 CH32V00X_PINMUX_DEFINE(PA, 3, TIM2, 5)
176 0 : #define TIM2_CH4_PA3_6 CH32V00X_PINMUX_DEFINE(PA, 3, TIM2, 6)
177 0 : #define TIM2_CH4_PA3_7 CH32V00X_PINMUX_DEFINE(PA, 3, TIM2, 7)
178 :
179 0 : #define USART1_TX_PD5_0 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 0)
180 0 : #define USART1_TX_PD6_1 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 1)
181 0 : #define USART1_TX_PD0_2 CH32V00X_PINMUX_DEFINE(PD, 0, USART1, 2)
182 0 : #define USART1_TX_PC0_3 CH32V00X_PINMUX_DEFINE(PC, 0, USART1, 3)
183 0 : #define USART1_TX_PD1_4 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 4)
184 0 : #define USART1_TX_PB3_5 CH32V00X_PINMUX_DEFINE(PB, 3, USART1, 5)
185 0 : #define USART1_TX_PC5_6 CH32V00X_PINMUX_DEFINE(PC, 5, USART1, 6)
186 0 : #define USART1_TX_PB5_7 CH32V00X_PINMUX_DEFINE(PB, 5, USART1, 7)
187 0 : #define USART1_TX_PA0_8 CH32V00X_PINMUX_DEFINE(PA, 0, USART1, 8)
188 0 : #define USART1_TX_PA0_9 CH32V00X_PINMUX_DEFINE(PA, 0, USART1, 9)
189 0 : #define USART1_RX_PD6_0 CH32V00X_PINMUX_DEFINE(PD, 6, USART1, 0)
190 0 : #define USART1_RX_PD5_1 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 1)
191 0 : #define USART1_RX_PD1_2 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 2)
192 0 : #define USART1_RX_PC1_3 CH32V00X_PINMUX_DEFINE(PC, 1, USART1, 3)
193 0 : #define USART1_RX_PB3_4 CH32V00X_PINMUX_DEFINE(PB, 3, USART1, 4)
194 0 : #define USART1_RX_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, USART1, 5)
195 0 : #define USART1_RX_PC6_6 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 6)
196 0 : #define USART1_RX_PB6_7 CH32V00X_PINMUX_DEFINE(PB, 6, USART1, 7)
197 0 : #define USART1_RX_PA1_8 CH32V00X_PINMUX_DEFINE(PA, 1, USART1, 8)
198 0 : #define USART1_RX_PC4_9 CH32V00X_PINMUX_DEFINE(PC, 4, USART1, 9)
199 0 : #define USART1_CTS_PD3_0 CH32V00X_PINMUX_DEFINE(PD, 3, USART1, 0)
200 0 : #define USART1_CTS_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 1)
201 0 : #define USART1_CTS_PC3_2 CH32V00X_PINMUX_DEFINE(PC, 3, USART1, 2)
202 0 : #define USART1_CTS_PC6_3 CH32V00X_PINMUX_DEFINE(PC, 6, USART1, 3)
203 0 : #define USART1_CTS_PD7_4 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 4)
204 0 : #define USART1_CTS_PD7_5 CH32V00X_PINMUX_DEFINE(PD, 7, USART1, 5)
205 0 : #define USART1_CTS_PC7_6 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 6)
206 0 : #define USART1_CTS_PC7_7 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 7)
207 0 : #define USART1_CTS_PD2_8 CH32V00X_PINMUX_DEFINE(PD, 2, USART1, 8)
208 0 : #define USART1_CTS_PD5_9 CH32V00X_PINMUX_DEFINE(PD, 5, USART1, 9)
209 0 : #define USART1_RTS_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 0)
210 0 : #define USART1_RTS_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 1)
211 0 : #define USART1_RTS_PC2_2 CH32V00X_PINMUX_DEFINE(PC, 2, USART1, 2)
212 0 : #define USART1_RTS_PC7_3 CH32V00X_PINMUX_DEFINE(PC, 7, USART1, 3)
213 0 : #define USART1_RTS_PA5_4 CH32V00X_PINMUX_DEFINE(PA, 5, USART1, 4)
214 0 : #define USART1_RTS_PA5_5 CH32V00X_PINMUX_DEFINE(PA, 5, USART1, 5)
215 0 : #define USART1_RTS_PB4_6 CH32V00X_PINMUX_DEFINE(PB, 4, USART1, 6)
216 0 : #define USART1_RTS_PB4_7 CH32V00X_PINMUX_DEFINE(PB, 4, USART1, 7)
217 0 : #define USART1_RTS_PD3_8 CH32V00X_PINMUX_DEFINE(PD, 3, USART1, 8)
218 0 : #define USART1_RTS_PD4_9 CH32V00X_PINMUX_DEFINE(PD, 4, USART1, 9)
219 :
220 0 : #define USART2_TX_PA7_0 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 0)
221 0 : #define USART2_TX_PA4_1 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 1)
222 0 : #define USART2_TX_PA2_2 CH32V00X_PINMUX_DEFINE(PA, 2, USART2, 2)
223 0 : #define USART2_TX_PD2_3 CH32V00X_PINMUX_DEFINE(PD, 2, USART2, 3)
224 0 : #define USART2_TX_PB0_4 CH32V00X_PINMUX_DEFINE(PB, 0, USART2, 4)
225 0 : #define USART2_TX_PC4_5 CH32V00X_PINMUX_DEFINE(PC, 4, USART2, 5)
226 0 : #define USART2_TX_PA6_6 CH32V00X_PINMUX_DEFINE(PA, 6, USART2, 6)
227 0 : #define USART2_RX_PB3_0 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 0)
228 0 : #define USART2_RX_PA5_1 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 1)
229 0 : #define USART2_RX_PA3_2 CH32V00X_PINMUX_DEFINE(PA, 3, USART2, 2)
230 0 : #define USART2_RX_PD3_3 CH32V00X_PINMUX_DEFINE(PD, 3, USART2, 3)
231 0 : #define USART2_RX_PB1_4 CH32V00X_PINMUX_DEFINE(PB, 1, USART2, 4)
232 0 : #define USART2_RX_PD1_5 CH32V00X_PINMUX_DEFINE(PD, 1, USART2, 5)
233 0 : #define USART2_RX_PA5_6 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 6)
234 0 : #define USART2_CTS_PA4_0 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 0)
235 0 : #define USART2_CTS_PA7_1 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 1)
236 0 : #define USART2_CTS_PA0_2 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 2)
237 0 : #define USART2_CTS_PA0_3 CH32V00X_PINMUX_DEFINE(PA, 0, USART2, 3)
238 0 : #define USART2_CTS_PB6_4 CH32V00X_PINMUX_DEFINE(PB, 6, USART2, 4)
239 0 : #define USART2_CTS_PA4_5 CH32V00X_PINMUX_DEFINE(PA, 4, USART2, 5)
240 0 : #define USART2_CTS_PA7_6 CH32V00X_PINMUX_DEFINE(PA, 7, USART2, 6)
241 0 : #define USART2_RTS_PA5_0 CH32V00X_PINMUX_DEFINE(PA, 5, USART2, 0)
242 0 : #define USART2_RTS_PB3_1 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 1)
243 0 : #define USART2_RTS_PA1_2 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 2)
244 0 : #define USART2_RTS_PA1_3 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 3)
245 0 : #define USART2_RTS_PA1_4 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 4)
246 0 : #define USART2_RTS_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, USART2, 5)
247 0 : #define USART2_RTS_PB3_6 CH32V00X_PINMUX_DEFINE(PB, 3, USART2, 6)
248 :
249 0 : #define SPI1_NSS_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, SPI1, 0)
250 0 : #define SPI1_NSS_PC0_1 CH32V00X_PINMUX_DEFINE(PC, 0, SPI1, 1)
251 0 : #define SPI1_NSS_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, SPI1, 2)
252 0 : #define SPI1_NSS_PB0_3 CH32V00X_PINMUX_DEFINE(PB, 0, SPI1, 3)
253 0 : #define SPI1_NSS_PD3_4 CH32V00X_PINMUX_DEFINE(PD, 3, SPI1, 4)
254 0 : #define SPI1_NSS_PC1_5 CH32V00X_PINMUX_DEFINE(PC, 1, SPI1, 5)
255 0 : #define SPI1_NSS_PC4_6 CH32V00X_PINMUX_DEFINE(PC, 4, SPI1, 6)
256 0 : #define SPI1_SCK_PC5_0 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 0)
257 0 : #define SPI1_SCK_PC5_1 CH32V00X_PINMUX_DEFINE(PC, 5, SPI1, 1)
258 0 : #define SPI1_SCK_PD2_2 CH32V00X_PINMUX_DEFINE(PD, 2, SPI1, 2)
259 0 : #define SPI1_SCK_PB1_3 CH32V00X_PINMUX_DEFINE(PB, 1, SPI1, 3)
260 0 : #define SPI1_SCK_PD4_4 CH32V00X_PINMUX_DEFINE(PD, 4, SPI1, 4)
261 0 : #define SPI1_SCK_PA1_5 CH32V00X_PINMUX_DEFINE(PA, 1, SPI1, 5)
262 0 : #define SPI1_SCK_PB5_6 CH32V00X_PINMUX_DEFINE(PB, 5, SPI1, 6)
263 0 : #define SPI1_MISO_PC7_0 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 0)
264 0 : #define SPI1_MISO_PC7_1 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 1)
265 0 : #define SPI1_MISO_PB3_2 CH32V00X_PINMUX_DEFINE(PB, 3, SPI1, 2)
266 0 : #define SPI1_MISO_PB2_3 CH32V00X_PINMUX_DEFINE(PB, 2, SPI1, 3)
267 0 : #define SPI1_MISO_PD5_4 CH32V00X_PINMUX_DEFINE(PD, 5, SPI1, 4)
268 0 : #define SPI1_MISO_PB5_5 CH32V00X_PINMUX_DEFINE(PB, 5, SPI1, 5)
269 0 : #define SPI1_MISO_PC7_6 CH32V00X_PINMUX_DEFINE(PC, 7, SPI1, 6)
270 0 : #define SPI1_MOSI_PC6_0 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 0)
271 0 : #define SPI1_MOSI_PC6_1 CH32V00X_PINMUX_DEFINE(PC, 6, SPI1, 1)
272 0 : #define SPI1_MOSI_PD3_2 CH32V00X_PINMUX_DEFINE(PD, 3, SPI1, 2)
273 0 : #define SPI1_MOSI_PC0_3 CH32V00X_PINMUX_DEFINE(PC, 0, SPI1, 3)
274 0 : #define SPI1_MOSI_PD6_4 CH32V00X_PINMUX_DEFINE(PD, 6, SPI1, 4)
275 0 : #define SPI1_MOSI_PA2_5 CH32V00X_PINMUX_DEFINE(PA, 2, SPI1, 5)
276 0 : #define SPI1_MOSI_PB4_6 CH32V00X_PINMUX_DEFINE(PB, 4, SPI1, 6)
277 :
278 0 : #define I2C1_SCL_PC2_0 CH32V00X_PINMUX_DEFINE(PC, 2, I2C1, 0)
279 0 : #define I2C1_SCL_PD1_1 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 1)
280 0 : #define I2C1_SCL_PC5_2 CH32V00X_PINMUX_DEFINE(PC, 5, I2C1, 2)
281 0 : #define I2C1_SCL_PB5_3 CH32V00X_PINMUX_DEFINE(PB, 5, I2C1, 3)
282 0 : #define I2C1_SCL_PB3_4 CH32V00X_PINMUX_DEFINE(PB, 3, I2C1, 4)
283 0 : #define I2C1_SDA_PC1_0 CH32V00X_PINMUX_DEFINE(PC, 1, I2C1, 0)
284 0 : #define I2C1_SDA_PD0_1 CH32V00X_PINMUX_DEFINE(PD, 0, I2C1, 1)
285 0 : #define I2C1_SDA_PC6_2 CH32V00X_PINMUX_DEFINE(PC, 6, I2C1, 2)
286 : /* CH32V007 specific remap */
287 0 : #define I2C1_SDA_PC4_2 CH32V00X_PINMUX_DEFINE(PC, 4, I2C1, 2)
288 0 : #define I2C1_SDA_PB6_3 CH32V00X_PINMUX_DEFINE(PB, 6, I2C1, 3)
289 0 : #define I2C1_SDA_PD1_4 CH32V00X_PINMUX_DEFINE(PD, 1, I2C1, 4)
290 :
291 : #endif /* __CH32V00X_PINCTRL_H__ */
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