Line data Source code
1 0 : /*
2 : * Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 :
7 : #ifndef __CH32V20X_V30X_PINCTRL_H__
8 : #define __CH32V20X_V30X_PINCTRL_H__
9 :
10 0 : #define CH32V20X_V30X_PINMUX_PORT_PA 0
11 0 : #define CH32V20X_V30X_PINMUX_PORT_PB 1
12 0 : #define CH32V20X_V30X_PINMUX_PORT_PC 2
13 0 : #define CH32V20X_V30X_PINMUX_PORT_PD 3
14 0 : #define CH32V20X_V30X_PINMUX_PORT_PE 4
15 :
16 : /*
17 : * Defines the starting bit for the remap field.
18 : */
19 0 : #define CH32V20X_V30X_PINMUX_SPI1_RM 0
20 0 : #define CH32V20X_V30X_PINMUX_I2C1_RM 1
21 0 : #define CH32V20X_V30X_PINMUX_USART1_RM 2
22 0 : #define CH32V20X_V30X_PINMUX_USART2_RM 3
23 0 : #define CH32V20X_V30X_PINMUX_USART3_RM 4
24 0 : #define CH32V20X_V30X_PINMUX_TIM1_RM 6
25 0 : #define CH32V20X_V30X_PINMUX_TIM2_RM 8
26 0 : #define CH32V20X_V30X_PINMUX_TIM3_RM 10
27 0 : #define CH32V20X_V30X_PINMUX_TIM4_RM 12
28 0 : #define CH32V20X_V30X_PINMUX_CAN1_RM 13
29 0 : #define CH32V20X_V30X_PINMUX_PD01_RM 15
30 0 : #define CH32V20X_V30X_PINMUX_TIM5CH4_RM 16
31 0 : #define CH32V20X_V30X_PINMUX_ETH_RM 21
32 0 : #define CH32V20X_V30X_PINMUX_CAN2_RM 22
33 0 : #define CH32V20X_V30X_PINMUX_RMII_RM 23
34 0 : #define CH32V20X_V30X_PINMUX_SDI_RM 24
35 0 : #define CH32V20X_V30X_PINMUX_SPI3_RM 28
36 :
37 0 : #define CH32V20X_V30X_PINMUX_TIM8_RM (32 + 2)
38 0 : #define CH32V20X_V30X_PINMUX_TIM9_RM (32 + 3)
39 0 : #define CH32V20X_V30X_PINMUX_TIM10_RM (32 + 5)
40 0 : #define CH32V20X_V30X_PINMUX_USART4_RM (32 + 16)
41 0 : #define CH32V20X_V30X_PINMUX_USART5_RM (32 + 18)
42 0 : #define CH32V20X_V30X_PINMUX_USART6_RM (32 + 20)
43 0 : #define CH32V20X_V30X_PINMUX_USART7_RM (32 + 22)
44 0 : #define CH32V20X_V30X_PINMUX_USART8_RM (32 + 24)
45 0 : #define CH32V20X_V30X_PINMUX_USART1_RM1 (32 + 26)
46 :
47 : /* Port number with 0-4 */
48 0 : #define CH32V20X_V30X_PINCTRL_PORT_SHIFT 0
49 0 : #define CH32V20X_V30X_PINCTRL_PORT_MASK GENMASK(2, 0)
50 : /* Pin number 0-15 */
51 0 : #define CH32V20X_V30X_PINCTRL_PIN_SHIFT 3
52 0 : #define CH32V20X_V30X_PINCTRL_PIN_MASK GENMASK(6, 3)
53 : /* Base remap bit 0-31 */
54 0 : #define CH32V20X_V30X_PINCTRL_RM_BASE_SHIFT 7
55 0 : #define CH32V20X_V30X_PINCTRL_RM_BASE_MASK GENMASK(11, 7)
56 : /* Remap Register ID */
57 0 : #define CH32V20X_V30X_PINCTRL_PCFR_ID_SHIFT 12
58 0 : #define CH32V20X_V30X_PINCTRL_PCFR_ID_MASK GENMASK(12, 12)
59 : /* Function remapping ID 0-3 */
60 0 : #define CH32V20X_V30X_PINCTRL_RM_SHIFT 13
61 0 : #define CH32V20X_V30X_PINCTRL_RM_MASK GENMASK(14, 13)
62 :
63 0 : #define CH32V20X_V30X_PINMUX_DEFINE(port, pin, rm, remapping) \
64 : ((CH32V20X_V30X_PINMUX_PORT_##port << CH32V20X_V30X_PINCTRL_PORT_SHIFT) | \
65 : (pin << CH32V20X_V30X_PINCTRL_PIN_SHIFT) | \
66 : (CH32V20X_V30X_PINMUX_##rm##_RM << CH32V20X_V30X_PINCTRL_RM_BASE_SHIFT) | \
67 : (remapping << CH32V20X_V30X_PINCTRL_RM_SHIFT))
68 :
69 : /* Pin swaps.
70 : * Warning: Some of those do not apply to all packages.
71 : * Verify using reference manual and use CH32V20X_V30X_PINMUX_DEFINE directly if needed.
72 : */
73 :
74 0 : #define USART1_CK_PA8_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, USART1, 0)
75 0 : #define USART1_CK_PA8_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, USART1, 1)
76 0 : #define USART1_CK_PA10_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 10, USART1, 2)
77 0 : #define USART1_CK_PA5_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, USART1, 3)
78 0 : #define USART1_TX_PA9_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 9, USART1, 0)
79 0 : #define USART1_TX_PB6_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 6, USART1, 1)
80 0 : #define USART1_TX_PB15_2 CH32V20X_V30X_PINMUX_DEFINE(PB, 15, USART1, 2)
81 0 : #define USART1_TX_PA6_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, USART1, 3)
82 0 : #define USART1_RX_PA10_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 10, USART1, 0)
83 0 : #define USART1_RX_PB7_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, USART1, 1)
84 0 : #define USART1_RX_PA8_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 8, USART1, 2)
85 0 : #define USART1_RX_PA7_3 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, USART1, 3)
86 0 : #define USART1_CTS_PA11_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, USART1, 0)
87 0 : #define USART1_CTS_PA11_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, USART1, 1)
88 0 : #define USART1_CTS_PA5_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, USART1, 2)
89 0 : #define USART1_CTS_PC4_3 CH32V20X_V30X_PINMUX_DEFINE(PC, 4, USART1, 3)
90 0 : #define USART1_RTS_PA12_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, USART1, 0)
91 0 : #define USART1_RTS_PA12_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, USART1, 1)
92 0 : #define USART1_RTS_PA9_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 9, USART1, 2)
93 0 : #define USART1_RTS_PC5_3 CH32V20X_V30X_PINMUX_DEFINE(PC, 5, USART1, 3)
94 :
95 0 : #define USART2_CK_PA4_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, USART2, 0)
96 0 : #define USART2_CK_PD7_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 7, USART2, 1)
97 0 : #define USART2_TX_PA2_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 2, USART2, 0)
98 0 : #define USART2_TX_PD5_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 5, USART2, 1)
99 0 : #define USART2_RX_PA3_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 3, USART2, 0)
100 0 : #define USART2_RX_PD6_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 6, USART2, 1)
101 0 : #define USART2_CTS_PA0_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, USART2, 0)
102 0 : #define USART2_CTS_PD3_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 3, USART2, 1)
103 0 : #define USART2_RTS_PA1_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, USART2, 0)
104 0 : #define USART2_RTS_PD4_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 4, USART2, 1)
105 :
106 0 : #define USART3_CK_PB12_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 12, USART3, 0)
107 0 : #define USART3_CK_PC12_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 12, USART3, 1)
108 0 : #define USART3_CK_PD10_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 10, USART3, 2)
109 0 : #define USART3_CK_PD10_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 10, USART3, 3)
110 0 : #define USART3_TX_PB10_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 10, USART3, 0)
111 0 : #define USART3_TX_PC10_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 10, USART3, 1)
112 0 : #define USART3_TX_PA13_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 13, USART3, 2)
113 0 : #define USART3_TX_PD8_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 8, USART3, 3)
114 0 : #define USART3_RX_PB11_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 11, USART3, 0)
115 0 : #define USART3_RX_PC11_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 11, USART3, 1)
116 0 : #define USART3_RX_PA14_2 CH32V20X_V30X_PINMUX_DEFINE(PA, 14, USART3, 2)
117 0 : #define USART3_RX_PD9_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 9, USART3, 3)
118 0 : #define USART3_CTS_PB13_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, USART3, 0)
119 0 : #define USART3_CTS_PB13_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, USART3, 1)
120 0 : #define USART3_CTS_PD11_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 11, USART3, 2)
121 0 : #define USART3_CTS_PD11_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 11, USART3, 3)
122 0 : #define USART3_RTS_PB14_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, USART3, 0)
123 0 : #define USART3_RTS_PB14_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, USART3, 1)
124 0 : #define USART3_RTS_PD12_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, USART3, 2)
125 0 : #define USART3_RTS_PD12_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, USART3, 3)
126 :
127 0 : #define USART4_CK_PB2_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 2, USART4, 0)
128 0 : #define USART4_CK_PA6_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, USART4, 1)
129 0 : #define USART4_TX_PB0_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 0, USART4, 0)
130 0 : #define USART4_TX_PA5_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, USART4, 1)
131 0 : #define USART4_RX_PB1_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 1, USART4, 0)
132 0 : #define USART4_RX_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, USART4, 1)
133 0 : #define USART4_CTS_PB3_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, USART4, 0)
134 0 : #define USART4_CTS_PA7_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, USART4, 1)
135 0 : #define USART4_RTS_PB4_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, USART4, 0)
136 0 : #define USART4_RTS_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, USART4, 1)
137 :
138 0 : #define USART5_TX_PC12_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 12, USART5, 0)
139 0 : #define USART5_TX_PB4_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, USART5, 1)
140 0 : #define USART5_TX_PE8_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 8, USART5, 2)
141 0 : #define USART5_RX_PD2_0 CH32V20X_V30X_PINMUX_DEFINE(PD, 2, USART5, 0)
142 0 : #define USART5_RX_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, USART5, 1)
143 0 : #define USART5_RX_PE9_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 9, USART5, 2)
144 :
145 0 : #define USART6_TX_PC0_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 0, USART6, 0)
146 0 : #define USART6_TX_PB8_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, USART6, 1)
147 0 : #define USART6_TX_PE10_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 10, USART6, 2)
148 0 : #define USART6_RX_PC1_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 1, USART6, 0)
149 0 : #define USART6_RX_PB9_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, USART6, 1)
150 0 : #define USART6_RX_PE11_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 11, USART6, 2)
151 :
152 0 : #define USART7_TX_PC2_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 2, USART7, 0)
153 0 : #define USART7_TX_PA6_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, USART7, 1)
154 0 : #define USART7_TX_PE12_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 12, USART7, 2)
155 0 : #define USART7_RX_PC3_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 3, USART7, 0)
156 0 : #define USART7_RX_PA7_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, USART7, 1)
157 0 : #define USART7_RX_PE13_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 13, USART7, 2)
158 :
159 0 : #define USART8_TX_PC4_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 4, USART8, 0)
160 0 : #define USART8_TX_PA14_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 14, USART8, 1)
161 0 : #define USART8_TX_PE14_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 14, USART8, 2)
162 0 : #define USART8_RX_PC5_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 5, USART8, 0)
163 0 : #define USART8_RX_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, USART8, 1)
164 0 : #define USART8_RX_PE15_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 15, USART8, 2)
165 :
166 0 : #define SPI1_NSS_PA4_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, SPI1, 0)
167 0 : #define SPI1_NSS_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, SPI1, 1)
168 0 : #define SPI1_SCK_PA5_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, SPI1, 0)
169 0 : #define SPI1_SCK_PB3_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, SPI1, 1)
170 0 : #define SPI1_MISO_PA6_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, SPI1, 0)
171 0 : #define SPI1_MISO_PB4_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, SPI1, 1)
172 0 : #define SPI1_MOSI_PA7_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, SPI1, 0)
173 0 : #define SPI1_MOSI_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, SPI1, 1)
174 :
175 0 : #define I2C1_SCL_PB6_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 6, I2C1, 0)
176 0 : #define I2C1_SCL_PB8_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, I2C1, 1)
177 0 : #define I2C1_SDA_PB7_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, I2C1, 0)
178 0 : #define I2C1_SDA_PB9_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, I2C1, 1)
179 :
180 0 : #define SPI1_NSS_PA4_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, SPI1, 0)
181 0 : #define SPI1_NSS_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, SPI1, 1)
182 0 : #define SPI1_SCK_PA5_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 5, SPI1, 0)
183 0 : #define SPI1_SCK_PB3_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, SPI1, 1)
184 0 : #define SPI1_MISO_PA6_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, SPI1, 0)
185 0 : #define SPI1_MISO_PB4_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, SPI1, 1)
186 0 : #define SPI1_MOSI_PA7_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, SPI1, 0)
187 0 : #define SPI1_MOSI_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, SPI1, 1)
188 :
189 0 : #define SPI2_NSS_PB12_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 12, SPI2, 0)
190 0 : #define SPI2_SCK_PB13_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, SPI2, 0)
191 0 : #define SPI2_MISO_PB14_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, SPI2, 0)
192 0 : #define SPI2_MOSI_PB15_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 15, SPI2, 0)
193 :
194 0 : #define SPI3_NSS_PA15_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, SPI3, 0)
195 0 : #define SPI3_NSS_PA4_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 4, SPI3, 1)
196 0 : #define SPI3_SCK_PB3_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 3, SPI3, 0)
197 0 : #define SPI3_SCK_PC10_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 10, SPI3, 1)
198 0 : #define SPI3_MISO_PB4_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, SPI3, 0)
199 0 : #define SPI3_MISO_PC11_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 11, SPI3, 1)
200 0 : #define SPI3_MOSI_PB5_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, SPI3, 0)
201 0 : #define SPI3_MOSI_PC12_1 CH32V20X_V30X_PINMUX_DEFINE(PC, 12, SPI3, 1)
202 :
203 : #endif /* __CH32V20X_V30X_PINCTRL_H__ */
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