Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP_PINCTRL_COMMON_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP_PINCTRL_COMMON_H_
       9              : 
      10              : #include <zephyr/dt-bindings/dt-util.h>
      11              : 
      12            0 : #define ESP32_PIN_NUM_SHIFT      0U
      13            0 : #define ESP32_PIN_NUM_MASK       0x3FU
      14              : 
      15              : /*
      16              :  * Definitions used to extract I/O
      17              :  * signal indexes used by the GPIO
      18              :  * matrix signal routing mechanism
      19              :  */
      20            0 : #define ESP32_PIN_SIGI_MASK      0x1FFU
      21            0 : #define ESP32_PIN_SIGI_SHIFT     6U
      22            0 : #define ESP32_PIN_SIGO_MASK      0x1FFU
      23            0 : #define ESP32_PIN_SIGO_SHIFT     15U
      24            0 : #define ESP_SIG_INVAL            ESP32_PIN_SIGI_MASK
      25              : 
      26            0 : #define ESP32_PINMUX(pin, sig_i, sig_o)                                         \
      27              :                 (((pin & ESP32_PIN_NUM_MASK) << ESP32_PIN_NUM_SHIFT) |                \
      28              :                 ((sig_i & ESP32_PIN_SIGI_MASK) << ESP32_PIN_SIGI_SHIFT) |     \
      29              :                 ((sig_o & ESP32_PIN_SIGO_MASK) << ESP32_PIN_SIGO_SHIFT))
      30              : 
      31              : /*
      32              :  * Definitions used to extract pin
      33              :  * properties: bias, drive and
      34              :  * initial pin level
      35              :  */
      36            0 : #define ESP32_PIN_BIAS_SHIFT     0U
      37            0 : #define ESP32_PIN_BIAS_MASK      0x3U
      38            0 : #define ESP32_PIN_DRV_SHIFT      2U
      39            0 : #define ESP32_PIN_DRV_MASK       0x3U
      40            0 : #define ESP32_PIN_OUT_SHIFT      4U
      41            0 : #define ESP32_PIN_OUT_MASK       0x3U
      42            0 : #define ESP32_PIN_EN_DIR_SHIFT   6U
      43            0 : #define ESP32_PIN_EN_DIR_MASK    0x3U
      44              : 
      45              : /* Bias definitions */
      46            0 : #define ESP32_NO_PULL            0x1
      47            0 : #define ESP32_PULL_UP            0x2
      48            0 : #define ESP32_PULL_DOWN          0x3
      49              : 
      50              : /* Pin drive definitions */
      51            0 : #define ESP32_PUSH_PULL          0x1
      52            0 : #define ESP32_OPEN_DRAIN         0x2
      53              : 
      54              : /*
      55              :  * An output pin can be initialized
      56              :  * to either high or low
      57              :  */
      58            0 : #define ESP32_PIN_OUT_HIGH       0x1
      59            0 : #define ESP32_PIN_OUT_LOW        0x2
      60              : 
      61              : /*
      62              :  * Enable input or output on pin
      63              :  * regardless of its direction
      64              :  */
      65            0 : #define ESP32_PIN_OUT_EN       0x1
      66            0 : #define ESP32_PIN_IN_EN        0x2
      67              : 
      68              : /*
      69              :  * These flags are used by the pinctrl
      70              :  * driver, based on the DTS properties
      71              :  * assigned to a specific pin state
      72              :  */
      73            0 : #define ESP32_NO_PULL_FLAG       BIT(0)
      74            0 : #define ESP32_PULL_UP_FLAG       BIT(1)
      75            0 : #define ESP32_PULL_DOWN_FLAG     BIT(2)
      76            0 : #define ESP32_PUSH_PULL_FLAG     BIT(3)
      77            0 : #define ESP32_OPEN_DRAIN_FLAG    BIT(4)
      78            0 : #define ESP32_DIR_INP_FLAG       BIT(5)
      79            0 : #define ESP32_DIR_OUT_FLAG       BIT(6)
      80            0 : #define ESP32_PIN_OUT_HIGH_FLAG  BIT(7)
      81            0 : #define ESP32_PIN_OUT_LOW_FLAG   BIT(8)
      82            0 : #define ESP32_PIN_OUT_EN_FLAG    BIT(9)
      83            0 : #define ESP32_PIN_IN_EN_FLAG     BIT(10)
      84              : 
      85              : #endif  /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP_PINCTRL_COMMON_H_ */