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1 0 : /* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or 2 : * an affiliate of Cypress Semiconductor Corporation 3 : * 4 : * SPDX-License-Identifier: Apache-2.0 5 : */ 6 : 7 : /** 8 : * @brief Pin control binding helper. 9 : */ 10 : 11 : /** 12 : * Bit definition in PINMUX field 13 : */ 14 1 : #define SOC_PINMUX_PORT_POS (0) 15 0 : #define SOC_PINMUX_PORT_MASK (0xFFul << SOC_PINMUX_PORT_POS) 16 0 : #define SOC_PINMUX_PIN_POS (8) 17 0 : #define SOC_PINMUX_PIN_MASK (0xFFul << SOC_PINMUX_PIN_POS) 18 0 : #define SOC_PINMUX_HSIOM_FUNC_POS (16) 19 0 : #define SOC_PINMUX_HSIOM_MASK (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS) 20 0 : #define SOC_PINMUX_SIGNAL_POS (24) 21 0 : #define SOC_PINMUX_SIGNAL_MASK (0xFFul << SOC_PINMUX_SIGNAL_POS) 22 : 23 : /** 24 : * Functions are defined using HSIOM SEL 25 : */ 26 1 : #define HSIOM_SEL_GPIO (0) 27 0 : #define HSIOM_SEL_GPIO_DSI (1) 28 0 : #define HSIOM_SEL_DSI_DSI (2) 29 0 : #define HSIOM_SEL_DSI_GPIO (3) 30 0 : #define HSIOM_SEL_AMUXA (4) 31 0 : #define HSIOM_SEL_AMUXB (5) 32 0 : #define HSIOM_SEL_AMUXA_DSI (6) 33 0 : #define HSIOM_SEL_AMUXB_DSI (7) 34 0 : #define HSIOM_SEL_ACT_0 (8) 35 0 : #define HSIOM_SEL_ACT_1 (9) 36 0 : #define HSIOM_SEL_ACT_2 (10) 37 0 : #define HSIOM_SEL_ACT_3 (11) 38 0 : #define HSIOM_SEL_DS_0 (12) 39 0 : #define HSIOM_SEL_DS_1 (13) 40 0 : #define HSIOM_SEL_DS_2 (14) 41 0 : #define HSIOM_SEL_DS_3 (15) 42 0 : #define HSIOM_SEL_ACT_4 (16) 43 0 : #define HSIOM_SEL_ACT_5 (17) 44 0 : #define HSIOM_SEL_ACT_6 (18) 45 0 : #define HSIOM_SEL_ACT_7 (19) 46 0 : #define HSIOM_SEL_ACT_8 (20) 47 0 : #define HSIOM_SEL_ACT_9 (21) 48 0 : #define HSIOM_SEL_ACT_10 (22) 49 0 : #define HSIOM_SEL_ACT_11 (23) 50 0 : #define HSIOM_SEL_ACT_12 (24) 51 0 : #define HSIOM_SEL_ACT_13 (25) 52 0 : #define HSIOM_SEL_ACT_14 (26) 53 0 : #define HSIOM_SEL_ACT_15 (27) 54 0 : #define HSIOM_SEL_DS_4 (28) 55 0 : #define HSIOM_SEL_DS_5 (29) 56 0 : #define HSIOM_SEL_DS_6 (30) 57 0 : #define HSIOM_SEL_DS_7 (31) 58 : 59 : /** 60 : * Macro to set drive mode 61 : */ 62 1 : #define DT_CAT1_DRIVE_MODE_INFO(peripheral_signal) \ 63 : CAT1_PIN_MAP_DRIVE_MODE_##peripheral_signal 64 : 65 : /** 66 : * Macro to set pin control information (from pinctrl node) 67 : */ 68 1 : #define DT_CAT1_PINMUX(port, pin, hsiom) \ 69 : ((port << SOC_PINMUX_PORT_POS) | \ 70 : (pin << SOC_PINMUX_PIN_POS) | \ 71 : (hsiom << SOC_PINMUX_HSIOM_FUNC_POS)) 72 : 73 : /* Redefine DT GPIO label (Px) to CYHAL port macros (CYHAL_PORT_x) */ 74 0 : #define P0 CYHAL_PORT_0 75 0 : #define P1 CYHAL_PORT_1 76 0 : #define P2 CYHAL_PORT_2 77 0 : #define P3 CYHAL_PORT_3 78 0 : #define P4 CYHAL_PORT_4 79 0 : #define P5 CYHAL_PORT_5 80 0 : #define P6 CYHAL_PORT_6 81 0 : #define P7 CYHAL_PORT_7 82 0 : #define P8 CYHAL_PORT_8 83 0 : #define P9 CYHAL_PORT_9 84 0 : #define P10 CYHAL_PORT_10 85 0 : #define P11 CYHAL_PORT_11 86 0 : #define P12 CYHAL_PORT_12 87 0 : #define P13 CYHAL_PORT_13 88 0 : #define P14 CYHAL_PORT_14 89 0 : #define P15 CYHAL_PORT_15 90 0 : #define P16 CYHAL_PORT_16 91 0 : #define P17 CYHAL_PORT_17 92 0 : #define P18 CYHAL_PORT_18 93 0 : #define P19 CYHAL_PORT_19 94 0 : #define P20 CYHAL_PORT_20 95 : 96 : /* Returns CYHAL GPIO from Board device tree GPIO configuration 97 : * CYHAL_GET_GPIO(port_number, pin_number), 98 : * port_number = ((REG ADDR of node) - (REG ADDR of gpio_prt0)) / (REG SIZE of gpio_prt0) 99 : * pin_number = DT_PHA_BY_IDX(node, gpios_prop, 0, pin) 100 : */ 101 0 : #define DT_GET_CYHAL_GPIO_FROM_DT_GPIOS(node, gpios_prop) \ 102 : CYHAL_GET_GPIO( \ 103 : (DT_REG_ADDR_BY_IDX(DT_GPIO_CTLR_BY_IDX(node, gpios_prop, 0), 0) - \ 104 : DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 0)) / \ 105 : DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 1), \ 106 : DT_PHA_BY_IDX(node, gpios_prop, 0, pin) \ 107 : )
