Line data Source code
1 0 : /* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
2 : * an affiliate of Cypress Semiconductor Corporation
3 : *
4 : * SPDX-License-Identifier: Apache-2.0
5 : */
6 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_
7 : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_
8 : /**
9 : * @brief Pin control binding helper.
10 : */
11 :
12 : /**
13 : * Bit definition in PINMUX field
14 : */
15 1 : #define SOC_PINMUX_PORT_POS (0)
16 0 : #define SOC_PINMUX_PORT_MASK (0xFFul << SOC_PINMUX_PORT_POS)
17 0 : #define SOC_PINMUX_PIN_POS (8)
18 0 : #define SOC_PINMUX_PIN_MASK (0xFFul << SOC_PINMUX_PIN_POS)
19 0 : #define SOC_PINMUX_HSIOM_FUNC_POS (16)
20 0 : #define SOC_PINMUX_HSIOM_MASK (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS)
21 0 : #define SOC_PINMUX_SIGNAL_POS (24)
22 0 : #define SOC_PINMUX_SIGNAL_MASK (0xFFul << SOC_PINMUX_SIGNAL_POS)
23 :
24 : /**
25 : * Functions are defined using HSIOM SEL
26 : */
27 1 : #define HSIOM_SEL_GPIO (0)
28 0 : #define HSIOM_SEL_GPIO_DSI (1)
29 0 : #define HSIOM_SEL_DSI_DSI (2)
30 0 : #define HSIOM_SEL_DSI_GPIO (3)
31 0 : #define HSIOM_SEL_AMUXA (4)
32 0 : #define HSIOM_SEL_AMUXB (5)
33 0 : #define HSIOM_SEL_AMUXA_DSI (6)
34 0 : #define HSIOM_SEL_AMUXB_DSI (7)
35 0 : #define HSIOM_SEL_ACT_0 (8)
36 0 : #define HSIOM_SEL_ACT_1 (9)
37 0 : #define HSIOM_SEL_ACT_2 (10)
38 0 : #define HSIOM_SEL_ACT_3 (11)
39 0 : #define HSIOM_SEL_DS_0 (12)
40 0 : #define HSIOM_SEL_DS_1 (13)
41 0 : #define HSIOM_SEL_DS_2 (14)
42 0 : #define HSIOM_SEL_DS_3 (15)
43 0 : #define HSIOM_SEL_ACT_4 (16)
44 0 : #define HSIOM_SEL_ACT_5 (17)
45 0 : #define HSIOM_SEL_ACT_6 (18)
46 0 : #define HSIOM_SEL_ACT_7 (19)
47 0 : #define HSIOM_SEL_ACT_8 (20)
48 0 : #define HSIOM_SEL_ACT_9 (21)
49 0 : #define HSIOM_SEL_ACT_10 (22)
50 0 : #define HSIOM_SEL_ACT_11 (23)
51 0 : #define HSIOM_SEL_ACT_12 (24)
52 0 : #define HSIOM_SEL_ACT_13 (25)
53 0 : #define HSIOM_SEL_ACT_14 (26)
54 0 : #define HSIOM_SEL_ACT_15 (27)
55 0 : #define HSIOM_SEL_DS_4 (28)
56 0 : #define HSIOM_SEL_DS_5 (29)
57 0 : #define HSIOM_SEL_DS_6 (30)
58 0 : #define HSIOM_SEL_DS_7 (31)
59 :
60 : /**
61 : * Macro to set drive mode
62 : */
63 1 : #define DT_CAT1_DRIVE_MODE_INFO(peripheral_signal) \
64 : CAT1_PIN_MAP_DRIVE_MODE_##peripheral_signal
65 :
66 : /**
67 : * Macro to set pin control information (from pinctrl node)
68 : */
69 1 : #define DT_CAT1_PINMUX(port, pin, hsiom) \
70 : ((port << SOC_PINMUX_PORT_POS) | \
71 : (pin << SOC_PINMUX_PIN_POS) | \
72 : (hsiom << SOC_PINMUX_HSIOM_FUNC_POS))
73 :
74 : /* Redefine DT GPIO label (Px) to CYHAL port macros (CYHAL_PORT_x) */
75 0 : #define P0 CYHAL_PORT_0
76 0 : #define P1 CYHAL_PORT_1
77 0 : #define P2 CYHAL_PORT_2
78 0 : #define P3 CYHAL_PORT_3
79 0 : #define P4 CYHAL_PORT_4
80 0 : #define P5 CYHAL_PORT_5
81 0 : #define P6 CYHAL_PORT_6
82 0 : #define P7 CYHAL_PORT_7
83 0 : #define P8 CYHAL_PORT_8
84 0 : #define P9 CYHAL_PORT_9
85 0 : #define P10 CYHAL_PORT_10
86 0 : #define P11 CYHAL_PORT_11
87 0 : #define P12 CYHAL_PORT_12
88 0 : #define P13 CYHAL_PORT_13
89 0 : #define P14 CYHAL_PORT_14
90 0 : #define P15 CYHAL_PORT_15
91 0 : #define P16 CYHAL_PORT_16
92 0 : #define P17 CYHAL_PORT_17
93 0 : #define P18 CYHAL_PORT_18
94 0 : #define P19 CYHAL_PORT_19
95 0 : #define P20 CYHAL_PORT_20
96 :
97 : /* Returns CYHAL GPIO from Board device tree GPIO configuration
98 : * CYHAL_GET_GPIO(port_number, pin_number),
99 : * port_number = ((REG ADDR of node) - (REG ADDR of gpio_prt0)) / (REG SIZE of gpio_prt0)
100 : * pin_number = DT_PHA_BY_IDX(node, gpios_prop, 0, pin)
101 : */
102 0 : #define DT_GET_CYHAL_GPIO_FROM_DT_GPIOS(node, gpios_prop) \
103 : CYHAL_GET_GPIO( \
104 : (DT_REG_ADDR_BY_IDX(DT_GPIO_CTLR_BY_IDX(node, gpios_prop, 0), 0) - \
105 : DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 0)) / \
106 : DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 1), \
107 : DT_PHA_BY_IDX(node, gpios_prop, 0, pin) \
108 : )
109 :
110 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_ */
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