LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/pinctrl - imx8qm-pinctrl.h Coverage Total Hit
Test: new.info Lines: 0.0 % 33 0
Test Date: 2025-09-05 16:43:28

            Line data    Source code
       1            0 : /*
       2              :  * Copyright 2023, 2025 NXP
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
       9              : 
      10              : /* values for pad field */
      11            0 : #define SC_P_UART0_RTS_B 23
      12            0 : #define SC_P_UART0_CTS_B 24
      13            0 : #define SC_P_ESAI0_FSR 104
      14            0 : #define SC_P_ESAI0_FST 105
      15            0 : #define SC_P_ESAI0_SCKR 106
      16            0 : #define SC_P_ESAI0_SCKT 107
      17            0 : #define SC_P_ESAI0_TX0 108
      18            0 : #define SC_P_ESAI0_TX1 109
      19            0 : #define SC_P_ESAI0_TX2_RX3 110
      20            0 : #define SC_P_ESAI0_TX3_RX2 111
      21            0 : #define SC_P_ESAI0_TX4_RX1 112
      22            0 : #define SC_P_ESAI0_TX5_RX0 113
      23            0 : #define SC_P_SAI1_RXD 128
      24            0 : #define SC_P_SAI1_TXC 130
      25            0 : #define SC_P_SAI1_TXD 131
      26            0 : #define SC_P_SAI1_TXFS 132
      27              : 
      28              : /* mux values */
      29            0 : #define IMX8QM_DMA_LPUART2_RX_UART0_RTS_B 2 /* UART0_RTS_B ---> DMA_LPUART2_RX */
      30            0 : #define IMX8QM_DMA_LPUART2_TX_UART0_CTS_B 2 /* DMA_LPUART2_TX ---> UART0_CTS_B */
      31            0 : #define IMX8QM_AUD_SAI1_RXD_SAI1_RXD 0 /* AUD_SAI1_RXD <--- SAI1_RXD */
      32            0 : #define IMX8QM_AUD_SAI1_TXC_SAI1_TXC 0 /* AUD_SAI1_TXC <---> SAI1_TXC */
      33            0 : #define IMX8QM_AUD_SAI1_TXD_SAI1_TXD 0 /* AUD_SAI1_TXD ---> SAI1_TXD */
      34            0 : #define IMX8QM_AUD_SAI1_TXFS_SAI1_TXFS 0 /* AUD_SAI1_TXFS <---> SAI1_TXFS */
      35            0 : #define IMX8QM_AUD_ESAI0_FSR_ESAI0_FSR 0
      36            0 : #define IMX8QM_AUD_ESAI0_FST_ESAI0_FST 0
      37            0 : #define IMX8QM_AUD_ESAI0_SCKR_ESAI0_SCKR 0
      38            0 : #define IMX8QM_AUD_ESAI0_SCKT_ESAI0_SCKT 0
      39            0 : #define IMX8QM_AUD_ESAI0_TX0_ESAI_TX0 0
      40            0 : #define IMX8QM_AUD_ESAI0_TX1_ESAI_TX1 0
      41            0 : #define IMX8QM_AUD_ESAI0_TX2_RX3_ESAI0_TX2_RX3 0
      42            0 : #define IMX8QM_AUD_ESAI0_TX3_RX2_ESAI0_TX3_RX2 0
      43            0 : #define IMX8QM_AUD_ESAI0_TX4_RX1_ESAI0_TX4_RX1 0
      44            0 : #define IMX8QM_AUD_ESAI0_TX5_RX0_ESAI0_TX5_RX0 0
      45              : 
      46              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_ */
        

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