Line data    Source code

       1            0 : /*
       2              :  * Copyright (c) 2024-2025 Renesas Electronics Corporation
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_H__
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_H__
       9              : 
      10            0 : #define RA_PORT_NUM_POS  0
      11            0 : #define RA_PORT_NUM_MASK 0xf
      12              : 
      13            0 : #define RA_PIN_NUM_POS  4
      14            0 : #define RA_PIN_NUM_MASK 0xf
      15              : 
      16            0 : #define RA_PSEL_HIZ_JTAG_SWD 0x0
      17            0 : #define RA_PSEL_ADC          0x0
      18            0 : #define RA_PSEL_DAC          0x0
      19            0 : #define RA_PSEL_ACMPHS       0x0
      20            0 : #define RA_PSEL_AGT          0x1
      21            0 : #define RA_PSEL_GPT0         0x2
      22            0 : #define RA_PSEL_GPT1         0x3
      23            0 : #define RA_PSEL_SCI_0        0x4
      24            0 : #define RA_PSEL_SCI_2        0x4
      25            0 : #define RA_PSEL_SCI_4        0x4
      26            0 : #define RA_PSEL_SCI_6        0x4
      27            0 : #define RA_PSEL_SCI_8        0x4
      28            0 : #define RA_PSEL_SCI_1        0x5
      29            0 : #define RA_PSEL_SCI_3        0x5
      30            0 : #define RA_PSEL_SCI_5        0x5
      31            0 : #define RA_PSEL_SCI_7        0x5
      32            0 : #define RA_PSEL_SCI_9        0x5
      33            0 : #define RA_PSEL_SPI          0x6
      34            0 : #define RA_PSEL_I2C          0x7
      35            0 : #define RA_PSEL_I3C          0x7
      36            0 : #define RA_PSEL_CLKOUT_RTC   0x9
      37            0 : #define RA_PSEL_ACMPHS_VCOUT 0x9
      38            0 : #define RA_PSEL_CAC_ADC      0xa
      39            0 : #define RA_PSEL_CAC_DAC      0xa
      40            0 : #define RA_PSEL_BUS          0xb
      41            0 : #define RA_PSEL_CANFD        0x10
      42            0 : #define RA_PSEL_QSPI         0x11
      43            0 : #define RA_PSEL_SSIE         0x12
      44            0 : #define RA_PSEL_USBFS        0x13
      45            0 : #define RA_PSEL_USBHS        0x14
      46            0 : #define RA_PSEL_SDHI         0x15
      47            0 : #define RA_PSEL_ETH_MII      0x16
      48            0 : #define RA_PSEL_ETH_RMII     0x17
      49            0 : #define RA_PSEL_GLCDC        0x19
      50            0 : #define RA_PSEL_OSPI         0x1c
      51            0 : #define RA_PSEL_CTSU         0x0c
      52              : 
      53            0 : #define RA_PSEL_POS  8
      54            0 : #define RA_PSEL_MASK 0x1f
      55              : 
      56            0 : #define RA_MODE_POS  13
      57            0 : #define RA_MODE_MASK 0x1
      58              : 
      59            0 : #define RA_PSEL(psel, port_num, pin_num)                                                           \
      60              :         (1 << RA_MODE_POS | psel << RA_PSEL_POS | port_num << RA_PORT_NUM_POS |                    \
      61              :          pin_num << RA_PIN_NUM_POS)
      62              : 
      63              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_H__ */