Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2024 Renesas Electronics Corporation
       3             :  *
       4             :  * SPDX-License-Identifier: Apache-2.0
       5             :  */
       6             : 
       7             : #ifndef __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
       8             : #define __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
       9             : 
      10           0 : #define RA_PORT_NUM_POS  0
      11           0 : #define RA_PORT_NUM_MASK 0xf
      12             : 
      13           0 : #define RA_PIN_NUM_POS  4
      14           0 : #define RA_PIN_NUM_MASK 0xf
      15             : 
      16           0 : #define RA_PSEL_HIZ_JTAG_SWD 0x0
      17           0 : #define RA_PSEL_AGT          0x1
      18           0 : #define RA_PSEL_GPT0         0x2
      19           0 : #define RA_PSEL_GPT1         0x3
      20           0 : #define RA_PSEL_SCI_0        0x4
      21           0 : #define RA_PSEL_SCI_2        0x4
      22           0 : #define RA_PSEL_SCI_4        0x4
      23           0 : #define RA_PSEL_SCI_6        0x4
      24           0 : #define RA_PSEL_SCI_8        0x4
      25           0 : #define RA_PSEL_SCI_1        0x5
      26           0 : #define RA_PSEL_SCI_3        0x5
      27           0 : #define RA_PSEL_SCI_5        0x5
      28           0 : #define RA_PSEL_SCI_7        0x5
      29           0 : #define RA_PSEL_SCI_9        0x5
      30           0 : #define RA_PSEL_SPI          0x6
      31           0 : #define RA_PSEL_I2C          0x7
      32           0 : #define RA_PSEL_CLKOUT_RTC   0x9
      33           0 : #define RA_PSEL_CAC_ADC      0xa
      34           0 : #define RA_PSEL_BUS          0xb
      35           0 : #define RA_PSEL_CANFD        0x10
      36           0 : #define RA_PSEL_QSPI         0x11
      37           0 : #define RA_PSEL_SSIE         0x12
      38           0 : #define RA_PSEL_USBFS        0x13
      39           0 : #define RA_PSEL_USBHS        0x14
      40           0 : #define RA_PSEL_SDHI         0x15
      41           0 : #define RA_PSEL_ETH_MII      0x16
      42           0 : #define RA_PSEL_ETH_RMII     0x17
      43           0 : #define RA_PSEL_GLCDC        0x19
      44           0 : #define RA_PSEL_OSPI         0x1c
      45           0 : #define RA_PSEL_ADC          0x00
      46             : 
      47           0 : #define RA_PSEL_POS  8
      48           0 : #define RA_PSEL_MASK 0x1f
      49             : 
      50           0 : #define RA_MODE_POS  13
      51           0 : #define RA_MODE_MASK 0x1
      52             : 
      53           0 : #define RA_PSEL(psel, port_num, pin_num)                                                           \
      54             :         (1 << RA_MODE_POS | psel << RA_PSEL_POS | port_num << RA_PORT_NUM_POS |                    \
      55             :          pin_num << RA_PIN_NUM_POS)
      56             : 
      57             : #endif /* __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ */