LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/pinctrl/renesas - pinctrl-rx.h Coverage Total Hit
Test: new.info Lines: 0.0 % 307 0
Test Date: 2025-09-05 16:43:28

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2024 Renesas Electronics Corporation
       3              :  *
       4              :  * SPDX-License-Identifier: Apache-2.0
       5              :  */
       6              : 
       7              : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PINCTRL_RX_H_
       8              : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PINCTRL_RX_H_
       9              : 
      10            0 : #define RX_PORT_NUM_POS  0
      11            0 : #define RX_PORT_NUM_MASK 0x1f
      12              : 
      13            0 : #define RX_PIN_NUM_POS  5
      14            0 : #define RX_PIN_NUM_MASK 0xf
      15              : 
      16            0 : #define RX_PSEL_MASK 0x1f
      17            0 : #define RX_PSEL_POS  9
      18              : 
      19            0 : #define RX_PSEL_RSCI      0xA
      20            0 : #define RX_PSEL_RSCI_TXDB 0xC
      21            0 : #define RX_PSEL_SCI_1     0xA
      22            0 : #define RX_PSEL_SCI_5     0xA
      23            0 : #define RX_PSEL_SCI_6     0xB
      24            0 : #define RX_PSEL_SCI_12    0xC
      25            0 : #define RX_PSEL_TMR       0x5
      26            0 : #define RX_PSEL_POE       0x7
      27            0 : #define RX_PSEL_ADC       0x0
      28              : 
      29              : /* P0nPFS */
      30            0 : #define RX_PSEL_P0nPFS_HIZ    0x0
      31            0 : #define RX_PSEL_P0nPFS_ADTRG0 0x1
      32              : 
      33              : /* P1nPFS */
      34            0 : #define RX_PSEL_P1nPFS_MTIOC0B 0x01
      35            0 : #define RX_PSEL_P1nPFS_MTIOC3A 0x01
      36            0 : #define RX_PSEL_P1nPFS_MTIOC3C 0x01
      37              : 
      38            0 : #define RX_PSEL_P1nPFS_MTCLKA  0x02
      39            0 : #define RX_PSEL_P1nPFS_MTCLKB  0x02
      40            0 : #define RX_PSEL_P1nPFS_MTIOC3B 0x02
      41            0 : #define RX_PSEL_P1nPFS_MTIOC3D 0x02
      42              : 
      43            0 : #define RX_PSEL_P1nPFS_TMCI1 0x5
      44            0 : #define RX_PSEL_P1nPFS_TMO1  0x5
      45            0 : #define RX_PSEL_P1nPFS_TMCI2 0x5
      46            0 : #define RX_PSEL_P1nPFS_TMO2  0x5
      47            0 : #define RX_PSEL_P1nPFS_TMRI2 0x5
      48            0 : #define RX_PSEL_P1nPFS_TMO3  0x5
      49              : 
      50            0 : #define RX_PSEL_P1nPFS_RTCOUT 0x7
      51            0 : #define RX_PSEL_P1nPFS_POE8   0x7
      52              : 
      53            0 : #define RX_PSEL_P1nPFS_ADTRG0 0x9
      54              : 
      55            0 : #define RX_PSEL_P1nPFS_RXD1   0xA
      56            0 : #define RX_PSEL_P1nPFS_SMISO1 0xA
      57            0 : #define RX_PSEL_P1nPFS_SSCL1  0xA
      58            0 : #define RX_PSEL_P1nPFS_TXD1   0xA
      59            0 : #define RX_PSEL_P1nPFS_SMOSI1 0xA
      60            0 : #define RX_PSEL_P1nPFS_SSDA1  0xA
      61              : 
      62            0 : #define RX_PSEL_P1nPFS_CTS1 0xB
      63            0 : #define RX_PSEL_P1nPFS_RTS1 0xB
      64            0 : #define RX_PSEL_P1nPFS_SS1  0xB
      65              : 
      66            0 : #define RX_PSEL_P1nPFS_MOSIA 0xD
      67            0 : #define RX_PSEL_P1nPFS_MISOA 0xD
      68              : 
      69            0 : #define RX_PSEL_P1nPFS_SCL 0xF
      70            0 : #define RX_PSEL_P1nPFS_SDA 0xF
      71              : 
      72            0 : #define RX_PSEL_P1nPFS_TS5 0x19
      73            0 : #define RX_PSEL_P1nPFS_TS6 0x19
      74              : 
      75              : /* P2nPFS */
      76            0 : #define RX_PSEL_P2nPFS_MTIOC1A 0x01
      77            0 : #define RX_PSEL_P2nPFS_MTIOC1B 0x01
      78            0 : #define RX_PSEL_P2nPFS_MTIOC2A 0x01
      79            0 : #define RX_PSEL_P2nPFS_MTIOC2B 0x01
      80            0 : #define RX_PSEL_P2nPFS_MTIOC3B 0x01
      81            0 : #define RX_PSEL_P2nPFS_MTIOC3D 0x01
      82            0 : #define RX_PSEL_P2nPFS_MTIOC4A 0x01
      83            0 : #define RX_PSEL_P2nPFS_MTIOC4C 0x01
      84              : 
      85            0 : #define RX_PSEL_P2nPFS_MTCLKA 0x02
      86            0 : #define RX_PSEL_P2nPFS_MTCLKB 0x02
      87            0 : #define RX_PSEL_P2nPFS_MTCLKC 0x02
      88            0 : #define RX_PSEL_P2nPFS_MTCLKD 0x02
      89              : 
      90            0 : #define RX_PSEL_P2nPFS_TMCI0 0x5
      91            0 : #define RX_PSEL_P2nPFS_TMO0  0x5
      92            0 : #define RX_PSEL_P2nPFS_TMRI0 0x5
      93            0 : #define RX_PSEL_P2nPFS_TMO1  0x5
      94            0 : #define RX_PSEL_P2nPFS_TMRI1 0x5
      95            0 : #define RX_PSEL_P2nPFS_TMCI3 0x5
      96              : 
      97            0 : #define RX_PSEL_P2nPFS_ADTRG0 0x9
      98              : 
      99            0 : #define RX_PSEL_P2nPFS_RXD0   0xA
     100            0 : #define RX_PSEL_P2nPFS_SMISO0 0xA
     101            0 : #define RX_PSEL_P2nPFS_SSCL0  0xA
     102            0 : #define RX_PSEL_P2nPFS_TXD0   0xA
     103            0 : #define RX_PSEL_P2nPFS_SMOSI0 0xA
     104            0 : #define RX_PSEL_P2nPFS_SSDA0  0xA
     105            0 : #define RX_PSEL_P2nPFS_SCK0   0xA
     106            0 : #define RX_PSEL_P2nPFS_TXD1   0xA
     107            0 : #define RX_PSEL_P2nPFS_SMOSI1 0xA
     108            0 : #define RX_PSEL_P2nPFS_SSDA1  0xA
     109            0 : #define RX_PSEL_P2nPFS_SCK1   0xA
     110              : 
     111            0 : #define RX_PSEL_P2nPFS_CTS0 0xB
     112            0 : #define RX_PSEL_P2nPFS_RTS0 0xB
     113            0 : #define RX_PSEL_P2nPFS_SS0  0xB
     114              : 
     115            0 : #define RX_PSEL_P2nPFS_TS3 0x19
     116            0 : #define RX_PSEL_P2nPFS_TS4 0x19
     117              : 
     118              : /* P3nPFS */
     119            0 : #define RX_PSEL_P3nPFS_MTIOC0A 0x01
     120            0 : #define RX_PSEL_P3nPFS_MTIOC0C 0x01
     121            0 : #define RX_PSEL_P3nPFS_MTIOC0D 0x01
     122            0 : #define RX_PSEL_P3nPFS_MTIOC4B 0x01
     123            0 : #define RX_PSEL_P3nPFS_MTIOC4D 0x01
     124              : 
     125            0 : #define RX_PSEL_P3nPFS_TMCI2 0x5
     126            0 : #define RX_PSEL_P3nPFS_TMO3  0x5
     127            0 : #define RX_PSEL_P3nPFS_TMRI3 0x5
     128            0 : #define RX_PSEL_P3nPFS_TMCI3 0x5
     129              : 
     130            0 : #define RX_PSEL_P3nPFS_RTCOUT 0x7
     131            0 : #define RX_PSEL_P3nPFS_POE2   0x7
     132            0 : #define RX_PSEL_P3nPFS_POE3   0x7
     133            0 : #define RX_PSEL_P3nPFS_POE8   0x7
     134              : 
     135            0 : #define RX_PSEL_P3nPFS_RXD1   0xA
     136            0 : #define RX_PSEL_P3nPFS_SMISO1 0xA
     137            0 : #define RX_PSEL_P3nPFS_SSCL1  0xA
     138              : 
     139            0 : #define RX_PSEL_P3nPFS_CTS1   0xB
     140            0 : #define RX_PSEL_P3nPFS_RTS1   0xB
     141            0 : #define RX_PSEL_P3nPFS_SS1    0xB
     142            0 : #define RX_PSEL_P3nPFS_RXD6   0xB
     143            0 : #define RX_PSEL_P3nPFS_SMISO6 0xB
     144            0 : #define RX_PSEL_P3nPFS_SSCL6  0xB
     145            0 : #define RX_PSEL_P3nPFS_TXD6   0xB
     146            0 : #define RX_PSEL_P3nPFS_SMOSI6 0xB
     147            0 : #define RX_PSEL_P3nPFS_SSDA6  0xB
     148            0 : #define RX_PSEL_P3nPFS_SCK6   0xB
     149              : 
     150            0 : #define RX_PSEL_P3nPFS_TS0 0x19
     151            0 : #define RX_PSEL_P3nPFS_TS1 0x19
     152            0 : #define RX_PSEL_P3nPFS_TS2 0x19
     153              : 
     154              : /* P5nPFS */
     155            0 : #define RX_PSEL_P5nPFS_MTIOC4B 0x01
     156            0 : #define RX_PSEL_P5nPFS_MTIOC4D 0x01
     157              : 
     158            0 : #define RX_PSEL_P5nPFS_TMCI1 0x5
     159            0 : #define RX_PSEL_P5nPFS_TMO3  0x5
     160              : 
     161            0 : #define RX_PSEL_P5nPFS_TS11 0x19
     162            0 : #define RX_PSEL_P5nPFS_TS12 0x19
     163              : 
     164            0 : #define RX_PSEL_P5nPFS_PMC0 0x19
     165            0 : #define RX_PSEL_P5nPFS_PMC1 0x19
     166              : 
     167              : /* PAnPFS */
     168            0 : #define RX_PSEL_PAnPFS_MTIOC4A 0x01
     169            0 : #define RX_PSEL_PAnPFS_MTIOC0B 0x01
     170            0 : #define RX_PSEL_PAnPFS_MTIOC0D 0x01
     171            0 : #define RX_PSEL_PAnPFS_MTIOC5U 0x01
     172            0 : #define RX_PSEL_PAnPFS_MTIOC5V 0x01
     173              : 
     174            0 : #define RX_PSEL_PAnPFS_MTCLKA 0x02
     175            0 : #define RX_PSEL_PAnPFS_MTCLKB 0x02
     176            0 : #define RX_PSEL_PAnPFS_MTCLKC 0x02
     177            0 : #define RX_PSEL_PAnPFS_MTCLKD 0x02
     178              : 
     179            0 : #define RX_PSEL_PAnPFS_TMRI0 0x5
     180            0 : #define RX_PSEL_PAnPFS_TMCI3 0x5
     181              : 
     182            0 : #define RX_PSEL_PAnPFS_POE2   0x7
     183            0 : #define RX_PSEL_PAnPFS_CACREF 0x7
     184              : 
     185            0 : #define RX_PSEL_PAnPFS_RXD5   0xA
     186            0 : #define RX_PSEL_PAnPFS_SMISO5 0xA
     187            0 : #define RX_PSEL_PAnPFS_SSCL5  0xA
     188            0 : #define RX_PSEL_PAnPFS_TXD5   0xA
     189            0 : #define RX_PSEL_PAnPFS_SMOSI5 0xA
     190            0 : #define RX_PSEL_PAnPFS_SSDA5  0xA
     191            0 : #define RX_PSEL_PAnPFS_SCK5   0xA
     192              : 
     193            0 : #define RX_PSEL_PAnPFS_CTS5 0xB
     194            0 : #define RX_PSEL_PAnPFS_RTS5 0xB
     195            0 : #define RX_PSEL_PAnPFS_SS5  0xB
     196              : 
     197            0 : #define RX_PSEL_PAnPFS_SSLA0  0xD
     198            0 : #define RX_PSEL_PAnPFS_SSLA1  0xD
     199            0 : #define RX_PSEL_PAnPFS_SSLA2  0xD
     200            0 : #define RX_PSEL_PAnPFS_SSLA3  0xD
     201            0 : #define RX_PSEL_PAnPFS_RSPCKA 0xD
     202            0 : #define RX_PSEL_PAnPFS_MOSIA  0xD
     203            0 : #define RX_PSEL_PAnPFS_MISOA  0xD
     204              : 
     205            0 : #define RX_PSEL_PAnPFS_TS26 0x19
     206            0 : #define RX_PSEL_PAnPFS_TS27 0x19
     207            0 : #define RX_PSEL_PAnPFS_TS28 0x19
     208            0 : #define RX_PSEL_PAnPFS_TS29 0x19
     209            0 : #define RX_PSEL_PAnPFS_TS30 0x19
     210            0 : #define RX_PSEL_PAnPFS_TS31 0x19
     211            0 : #define RX_PSEL_PAnPFS_TS32 0x19
     212              : 
     213              : /* PBnPFS */
     214            0 : #define RX_PSEL_PBnPFS_MTIOC0A 0x01
     215            0 : #define RX_PSEL_PBnPFS_MTIOC0C 0x01
     216            0 : #define RX_PSEL_PBnPFS_MTIOC2A 0x01
     217            0 : #define RX_PSEL_PBnPFS_MTIOC3B 0x01
     218            0 : #define RX_PSEL_PBnPFS_MTIOC3D 0x01
     219            0 : #define RX_PSEL_PBnPFS_MTIOC5W 0x01
     220              : 
     221            0 : #define RX_PSEL_PBnPFS_MTIOC1B 0x02
     222            0 : #define RX_PSEL_PBnPFS_MTIOC4A 0x02
     223            0 : #define RX_PSEL_PBnPFS_MTIOC4C 0x02
     224              : 
     225            0 : #define RX_PSEL_PBnPFS_TMO0  0x5
     226            0 : #define RX_PSEL_PBnPFS_TMRI1 0x5
     227            0 : #define RX_PSEL_PBnPFS_TMCI0 0x5
     228              : 
     229            0 : #define RX_PSEL_PBnPFS_POE1 0x7
     230            0 : #define RX_PSEL_PBnPFS_POE3 0x7
     231              : 
     232            0 : #define RX_PSEL_PBnPFS_RXD9   0xA
     233            0 : #define RX_PSEL_PBnPFS_SMISO9 0xA
     234            0 : #define RX_PSEL_PBnPFS_SSCL9  0xA
     235            0 : #define RX_PSEL_PBnPFS_TXD9   0xA
     236            0 : #define RX_PSEL_PBnPFS_SMOSI9 0xA
     237            0 : #define RX_PSEL_PBnPFS_SSDA9  0xA
     238            0 : #define RX_PSEL_PBnPFS_SCK9   0xA
     239              : 
     240            0 : #define RX_PSEL_PBnPFS_CTS6   0xB
     241            0 : #define RX_PSEL_PBnPFS_RTS6   0xB
     242            0 : #define RX_PSEL_PBnPFS_SS6    0xB
     243            0 : #define RX_PSEL_PBnPFS_CTS9   0xB
     244            0 : #define RX_PSEL_PBnPFS_RTS9   0xB
     245            0 : #define RX_PSEL_PBnPFS_SS9    0xB
     246            0 : #define RX_PSEL_PBnPFS_RXD6   0xB
     247            0 : #define RX_PSEL_PBnPFS_SMISO6 0xB
     248            0 : #define RX_PSEL_PBnPFS_SSCL6  0xB
     249            0 : #define RX_PSEL_PBnPFS_TXD6   0xB
     250            0 : #define RX_PSEL_PBnPFS_SMOSI6 0xB
     251            0 : #define RX_PSEL_PBnPFS_SSDA6  0xB
     252            0 : #define RX_PSEL_PBnPFS_SCK6   0xB
     253              : 
     254            0 : #define RX_PSEL_PBnPFS_RSPCKA 0xD
     255              : 
     256            0 : #define RX_PSEL_PBnPFS_CMPOB1 0x10
     257              : 
     258            0 : #define RX_PSEL_PBnPFS_TS18 0x19
     259            0 : #define RX_PSEL_PBnPFS_TS19 0x19
     260            0 : #define RX_PSEL_PBnPFS_TS20 0x19
     261            0 : #define RX_PSEL_PBnPFS_TS21 0x19
     262            0 : #define RX_PSEL_PBnPFS_TS22 0x19
     263            0 : #define RX_PSEL_PBnPFS_TS23 0x19
     264            0 : #define RX_PSEL_PBnPFS_TS24 0x19
     265            0 : #define RX_PSEL_PBnPFS_TS25 0x19
     266              : 
     267              : /* PCnPFS */
     268            0 : #define RX_PSEL_PCnPFS_MTIOC3A 0x01
     269            0 : #define RX_PSEL_PCnPFS_MTIOC3B 0x01
     270            0 : #define RX_PSEL_PCnPFS_MTIOC3C 0x01
     271            0 : #define RX_PSEL_PCnPFS_MTIOC3D 0x01
     272            0 : #define RX_PSEL_PCnPFS_MTIOC4B 0x01
     273            0 : #define RX_PSEL_PCnPFS_MTIOC4D 0x01
     274              : 
     275            0 : #define RX_PSEL_PCnPFS_MTCLKA 0x02
     276            0 : #define RX_PSEL_PCnPFS_MTCLKB 0x02
     277            0 : #define RX_PSEL_PCnPFS_MTCLKC 0x02
     278            0 : #define RX_PSEL_PCnPFS_MTCLKD 0x02
     279              : 
     280            0 : #define RX_PSEL_PCnPFS_TMCI1 0x5
     281            0 : #define RX_PSEL_PCnPFS_TMO2  0x5
     282            0 : #define RX_PSEL_PCnPFS_TMRI2 0x5
     283            0 : #define RX_PSEL_PCnPFS_TMCI2 0x5
     284              : 
     285            0 : #define RX_PSEL_PCnPFS_POE0   0x7
     286            0 : #define RX_PSEL_PCnPFS_CACREF 0x7
     287              : 
     288            0 : #define RX_PSEL_PCnPFS_RXD5   0xA
     289            0 : #define RX_PSEL_PCnPFS_SMISO5 0xA
     290            0 : #define RX_PSEL_PCnPFS_SSCL5  0xA
     291            0 : #define RX_PSEL_PCnPFS_TXD5   0xA
     292            0 : #define RX_PSEL_PCnPFS_SMOSI5 0xA
     293            0 : #define RX_PSEL_PCnPFS_SSDA5  0xA
     294            0 : #define RX_PSEL_PCnPFS_SCK5   0xA
     295            0 : #define RX_PSEL_PCnPFS_RXD8   0xA
     296            0 : #define RX_PSEL_PCnPFS_SMISO8 0xA
     297            0 : #define RX_PSEL_PCnPFS_SSCL8  0xA
     298            0 : #define RX_PSEL_PCnPFS_TXD8   0xA
     299            0 : #define RX_PSEL_PCnPFS_SMOSI8 0xA
     300            0 : #define RX_PSEL_PCnPFS_SSDA8  0xA
     301            0 : #define RX_PSEL_PCnPFS_SCK8   0xA
     302              : 
     303            0 : #define RX_PSEL_PCnPFS_CTS5 0xB
     304            0 : #define RX_PSEL_PCnPFS_RTS5 0xB
     305            0 : #define RX_PSEL_PCnPFS_SS5  0xB
     306            0 : #define RX_PSEL_PCnPFS_CTS8 0xB
     307            0 : #define RX_PSEL_PCnPFS_RTS8 0xB
     308            0 : #define RX_PSEL_PCnPFS_SS8  0xB
     309              : 
     310            0 : #define RX_PSEL_PCnPFS_SSLA0  0xD
     311            0 : #define RX_PSEL_PCnPFS_SSLA1  0xD
     312            0 : #define RX_PSEL_PCnPFS_SSLA2  0xD
     313            0 : #define RX_PSEL_PCnPFS_SSLA3  0xD
     314            0 : #define RX_PSEL_PCnPFS_RSPCKA 0xD
     315            0 : #define RX_PSEL_PCnPFS_MOSIA  0xD
     316            0 : #define RX_PSEL_PCnPFS_MISOA  0xD
     317              : 
     318            0 : #define RX_PSEL_PCnPFS_TS13  0x19
     319            0 : #define RX_PSEL_PCnPFS_TS14  0x19
     320            0 : #define RX_PSEL_PCnPFS_TS15  0x19
     321            0 : #define RX_PSEL_PCnPFS_TS16  0x19
     322            0 : #define RX_PSEL_PCnPFS_TS17  0x19
     323            0 : #define RX_PSEL_PCnPFS_TSCAP 0x19
     324              : 
     325              : /* PDnPFS */
     326            0 : #define RX_PSEL_PDnPFS_MTIOC4B 0x01
     327            0 : #define RX_PSEL_PDnPFS_MTIOC4D 0x01
     328            0 : #define RX_PSEL_PDnPFS_MTIOC5W 0x01
     329            0 : #define RX_PSEL_PDnPFS_MTIOC5V 0x01
     330            0 : #define RX_PSEL_PDnPFS_MTIOC5U 0x01
     331              : 
     332            0 : #define RX_PSEL_PDnPFS_POE0 0x7
     333            0 : #define RX_PSEL_PDnPFS_POE1 0x7
     334            0 : #define RX_PSEL_PDnPFS_POE2 0x7
     335            0 : #define RX_PSEL_PDnPFS_POE3 0x7
     336            0 : #define RX_PSEL_PDnPFS_POE8 0x7
     337              : 
     338            0 : #define RX_PSEL_PDnPFS_RXD6   0xB
     339            0 : #define RX_PSEL_PDnPFS_SMISO6 0xB
     340            0 : #define RX_PSEL_PDnPFS_SSCL6  0xB
     341            0 : #define RX_PSEL_PDnPFS_TXD6   0xB
     342            0 : #define RX_PSEL_PDnPFS_SMOSI6 0xB
     343            0 : #define RX_PSEL_PDnPFS_SSDA6  0xB
     344            0 : #define RX_PSEL_PDnPFS_SCK6   0xB
     345              : 
     346              : /* PEnPFS */
     347            0 : #define RX_PSEL_PEnPFS_MTIOC4A 0x01
     348            0 : #define RX_PSEL_PEnPFS_MTIOC4B 0x01
     349            0 : #define RX_PSEL_PEnPFS_MTIOC4C 0x01
     350            0 : #define RX_PSEL_PEnPFS_MTIOC4D 0x01
     351              : 
     352            0 : #define RX_PSEL_PEnPFS_MTIOC1A 0x02
     353            0 : #define RX_PSEL_PEnPFS_MTIOC2B 0x02
     354              : 
     355            0 : #define RX_PSEL_PEnPFS_POE8 0x7
     356              : 
     357            0 : #define RX_PSEL_PEnPFS_CLKOUT 0x9
     358              : 
     359            0 : #define RX_PSEL_PEnPFS_RXD12   0xC
     360            0 : #define RX_PSEL_PEnPFS_SMISO12 0xC
     361            0 : #define RX_PSEL_PEnPFS_SSCL12  0xC
     362            0 : #define RX_PSEL_PEnPFS_TXD12   0xC
     363            0 : #define RX_PSEL_PEnPFS_SMOSI12 0xC
     364            0 : #define RX_PSEL_PEnPFS_SSDA12  0xC
     365            0 : #define RX_PSEL_PEnPFS_SCK12   0xC
     366            0 : #define RX_PSEL_PEnPFS_TXDX12  0xC
     367            0 : #define RX_PSEL_PEnPFS_RXDX12  0xC
     368            0 : #define RX_PSEL_PEnPFS_SIOX12  0xC
     369            0 : #define RX_PSEL_PEnPFS_CTS12   0xC
     370            0 : #define RX_PSEL_PEnPFS_RTS12   0xC
     371            0 : #define RX_PSEL_PEnPFS_SS12    0xC
     372              : 
     373            0 : #define RX_PSEL_PEnPFS_CMPOB0 0X10
     374              : 
     375            0 : #define RX_PSEL_PEnPFS_TS33 0X19
     376            0 : #define RX_PSEL_PEnPFS_TS34 0x19
     377            0 : #define RX_PSEL_PEnPFS_TS35 0x19
     378              : 
     379              : /* PHnPFS */
     380            0 : #define RX_PSEL_PHnPFS_TMO0  0x05
     381            0 : #define RX_PSEL_PHnPFS_TMRI0 0x05
     382            0 : #define RX_PSEL_PHnPFS_TMCI0 0x05
     383              : 
     384            0 : #define RX_PSEL_PHnPFS_CACREF 0x7
     385              : 
     386            0 : #define RX_PSEL_PHnPFS_TS7  0x19
     387            0 : #define RX_PSEL_PHnPFS_TS8  0x19
     388            0 : #define RX_PSEL_PHnPFS_TS9  0x19
     389            0 : #define RX_PSEL_PHnPFS_TS10 0x19
     390              : 
     391              : /* PJnPFS */
     392            0 : #define RX_PSEL_PJnPFS_MTIOC3A 0x01
     393            0 : #define RX_PSEL_PJnPFS_MTIOC3C 0x01
     394              : 
     395            0 : #define RX_PSEL_PJnPFS_CTS6 0xB
     396            0 : #define RX_PSEL_PJnPFS_TTS6 0xB
     397            0 : #define RX_PSEL_PJnPFS_SS6  0xB
     398              : 
     399            0 : #define RX_PSEL(psel, port_num, pin_num)                                                           \
     400              :         (psel << RX_PSEL_POS | pin_num << RX_PIN_NUM_POS | port_num << RX_PORT_NUM_POS)
     401              : 
     402              : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SOC_RX_COMMON_H_ */
        

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