Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2024 Renesas Electronics Corporation
       3             :  * SPDX-License-Identifier: Apache-2.0
       4             :  */
       5             : 
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_
       8             : 
       9             : /* Superset list of all possible IO ports. */
      10           0 : #define PORT_00 0x0000 /* IO port 0 */
      11           0 : #define PORT_01 0x1000 /* IO port 1 */
      12           0 : #define PORT_02 0x1100 /* IO port 2 */
      13           0 : #define PORT_03 0x1200 /* IO port 3 */
      14           0 : #define PORT_04 0x1300 /* IO port 4 */
      15           0 : #define PORT_05 0x0100 /* IO port 5 */
      16           0 : #define PORT_06 0x0200 /* IO port 6 */
      17           0 : #define PORT_07 0x1400 /* IO port 7 */
      18           0 : #define PORT_08 0x1500 /* IO port 8 */
      19           0 : #define PORT_09 0x1600 /* IO port 9 */
      20           0 : #define PORT_10 0x1700 /* IO port 10 */
      21           0 : #define PORT_11 0x0300 /* IO port 11 */
      22           0 : #define PORT_12 0x0400 /* IO port 12 */
      23           0 : #define PORT_13 0x0500 /* IO port 13 */
      24           0 : #define PORT_14 0x0600 /* IO port 14 */
      25           0 : #define PORT_15 0x0700 /* IO port 15 */
      26           0 : #define PORT_16 0x0800 /* IO port 16 */
      27           0 : #define PORT_17 0x0900 /* IO port 17 */
      28           0 : #define PORT_18 0x0A00 /* IO port 18 */
      29             : 
      30             : /*
      31             :  * Create the value contain port/pin/function information
      32             :  *
      33             :  * port: port number BSP_IO_PORT_00..BSP_IO_PORT_18
      34             :  * pin: pin number
      35             :  * func: pin function
      36             :  */
      37           0 : #define RZG_PINMUX(port, pin, func) (port | pin | (func << 4))
      38             : 
      39             : /* Special purpose port */
      40           0 : #define BSP_IO_NMI 0xFFFF0000 /* NMI */
      41             : 
      42           0 : #define BSP_IO_TMS_SWDIO 0xFFFF0100 /* TMS_SWDIO */
      43           0 : #define BSP_IO_TDO       0xFFFF0101 /* TDO */
      44             : 
      45           0 : #define BSP_IO_AUDIO_CLK1 0xFFFF0200 /* AUDIO_CLK1 */
      46           0 : #define BSP_IO_AUDIO_CLK2 0xFFFF0201 /* AUDIO_CLK2 */
      47             : 
      48           0 : #define BSP_IO_XSPI_SPCLK   0xFFFF0400 /* XSPI_SPCLK */
      49           0 : #define BSP_IO_XSPI_RESET_N 0xFFFF0401 /* XSPI_RESET_N */
      50           0 : #define BSP_IO_XSPI_WP_N    0xFFFF0402 /* XSPI_WP_N */
      51           0 : #define BSP_IO_XSPI_DS      0xFFFF0403 /* XSPI_DS */
      52           0 : #define BSP_IO_XSPI_CS0_N   0xFFFF0404 /* XSPI_CS0_N */
      53           0 : #define BSP_IO_XSPI_CS1_N   0xFFFF0405 /* XSPI_CS1_N */
      54             : 
      55           0 : #define BSP_IO_XSPI_IO0 0xFFFF0500 /* XSPI_IO0 */
      56           0 : #define BSP_IO_XSPI_IO1 0xFFFF0501 /* XSPI_IO1 */
      57           0 : #define BSP_IO_XSPI_IO2 0xFFFF0502 /* XSPI_IO2 */
      58           0 : #define BSP_IO_XSPI_IO3 0xFFFF0503 /* XSPI_IO3 */
      59           0 : #define BSP_IO_XSPI_IO4 0xFFFF0504 /* XSPI_IO4 */
      60           0 : #define BSP_IO_XSPI_IO5 0xFFFF0505 /* XSPI_IO5 */
      61           0 : #define BSP_IO_XSPI_IO6 0xFFFF0506 /* XSPI_IO6 */
      62           0 : #define BSP_IO_XSPI_IO7 0xFFFF0507 /* XSPI_IO7 */
      63             : 
      64           0 : #define BSP_IO_WDTOVF_PERROUT 0xFFFF0600 /* WDTOVF_PERROUT */
      65             : 
      66           0 : #define BSP_IO_I3C_SDA 0xFFFF0900 /* I3C_SDA */
      67           0 : #define BSP_IO_I3C_SCL 0xFFFF0901 /* I3C_SCL */
      68             : 
      69           0 : #define BSP_IO_SD0_CLK   0xFFFF1000 /* CD0_CLK */
      70           0 : #define BSP_IO_SD0_CMD   0xFFFF1001 /* CD0_CMD */
      71           0 : #define BSP_IO_SD0_RST_N 0xFFFF1002 /* CD0_RST_N */
      72             : 
      73           0 : #define BSP_IO_SD0_DATA0 0xFFFF1100 /* SD0_DATA0 */
      74           0 : #define BSP_IO_SD0_DATA1 0xFFFF1101 /* SD0_DATA1 */
      75           0 : #define BSP_IO_SD0_DATA2 0xFFFF1102 /* SD0_DATA2 */
      76           0 : #define BSP_IO_SD0_DATA3 0xFFFF1103 /* SD0_DATA3 */
      77           0 : #define BSP_IO_SD0_DATA4 0xFFFF1104 /* SD0_DATA4 */
      78           0 : #define BSP_IO_SD0_DATA5 0xFFFF1105 /* SD0_DATA5 */
      79           0 : #define BSP_IO_SD0_DATA6 0xFFFF1106 /* SD0_DATA6 */
      80           0 : #define BSP_IO_SD0_DATA7 0xFFFF1107 /* SD0_DATA7 */
      81             : 
      82           0 : #define BSP_IO_SD1_CLK 0xFFFF1200 /* SD1_CLK */
      83           0 : #define BSP_IO_SD1_CMD 0xFFFF1201 /* SD1_CMD */
      84             : 
      85           0 : #define BSP_IO_SD1_DATA0 0xFFFF1300 /* SD1_DATA0 */
      86           0 : #define BSP_IO_SD1_DATA1 0xFFFF1301 /* SD1_DATA1 */
      87           0 : #define BSP_IO_SD1_DATA2 0xFFFF1302 /* SD1_DATA2 */
      88           0 : #define BSP_IO_SD1_DATA3 0xFFFF1303 /* SD1_DATA3 */
      89             : 
      90             : /*FILNUM*/
      91           0 : #define RZG_FILNUM_4_STAGE  0
      92           0 : #define RZG_FILNUM_8_STAGE  1
      93           0 : #define RZG_FILNUM_12_STAGE 2
      94           0 : #define RZG_FILNUM_16_STAGE 3
      95             : 
      96             : /*FILCLKSEL*/
      97           0 : #define RZG_FILCLKSEL_NOT_DIV   0
      98           0 : #define RZG_FILCLKSEL_DIV_9000  1
      99           0 : #define RZG_FILCLKSEL_DIV_18000 2
     100           0 : #define RZG_FILCLKSEL_DIV_36000 3
     101             : 
     102           0 : #define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
     103             : 
     104             : #endif /*ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_*/