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1 0 : /*
2 : * Copyright (c) 2025 Renesas Electronics Corporation
3 : * SPDX-License-Identifier: Apache-2.0
4 : */
5 :
6 : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_
7 : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_
8 :
9 : /* Superset list of all possible IO ports. */
10 0 : #define PORT_00 0x0000 /* IO port 0 */
11 0 : #define PORT_01 0x0100 /* IO port 1 */
12 0 : #define PORT_02 0x0200 /* IO port 2 */
13 0 : #define PORT_03 0x0300 /* IO port 3 */
14 0 : #define PORT_04 0x0400 /* IO port 4 */
15 0 : #define PORT_05 0x0500 /* IO port 5 */
16 0 : #define PORT_06 0x0600 /* IO port 6 */
17 0 : #define PORT_07 0x0700 /* IO port 7 */
18 0 : #define PORT_08 0x0800 /* IO port 8 */
19 0 : #define PORT_09 0x0900 /* IO port 9 */
20 0 : #define PORT_10 0x0A00 /* IO port 10 */
21 0 : #define PORT_11 0x0B00 /* IO port 11 */
22 0 : #define PORT_12 0x0C00 /* IO port 12 */
23 0 : #define PORT_13 0x0D00 /* IO port 13 */
24 0 : #define PORT_14 0x0E00 /* IO port 14 */
25 0 : #define PORT_15 0x0F00 /* IO port 15 */
26 0 : #define PORT_16 0x1000 /* IO port 16 */
27 0 : #define PORT_17 0x1100 /* IO port 17 */
28 0 : #define PORT_18 0x1200 /* IO port 18 */
29 0 : #define PORT_19 0x1300 /* IO port 19 */
30 0 : #define PORT_20 0x1400 /* IO port 20 */
31 0 : #define PORT_21 0x1500 /* IO port 21 */
32 0 : #define PORT_22 0x1600 /* IO port 22 */
33 0 : #define PORT_23 0x1700 /* IO port 23 */
34 0 : #define PORT_24 0x1800 /* IO port 24 */
35 0 : #define PORT_25 0x1900 /* IO port 25 */
36 0 : #define PORT_26 0x1A00 /* IO port 26 */
37 0 : #define PORT_27 0x1B00 /* IO port 27 */
38 0 : #define PORT_28 0x1C00 /* IO port 28 */
39 0 : #define PORT_29 0x1D00 /* IO port 29 */
40 0 : #define PORT_30 0x1E00 /* IO port 30 */
41 0 : #define PORT_31 0x1F00 /* IO port 31 */
42 0 : #define PORT_32 0x2000 /* IO port 32 */
43 0 : #define PORT_33 0x2100 /* IO port 33 */
44 0 : #define PORT_34 0x2200 /* IO port 34 */
45 0 : #define PORT_35 0x2300 /* IO port 35 */
46 0 : #define PORT_36 0x2400 /* IO port 36 */
47 0 : #define PORT_37 0x2500 /* IO port 37 */
48 0 : #define PORT_38 0x2600 /* IO port 38 */
49 0 : #define PORT_39 0x2700 /* IO port 39 */
50 0 : #define PORT_40 0x2800 /* IO port 40 */
51 0 : #define PORT_41 0x2900 /* IO port 41 */
52 0 : #define PORT_42 0x2A00 /* IO port 42 */
53 0 : #define PORT_43 0x2B00 /* IO port 43 */
54 0 : #define PORT_44 0x2C00 /* IO port 44 */
55 0 : #define PORT_45 0x2D00 /* IO port 45 */
56 0 : #define PORT_46 0x2E00 /* IO port 46 */
57 0 : #define PORT_47 0x2F00 /* IO port 47 */
58 0 : #define PORT_48 0x3000 /* IO port 48 */
59 :
60 : /*
61 : * Create the value contain port/pin/function information
62 : *
63 : * port: port number BSP_IO_PORT_00..BSP_IO_PORT_48
64 : * pin: pin number
65 : * func: pin function
66 : */
67 0 : #define RZV_PINMUX(port, pin, func) (port | pin | (func << 4))
68 :
69 : /* Special purpose port */
70 0 : #define BSP_IO_NMI 0xFFFF0100 /* NMI */
71 :
72 0 : #define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */
73 :
74 0 : #define BSP_IO_TDO 0xFFFF0300 /* TDO */
75 :
76 0 : #define BSP_IO_AUDIO_CLK1 0xFFFF0400 /* AUDIO_CLK1 */
77 0 : #define BSP_IO_AUDIO_CLK2 0xFFFF0401 /* AUDIO_CLK2 */
78 :
79 0 : #define BSP_IO_SD0_CLK 0xFFFF0600 /* SD0_CLK */
80 0 : #define BSP_IO_SD0_CMD 0xFFFF0601 /* SD0_CMD */
81 0 : #define BSP_IO_SD0_RST_N 0xFFFF0602 /* SD0_RST_N */
82 :
83 0 : #define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */
84 0 : #define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */
85 0 : #define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */
86 0 : #define BSP_IO_SD0_DATA3 0xFFFF0703 /* SD0_DATA3 */
87 0 : #define BSP_IO_SD0_DATA4 0xFFFF0704 /* SD0_DATA4 */
88 0 : #define BSP_IO_SD0_DATA5 0xFFFF0705 /* SD0_DATA5 */
89 0 : #define BSP_IO_SD0_DATA6 0xFFFF0706 /* SD0_DATA6 */
90 0 : #define BSP_IO_SD0_DATA7 0xFFFF0707 /* SD0_DATA7 */
91 :
92 0 : #define BSP_IO_SD1_CLK 0xFFFF0800 /* SD1_CLK */
93 0 : #define BSP_IO_SD1_CMD 0xFFFF0801 /* SD1_CMD */
94 :
95 0 : #define BSP_IO_SD1_DATA0 0xFFFF0900 /* SD1_DATA0 */
96 0 : #define BSP_IO_SD1_DATA1 0xFFFF0901 /* SD1_DATA1 */
97 0 : #define BSP_IO_SD1_DATA2 0xFFFF0902 /* SD1_DATA2 */
98 0 : #define BSP_IO_SD1_DATA3 0xFFFF0903 /* SD1_DATA3 */
99 :
100 0 : #define BSP_IO_QSPI0_SPCLK 0xFFFF0A00 /* QSPI0_SPCLK */
101 0 : #define BSP_IO_QSPI0_IO0 0xFFFF0A01 /* QSPI0_IO0 */
102 0 : #define BSP_IO_QSPI0_IO1 0xFFFF0A02 /* QSPI0_IO1 */
103 0 : #define BSP_IO_QSPI0_IO2 0xFFFF0A03 /* QSPI0_IO2 */
104 0 : #define BSP_IO_QSPI0_IO3 0xFFFF0A04 /* QSPI0_IO3 */
105 0 : #define BSP_IO_QSPI0_SSL 0xFFFF0A05 /* QSPI0_SSL */
106 :
107 0 : #define BSP_IO_QSPI1_SPCLK 0xFFFF0B00 /* QSPI1_SPCLK */
108 0 : #define BSP_IO_QSPI1_IO0 0xFFFF0B01 /* QSPI1_IO0 */
109 0 : #define BSP_IO_QSPI1_IO1 0xFFFF0B02 /* QSPI1_IO1 */
110 0 : #define BSP_IO_QSPI1_IO2 0xFFFF0B03 /* QSPI1_IO2 */
111 0 : #define BSP_IO_QSPI1_IO3 0xFFFF0B04 /* QSPI1_IO3 */
112 0 : #define BSP_IO_QSPI1_SSL 0xFFFF0B05 /* QSPI1_SSL */
113 :
114 0 : #define BSP_IO_QSPI_RESET_N 0xFFFF0C00 /* QSPI_RESET_N */
115 0 : #define BSP_IO_QSPI_WP_N 0xFFFF0C01 /* QSPI_WP_N */
116 0 : #define BSP_IO_QSPI_INT_N 0xFFFF0C02 /* QSPI_INT_N */
117 :
118 0 : #define BSP_IO_WDTOVF_PERROUT_N 0xFFFF0D00 /* WDTOVF_PERROUT_N */
119 :
120 0 : #define BSP_IO_RIIC0_SDA 0xFFFF0E00 /* RIIC0_SDA */
121 0 : #define BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */
122 0 : #define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */
123 0 : #define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */
124 :
125 : /* FILNUM */
126 0 : #define RZV_FILNUM_4_STAGE 0
127 0 : #define RZV_FILNUM_8_STAGE 1
128 0 : #define RZV_FILNUM_12_STAGE 2
129 0 : #define RZV_FILNUM_16_STAGE 3
130 :
131 : /* FILCLKSEL */
132 0 : #define RZV_FILCLKSEL_NOT_DIV 0
133 0 : #define RZV_FILCLKSEL_DIV_9000 1
134 0 : #define RZV_FILCLKSEL_DIV_18000 2
135 0 : #define RZV_FILCLKSEL_DIV_36000 3
136 :
137 0 : #define RZV_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
138 :
139 : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_ */
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