Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Core Devices LLC
3 : * SPDX-License-Identifier: Apache-2.0
4 : */
5 :
6 : #ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SF32LB_COMMON_PINCTRL_H_
7 : #define _INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SF32LB_COMMON_PINCTRL_H_
8 :
9 0 : #define SF32LB_FSEL_POS 0U
10 0 : #define SF32LB_FSEL_MSK 0x0000000FU
11 0 : #define SF32LB_PORT_POS 12U
12 0 : #define SF32LB_PORT_MSK 0x00003000U
13 0 : #define SF32LB_PAD_POS 14U
14 0 : #define SF32LB_PAD_MSK 0x003FC000U
15 0 : #define SF32LB_PINR_FIELD_POS 22U
16 0 : #define SF32LB_PINR_FIELD_MSK 0x00C00000U
17 0 : #define SF32LB_PINR_OFFSET_POS 24U
18 0 : #define SF32LB_PINR_OFFSET_MSK 0xFF000000U
19 :
20 : /**
21 : * @brief Pin configuration bit field.
22 : *
23 : * Bitmap:
24 : * - 0-10: Configuration bits (function select, pull, drive strength, etc.)
25 : * - 11: Reserved
26 : * - 12-13: Port (SA, PA, ...)
27 : * - 14-21: Pad (0-128)
28 : * - 22-23: PINR register field (0-3)
29 : * - 24:31: PINR register offset (1-255, 0=not used)
30 : *
31 : * @param port Port
32 : * @param pad Pad
33 : * @param fsel Function select
34 : * @param pinr_offset PINR register offset
35 : * @param pinr_field PINR register field
36 : */
37 1 : #define SF32LB_PINMUX(port, pad, fsel, pinr_offset, pinr_field) \
38 : ((((pinr_offset) << SF32LB_PINR_OFFSET_POS) & SF32LB_PINR_OFFSET_MSK) | \
39 : (((pinr_field) << SF32LB_PINR_FIELD_POS) & SF32LB_PINR_FIELD_MSK) | \
40 : (((SF32LB_PORT_##port) << SF32LB_PORT_POS) & SF32LB_PORT_MSK) | \
41 : (((pad) << SF32LB_PAD_POS) & SF32LB_PAD_MSK) | \
42 : (((fsel) << SF32LB_FSEL_POS) & SF32LB_FSEL_MSK))
43 :
44 : #endif /* _INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SF32LB_COMMON_PINCTRL_H_ */
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