Line data    Source code

       1           0 : /*
       2             :  * Copyright (c) 2024 Silicon Labs
       3             :  * SPDX-License-Identifier: Apache-2.0
       4             :  */
       5             : 
       6             : #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
       7             : #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
       8             : 
       9             : #include <zephyr/dt-bindings/dt-util.h>
      10             : 
      11             : /*
      12             :  * Silabs Series 2 DBUS configuration is encoded in a 32-bit bitfield organized as follows:
      13             :  *
      14             :  * 31..29: Reserved
      15             :  * 28..24: Route register offset in words from peripheral config (offset of <fun>ROUTE
      16             :  *         register in GPIO_<periph>ROUTE_TypeDef)
      17             :  * 23..19: Enable bit (offset into ROUTEEN register for given function)
      18             :  * 18    : Enable bit presence (some inputs are auto-enabled)
      19             :  * 17..8 : Peripheral config offset in words from DBUS base within GPIO (offset of <periph>ROUTE[n]
      20             :  *         register in GPIO_TypeDef minus offset of first route register [DBGROUTEPEN, 0x440])
      21             :  *  7..4 : GPIO pin
      22             :  *  3..0 : GPIO port
      23             :  */
      24             : 
      25           0 : #define SILABS_PINCTRL_GPIO_PORT_MASK   0x0000000FUL
      26           0 : #define SILABS_PINCTRL_GPIO_PIN_MASK    0x000000F0UL
      27           0 : #define SILABS_PINCTRL_PERIPH_BASE_MASK 0x0003FF00UL
      28           0 : #define SILABS_PINCTRL_HAVE_EN_MASK     0x00040000UL
      29           0 : #define SILABS_PINCTRL_EN_BIT_MASK      0x00F80000UL
      30           0 : #define SILABS_PINCTRL_ROUTE_MASK       0x1F000000UL
      31             : 
      32           0 : #define SILABS_DBUS(port, pin, periph_base, en_present, en_bit, route)                             \
      33             :         (FIELD_PREP(SILABS_PINCTRL_GPIO_PORT_MASK, port) |                                         \
      34             :          FIELD_PREP(SILABS_PINCTRL_GPIO_PIN_MASK, pin) |                                           \
      35             :          FIELD_PREP(SILABS_PINCTRL_PERIPH_BASE_MASK, periph_base) |                                \
      36             :          FIELD_PREP(SILABS_PINCTRL_HAVE_EN_MASK, en_present) |                                     \
      37             :          FIELD_PREP(SILABS_PINCTRL_EN_BIT_MASK, en_bit) |                                          \
      38             :          FIELD_PREP(SILABS_PINCTRL_ROUTE_MASK, route))
      39             : 
      40             : #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_ */