Line data Source code
1 0 : /*
2 : * Copyright (c) 2024 Silicon Laboratories Inc.
3 : * SPDX-License-Identifier: Apache-2.0
4 : */
5 :
6 : #ifndef INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_SIWX91X_PINCTRL_H_
7 : #define INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_SIWX91X_PINCTRL_H_
8 :
9 : #include <zephyr/dt-bindings/pinctrl/silabs-pinctrl-siwx91x.h>
10 :
11 : /* clang-format off */
12 :
13 0 : #define AGPIO_ULP0 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 0)
14 0 : #define AGPIO_ULP1 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 1)
15 0 : #define AGPIO_ULP2 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 2)
16 0 : #define AGPIO_ULP4 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 4)
17 0 : #define AGPIO_ULP5 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 5)
18 0 : #define AGPIO_ULP6 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 6)
19 0 : #define AGPIO_ULP7 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 7)
20 0 : #define AGPIO_ULP8 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 8)
21 0 : #define AGPIO_ULP9 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 9)
22 0 : #define AGPIO_ULP10 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 10)
23 0 : #define AGPIO_ULP11 SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 11)
24 :
25 0 : #define ADC_TOPGPIO_HP25 SIWX91X_GPIO(14, 0xFF, 0, 1, 9, 0)
26 0 : #define ADC_TOPGPIO_HP26 SIWX91X_GPIO(14, 0xFF, 0, 1, 10, 0)
27 0 : #define ADC_TOPGPIO_HP27 SIWX91X_GPIO(14, 0xFF, 0, 1, 11, 0)
28 0 : #define ADC_TOPGPIO_HP28 SIWX91X_GPIO(14, 0xFF, 0, 1, 12, 0)
29 0 : #define ADC_TOPGPIO_HP29 SIWX91X_GPIO(14, 0xFF, 0, 1, 13, 0)
30 0 : #define ADC_TOPGPIO_HP30 SIWX91X_GPIO(14, 0xFF, 0, 1, 14, 0)
31 :
32 0 : #define AUXULP_TRIG0_HP11 SIWX91X_GPIO(9, 5, 6, 0, 11, 5)
33 0 : #define AUXULP_TRIG0_HP30 SIWX91X_GPIO(11, 5, 0, 1, 14, 11)
34 0 : #define AUXULP_TRIG0_HP49 SIWX91X_GPIO(9, 5, 13, 3, 1, 11)
35 0 : #define AUXULP_TRIG0_ULP5 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 5)
36 0 : #define AUXULP_TRIG0_ULP6 SIWX91X_GPIO(0xFF, 10, 0xFF, 4, 0, 6)
37 0 : #define AUXULP_TRIG0_ULP11 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 11)
38 0 : #define AUXULP_TRIG1_ULP4 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 4)
39 0 : #define AUXULP_TRIG1_ULP7 SIWX91X_GPIO(0xFF, 10, 0xFF, 4, 0, 7)
40 :
41 0 : #define CLK_I2SPLL_HP27 SIWX91X_GPIO(12, 0xFF, 0, 1, 11, 0)
42 0 : #define CLK_I2SPLL_HP48 SIWX91X_GPIO(10, 0xFF, 12, 3, 0, 0)
43 0 : #define CLK_I2SPLL_HP54 SIWX91X_GPIO(10, 0xFF, 18, 3, 6, 0)
44 0 : #define CLK_INTFPLL_HP26 SIWX91X_GPIO(12, 0xFF, 0, 1, 10, 0)
45 0 : #define CLK_INTFPLL_HP47 SIWX91X_GPIO(10, 0xFF, 11, 2, 15, 0)
46 0 : #define CLK_INTFPLL_HP53 SIWX91X_GPIO(10, 0xFF, 17, 3, 5, 0)
47 0 : #define CLK_MCUOUT_HP11 SIWX91X_GPIO(12, 0xFF, 6, 0, 11, 0)
48 0 : #define CLK_MEMSREF_HP50 SIWX91X_GPIO(10, 0xFF, 14, 3, 2, 0)
49 0 : #define CLK_MEMSREF_HP56 SIWX91X_GPIO(10, 0xFF, 20, 3, 8, 0)
50 0 : #define CLK_OUT_HP12 SIWX91X_GPIO(8, 0xFF, 7, 0, 12, 0)
51 0 : #define CLK_OUT_HP15 SIWX91X_GPIO(8, 0xFF, 8, 0, 15, 0)
52 0 : #define CLK_PLLTESTMODE_HP51 SIWX91X_GPIO(10, 0xFF, 15, 3, 3, 0)
53 0 : #define CLK_SOCPLL_HP25 SIWX91X_GPIO(12, 0xFF, 0, 1, 9, 0)
54 0 : #define CLK_SOCPLL_HP46 SIWX91X_GPIO(10, 0xFF, 10, 2, 14, 0)
55 0 : #define CLK_SOCPLL_HP52 SIWX91X_GPIO(10, 0xFF, 16, 3, 4, 0)
56 0 : #define CLK_XTALONIN_HP28 SIWX91X_GPIO(12, 0xFF, 0, 1, 12, 0)
57 0 : #define CLK_XTALONIN_HP57 SIWX91X_GPIO(10, 0xFF, 21, 3, 9, 0)
58 :
59 0 : #define COMP1_OUT_HP8 SIWX91X_GPIO(9, 5, 3, 0, 8, 2)
60 0 : #define COMP1_OUT_HP28 SIWX91X_GPIO(11, 5, 0, 1, 12, 9)
61 0 : #define COMP1_OUT_HP47 SIWX91X_GPIO(9, 5, 11, 2, 15, 9)
62 0 : #define COMP1_OUT_ULP2 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 2)
63 0 : #define COMP1_OUT_ULP6 SIWX91X_GPIO(0xFF, 9, 0xFF, 4, 0, 6)
64 0 : #define COMP2_OUT_ULP7 SIWX91X_GPIO(0xFF, 9, 0xFF, 4, 0, 7)
65 :
66 0 : #define GSPI_CLK_HP8 SIWX91X_GPIO(4, 0xFF, 3, 0, 8, 0)
67 0 : #define GSPI_CLK_HP25 SIWX91X_GPIO(4, 0xFF, 0, 1, 9, 0)
68 0 : #define GSPI_CLK_HP46 SIWX91X_GPIO(4, 0xFF, 10, 2, 14, 0)
69 0 : #define GSPI_CLK_HP52 SIWX91X_GPIO(4, 0xFF, 16, 3, 4, 0)
70 0 : #define GSPI_CS0_HP9 SIWX91X_GPIO(4, 0xFF, 4, 0, 9, 0)
71 0 : #define GSPI_CS0_HP28 SIWX91X_GPIO(4, 0xFF, 0, 1, 12, 0)
72 0 : #define GSPI_CS0_HP49 SIWX91X_GPIO(4, 0xFF, 13, 3, 1, 0)
73 0 : #define GSPI_CS0_HP53 SIWX91X_GPIO(4, 0xFF, 17, 3, 5, 0)
74 0 : #define GSPI_CS1_HP10 SIWX91X_GPIO(4, 0xFF, 5, 0, 10, 0)
75 0 : #define GSPI_CS1_HP29 SIWX91X_GPIO(4, 0xFF, 0, 1, 13, 0)
76 0 : #define GSPI_CS1_HP50 SIWX91X_GPIO(4, 0xFF, 14, 3, 2, 0)
77 0 : #define GSPI_CS1_HP54 SIWX91X_GPIO(4, 0xFF, 18, 3, 6, 0)
78 0 : #define GSPI_CS2_HP15 SIWX91X_GPIO(4, 0xFF, 8, 0, 15, 0)
79 0 : #define GSPI_CS2_HP30 SIWX91X_GPIO(4, 0xFF, 0, 1, 14, 0)
80 0 : #define GSPI_CS2_HP51 SIWX91X_GPIO(4, 0xFF, 15, 3, 3, 0)
81 0 : #define GSPI_CS2_HP55 SIWX91X_GPIO(4, 0xFF, 19, 3, 7, 0)
82 0 : #define GSPI_MISO_HP11 SIWX91X_GPIO(4, 0xFF, 6, 0, 11, 0)
83 0 : #define GSPI_MISO_HP26 SIWX91X_GPIO(4, 0xFF, 0, 1, 10, 0)
84 0 : #define GSPI_MISO_HP47 SIWX91X_GPIO(4, 0xFF, 11, 2, 15, 0)
85 0 : #define GSPI_MISO_HP56 SIWX91X_GPIO(4, 0xFF, 20, 3, 8, 0)
86 0 : #define GSPI_MOSI_HP6 SIWX91X_GPIO(12, 0xFF, 1, 0, 6, 0)
87 0 : #define GSPI_MOSI_HP12 SIWX91X_GPIO(4, 0xFF, 7, 0, 12, 0)
88 0 : #define GSPI_MOSI_HP27 SIWX91X_GPIO(4, 0xFF, 0, 1, 11, 0)
89 0 : #define GSPI_MOSI_HP48 SIWX91X_GPIO(4, 0xFF, 12, 3, 0, 0)
90 0 : #define GSPI_MOSI_HP57 SIWX91X_GPIO(4, 0xFF, 21, 3, 9, 0)
91 :
92 0 : #define I2C0_SCL_HP7 SIWX91X_GPIO(4, 0xFF, 2, 0, 7, 0)
93 0 : #define I2C0_SCL_HP32 SIWX91X_GPIO(11, 0xFF, 9, 2, 0, 0)
94 0 : #define I2C0_SCL_ULP1 SIWX91X_GPIO(4, 6, 23, 4, 1, 1)
95 0 : #define I2C0_SCL_ULP2 SIWX91X_GPIO(4, 6, 24, 4, 2, 2)
96 0 : #define I2C0_SCL_ULP11 SIWX91X_GPIO(4, 6, 33, 4, 11, 11)
97 0 : #define I2C0_SDA_HP6 SIWX91X_GPIO(4, 0xFF, 1, 0, 6, 0)
98 0 : #define I2C0_SDA_HP31 SIWX91X_GPIO(11, 0xFF, 9, 1, 15, 0)
99 0 : #define I2C0_SDA_ULP0 SIWX91X_GPIO(4, 6, 22, 4, 0, 0)
100 0 : #define I2C0_SDA_ULP3 SIWX91X_GPIO(4, 6, 25, 4, 3, 3)
101 0 : #define I2C0_SDA_ULP10 SIWX91X_GPIO(4, 6, 32, 4, 10, 10)
102 :
103 0 : #define I2C1_SCL_HP6 SIWX91X_GPIO(5, 0xFF, 1, 0, 6, 0)
104 0 : #define I2C1_SCL_HP29 SIWX91X_GPIO(5, 0xFF, 0, 1, 13, 0)
105 0 : #define I2C1_SCL_HP33 SIWX91X_GPIO(11, 0xFF, 9, 2, 1, 0)
106 0 : #define I2C1_SCL_HP50 SIWX91X_GPIO(5, 0xFF, 14, 3, 2, 0)
107 0 : #define I2C1_SCL_HP54 SIWX91X_GPIO(5, 0xFF, 18, 3, 6, 0)
108 0 : #define I2C1_SCL_ULP0 SIWX91X_GPIO(5, 6, 22, 4, 0, 0)
109 0 : #define I2C1_SCL_ULP2 SIWX91X_GPIO(5, 6, 24, 4, 2, 2)
110 0 : #define I2C1_SCL_ULP6 SIWX91X_GPIO(5, 6, 28, 4, 6, 6)
111 0 : #define I2C1_SDA_HP7 SIWX91X_GPIO(5, 0xFF, 2, 0, 7, 0)
112 0 : #define I2C1_SDA_HP30 SIWX91X_GPIO(5, 0xFF, 0, 1, 14, 0)
113 0 : #define I2C1_SDA_HP34 SIWX91X_GPIO(11, 0xFF, 9, 2, 2, 0)
114 0 : #define I2C1_SDA_HP51 SIWX91X_GPIO(5, 0xFF, 15, 3, 3, 0)
115 0 : #define I2C1_SDA_HP55 SIWX91X_GPIO(5, 0xFF, 19, 3, 7, 0)
116 0 : #define I2C1_SDA_ULP1 SIWX91X_GPIO(5, 6, 23, 4, 1, 1)
117 0 : #define I2C1_SDA_ULP3 SIWX91X_GPIO(5, 6, 25, 4, 3, 3)
118 0 : #define I2C1_SDA_ULP7 SIWX91X_GPIO(5, 6, 29, 4, 7, 7)
119 :
120 0 : #define I2S0_CLK_HP8 SIWX91X_GPIO(7, 0xFF, 3, 0, 8, 0)
121 0 : #define I2S0_CLK_HP25 SIWX91X_GPIO(7, 0xFF, 0, 1, 9, 0)
122 0 : #define I2S0_CLK_HP46 SIWX91X_GPIO(7, 0xFF, 10, 2, 14, 0)
123 0 : #define I2S0_CLK_HP52 SIWX91X_GPIO(7, 0xFF, 16, 3, 4, 0)
124 0 : #define I2S0_DIN0_HP10 SIWX91X_GPIO(7, 0xFF, 5, 0, 10, 0)
125 0 : #define I2S0_DIN0_HP27 SIWX91X_GPIO(7, 0xFF, 0, 1, 11, 0)
126 0 : #define I2S0_DIN0_HP48 SIWX91X_GPIO(7, 0xFF, 12, 3, 0, 0)
127 0 : #define I2S0_DIN0_HP56 SIWX91X_GPIO(7, 0xFF, 20, 3, 8, 0)
128 0 : #define I2S0_DIN1_HP6 SIWX91X_GPIO(7, 0xFF, 1, 0, 6, 0)
129 0 : #define I2S0_DIN1_HP29 SIWX91X_GPIO(7, 0xFF, 0, 1, 13, 0)
130 0 : #define I2S0_DIN1_HP50 SIWX91X_GPIO(7, 0xFF, 14, 3, 2, 0)
131 0 : #define I2S0_DIN1_HP54 SIWX91X_GPIO(7, 0xFF, 18, 3, 6, 0)
132 0 : #define I2S0_DOUT0_HP11 SIWX91X_GPIO(7, 0xFF, 6, 0, 11, 0)
133 0 : #define I2S0_DOUT0_HP28 SIWX91X_GPIO(7, 0xFF, 0, 1, 12, 0)
134 0 : #define I2S0_DOUT0_HP49 SIWX91X_GPIO(7, 0xFF, 13, 3, 1, 0)
135 0 : #define I2S0_DOUT0_HP57 SIWX91X_GPIO(7, 0xFF, 21, 3, 9, 0)
136 0 : #define I2S0_DOUT1_HP7 SIWX91X_GPIO(7, 0xFF, 2, 0, 7, 0)
137 0 : #define I2S0_DOUT1_HP29 SIWX91X_GPIO(7, 0xFF, 0, 1, 14, 0)
138 0 : #define I2S0_DOUT1_HP51 SIWX91X_GPIO(7, 0xFF, 15, 3, 3, 0)
139 0 : #define I2S0_DOUT1_HP55 SIWX91X_GPIO(7, 0xFF, 19, 3, 7, 0)
140 0 : #define I2S0_WS_HP9 SIWX91X_GPIO(7, 0xFF, 4, 0, 9, 0)
141 0 : #define I2S0_WS_HP26 SIWX91X_GPIO(7, 0xFF, 0, 1, 10, 0)
142 0 : #define I2S0_WS_HP47 SIWX91X_GPIO(7, 0xFF, 11, 2, 15, 0)
143 0 : #define I2S0_WS_HP53 SIWX91X_GPIO(7, 0xFF, 17, 3, 5, 0)
144 :
145 0 : #define IR_INPUT_HP15 SIWX91X_GPIO(9, 1, 8, 0, 15, 7)
146 0 : #define IR_INPUT_HP26 SIWX91X_GPIO(11, 1, 0, 1, 10, 7)
147 0 : #define IR_INPUT_HP29 SIWX91X_GPIO(11, 4, 0, 1, 13, 10)
148 0 : #define IR_INPUT_HP48 SIWX91X_GPIO(9, 4, 12, 3, 0, 10)
149 0 : #define IR_INPUT_ULP4 SIWX91X_GPIO(0xFF, 10, 0xFF, 4, 0, 4)
150 0 : #define IR_INPUT_ULP7 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 7)
151 0 : #define IR_INPUT_ULP10 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 10)
152 0 : #define IR_OUTPUT_HP11 SIWX91X_GPIO(9, 1, 6, 0, 11, 5)
153 0 : #define IR_OUTPUT_ULP5 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 5)
154 :
155 0 : #define PMU_TEST1_HP6 SIWX91X_GPIO(8, 0xFF, 1, 0, 6, 0)
156 0 : #define PMU_TEST1_HP29 SIWX91X_GPIO(8, 0xFF, 0, 1, 13, 0)
157 0 : #define PMU_TEST1_HP30 SIWX91X_GPIO(12, 0xFF, 0, 1, 14, 0)
158 0 : #define PMU_TEST1_ULP0 SIWX91X_GPIO(13, 6, 22, 4, 0, 0)
159 0 : #define PMU_TEST1_ULP2 SIWX91X_GPIO(10, 6, 24, 4, 2, 2)
160 0 : #define PMU_TEST1_ULP6 SIWX91X_GPIO(12, 6, 28, 4, 6, 6)
161 0 : #define PMU_TEST1_ULP10 SIWX91X_GPIO(10, 6, 32, 4, 10, 10)
162 0 : #define PMU_TEST2_HP7 SIWX91X_GPIO(8, 0xFF, 2, 0, 7, 0)
163 0 : #define PMU_TEST2_HP30 SIWX91X_GPIO(8, 0xFF, 0, 1, 14, 0)
164 0 : #define PMU_TEST2_ULP1 SIWX91X_GPIO(13, 6, 23, 4, 1, 1)
165 0 : #define PMU_TEST2_ULP3 SIWX91X_GPIO(10, 6, 25, 4, 3, 3)
166 0 : #define PMU_TEST2_ULP7 SIWX91X_GPIO(12, 6, 29, 4, 7, 7)
167 0 : #define PMU_TEST2_ULP11 SIWX91X_GPIO(10, 6, 33, 4, 11, 11)
168 :
169 0 : #define PSRAM_CLK_HP46 SIWX91X_GPIO(11, 0xFF, 10, 2, 14, 0)
170 0 : #define PSRAM_CLK_HP52 SIWX91X_GPIO(12, 0xFF, 16, 3, 4, 0)
171 0 : #define PSRAM_CSN0_HP49 SIWX91X_GPIO(11, 0xFF, 13, 3, 1, 0)
172 0 : #define PSRAM_CSN0_HP55 SIWX91X_GPIO(12, 0xFF, 19, 3, 7, 0)
173 0 : #define PSRAM_CSN1_HP53 SIWX91X_GPIO(11, 0xFF, 17, 3, 5, 0)
174 0 : #define PSRAM_D0_HP47 SIWX91X_GPIO(11, 0xFF, 11, 2, 15, 0)
175 0 : #define PSRAM_D0_HP53 SIWX91X_GPIO(12, 0xFF, 17, 3, 5, 0)
176 0 : #define PSRAM_D1_HP48 SIWX91X_GPIO(11, 0xFF, 12, 3, 0, 0)
177 0 : #define PSRAM_D1_HP54 SIWX91X_GPIO(12, 0xFF, 18, 3, 6, 0)
178 0 : #define PSRAM_D2_HP50 SIWX91X_GPIO(11, 0xFF, 14, 3, 2, 0)
179 0 : #define PSRAM_D2_HP56 SIWX91X_GPIO(12, 0xFF, 20, 3, 8, 0)
180 0 : #define PSRAM_D3_HP51 SIWX91X_GPIO(11, 0xFF, 15, 3, 3, 0)
181 0 : #define PSRAM_D3_HP57 SIWX91X_GPIO(12, 0xFF, 21, 3, 9, 0)
182 0 : #define PSRAM_D4_HP54 SIWX91X_GPIO(11, 0xFF, 18, 3, 6, 0)
183 0 : #define PSRAM_D5_HP55 SIWX91X_GPIO(11, 0xFF, 19, 3, 7, 0)
184 0 : #define PSRAM_D6_HP56 SIWX91X_GPIO(11, 0xFF, 20, 3, 8, 0)
185 0 : #define PSRAM_D7_HP57 SIWX91X_GPIO(11, 0xFF, 21, 3, 9, 0)
186 :
187 0 : #define PWM_0H_HP7 SIWX91X_GPIO(10, 0xFF, 2, 0, 7, 0)
188 0 : #define PWM_0H_ULP1 SIWX91X_GPIO(12, 6, 23, 4, 1, 1)
189 0 : #define PWM_0L_HP6 SIWX91X_GPIO(10, 0xFF, 1, 0, 6, 0)
190 0 : #define PWM_0L_ULP0 SIWX91X_GPIO(12, 6, 22, 4, 0, 0)
191 0 : #define PWM_1H_HP9 SIWX91X_GPIO(10, 0xFF, 4, 0, 9, 0)
192 0 : #define PWM_1H_ULP3 SIWX91X_GPIO(8, 6, 25, 4, 3, 3)
193 0 : #define PWM_1H_ULP5 SIWX91X_GPIO(12, 6, 27, 4, 5, 5)
194 0 : #define PWM_1L_HP8 SIWX91X_GPIO(10, 0xFF, 3, 0, 8, 0)
195 0 : #define PWM_1L_ULP2 SIWX91X_GPIO(8, 6, 24, 4, 2, 2)
196 0 : #define PWM_1L_ULP4 SIWX91X_GPIO(12, 6, 26, 4, 4, 4)
197 0 : #define PWM_2H_HP11 SIWX91X_GPIO(10, 0xFF, 6, 0, 11, 0)
198 0 : #define PWM_2H_ULP5 SIWX91X_GPIO(8, 6, 27, 4, 5, 5)
199 0 : #define PWM_2L_HP10 SIWX91X_GPIO(10, 0xFF, 5, 0, 10, 0)
200 0 : #define PWM_2L_ULP4 SIWX91X_GPIO(8, 6, 26, 4, 4, 4)
201 0 : #define PWM_3H_HP15 SIWX91X_GPIO(10, 0xFF, 8, 0, 15, 0)
202 0 : #define PWM_3H_ULP7 SIWX91X_GPIO(8, 6, 29, 4, 7, 7)
203 0 : #define PWM_3L_HP12 SIWX91X_GPIO(10, 0xFF, 7, 0, 12, 0)
204 0 : #define PWM_3L_ULP6 SIWX91X_GPIO(8, 6, 28, 4, 6, 6)
205 0 : #define PWM_EXTTRIG0_HP27 SIWX91X_GPIO(10, 0xFF, 0, 1, 11, 0)
206 0 : #define PWM_EXTTRIG0_HP51 SIWX91X_GPIO(8, 0xFF, 15, 3, 3, 0)
207 0 : #define PWM_EXTTRIG0_ULP6 SIWX91X_GPIO(10, 6, 28, 4, 6, 6)
208 0 : #define PWM_EXTTRIG0_ULP11 SIWX91X_GPIO(8, 6, 33, 4, 11, 11)
209 0 : #define PWM_EXTTRIG1_HP28 SIWX91X_GPIO(10, 0xFF, 0, 1, 12, 0)
210 0 : #define PWM_EXTTRIG1_HP54 SIWX91X_GPIO(8, 0xFF, 18, 3, 6, 0)
211 0 : #define PWM_EXTTRIG1_ULP7 SIWX91X_GPIO(10, 6, 29, 4, 7, 7)
212 0 : #define PWM_EXTTRIG2_HP29 SIWX91X_GPIO(10, 0xFF, 0, 1, 13, 0)
213 0 : #define PWM_EXTTRIG2_HP55 SIWX91X_GPIO(8, 0xFF, 19, 3, 7, 0)
214 0 : #define PWM_EXTTRIG2_ULP8 SIWX91X_GPIO(10, 6, 30, 4, 8, 8)
215 0 : #define PWM_EXTTRIG3_HP30 SIWX91X_GPIO(10, 0xFF, 0, 1, 14, 0)
216 0 : #define PWM_EXTTRIG3_HP50 SIWX91X_GPIO(8, 0xFF, 14, 3, 2, 0)
217 0 : #define PWM_EXTTRIG3_ULP9 SIWX91X_GPIO(10, 6, 31, 4, 9, 9)
218 0 : #define PWM_FAULTA_HP25 SIWX91X_GPIO(10, 0xFF, 0, 1, 9, 0)
219 0 : #define PWM_FAULTA_ULP4 SIWX91X_GPIO(10, 6, 26, 4, 4, 4)
220 0 : #define PWM_FAULTA_ULP9 SIWX91X_GPIO(8, 6, 31, 4, 9, 9)
221 0 : #define PWM_FAULTB_HP26 SIWX91X_GPIO(10, 0xFF, 0, 1, 10, 0)
222 0 : #define PWM_FAULTB_ULP5 SIWX91X_GPIO(10, 6, 27, 4, 5, 5)
223 0 : #define PWM_FAULTB_ULP10 SIWX91X_GPIO(8, 6, 32, 4, 10, 10)
224 0 : #define PWM_SLEEPEVENT_ULP8 SIWX91X_GPIO(8, 6, 30, 4, 8, 8)
225 :
226 0 : #define QEI_DIR_HP11 SIWX91X_GPIO(5, 0xFF, 6, 0, 11, 0)
227 0 : #define QEI_DIR_HP28 SIWX91X_GPIO(5, 0xFF, 0, 1, 12, 0)
228 0 : #define QEI_DIR_HP34 SIWX91X_GPIO(13, 0xFF, 9, 2, 2, 0)
229 0 : #define QEI_DIR_HP49 SIWX91X_GPIO(3, 0xFF, 13, 3, 1, 0)
230 0 : #define QEI_DIR_HP57 SIWX91X_GPIO(5, 0xFF, 21, 3, 9, 0)
231 0 : #define QEI_DIR_ULP3 SIWX91X_GPIO(3, 6, 25, 4, 3, 3)
232 0 : #define QEI_DIR_ULP7 SIWX91X_GPIO(3, 6, 29, 4, 7, 7)
233 0 : #define QEI_DIR_ULP11 SIWX91X_GPIO(3, 6, 33, 4, 11, 11)
234 0 : #define QEI_IDX_HP8 SIWX91X_GPIO(5, 0xFF, 3, 0, 8, 0)
235 0 : #define QEI_IDX_HP31 SIWX91X_GPIO(13, 0xFF, 9, 1, 15, 0)
236 0 : #define QEI_IDX_HP25 SIWX91X_GPIO(5, 0xFF, 0, 1, 9, 0)
237 0 : #define QEI_IDX_HP46 SIWX91X_GPIO(3, 0xFF, 10, 2, 14, 0)
238 0 : #define QEI_IDX_HP52 SIWX91X_GPIO(5, 0xFF, 16, 3, 4, 0)
239 0 : #define QEI_IDX_ULP0 SIWX91X_GPIO(3, 6, 22, 4, 0, 0)
240 0 : #define QEI_IDX_ULP4 SIWX91X_GPIO(3, 6, 26, 4, 4, 4)
241 0 : #define QEI_IDX_ULP8 SIWX91X_GPIO(3, 6, 30, 4, 8, 8)
242 0 : #define QEI_PHA_HP9 SIWX91X_GPIO(5, 0xFF, 4, 0, 9, 0)
243 0 : #define QEI_PHA_HP26 SIWX91X_GPIO(5, 0xFF, 0, 1, 10, 0)
244 0 : #define QEI_PHA_HP32 SIWX91X_GPIO(13, 0xFF, 9, 2, 0, 0)
245 0 : #define QEI_PHA_HP47 SIWX91X_GPIO(3, 0xFF, 11, 2, 15, 0)
246 0 : #define QEI_PHA_HP53 SIWX91X_GPIO(5, 0xFF, 17, 3, 5, 0)
247 0 : #define QEI_PHA_ULP1 SIWX91X_GPIO(3, 6, 23, 4, 1, 1)
248 0 : #define QEI_PHA_ULP5 SIWX91X_GPIO(3, 6, 27, 4, 5, 5)
249 0 : #define QEI_PHA_ULP9 SIWX91X_GPIO(3, 6, 31, 4, 9, 9)
250 0 : #define QEI_PHB_HP10 SIWX91X_GPIO(5, 0xFF, 5, 0, 10, 0)
251 0 : #define QEI_PHB_HP27 SIWX91X_GPIO(5, 0xFF, 0, 1, 11, 0)
252 0 : #define QEI_PHB_HP33 SIWX91X_GPIO(13, 0xFF, 9, 2, 1, 0)
253 0 : #define QEI_PHB_HP48 SIWX91X_GPIO(3, 0xFF, 12, 3, 0, 0)
254 0 : #define QEI_PHB_HP56 SIWX91X_GPIO(5, 0xFF, 20, 3, 8, 0)
255 0 : #define QEI_PHB_ULP2 SIWX91X_GPIO(3, 6, 24, 4, 2, 2)
256 0 : #define QEI_PHB_ULP6 SIWX91X_GPIO(3, 6, 28, 4, 6, 6)
257 0 : #define QEI_PHB_ULP10 SIWX91X_GPIO(3, 6, 32, 4, 10, 10)
258 :
259 0 : #define QSPI_CLK_HP8 SIWX91X_GPIO(11, 0xFF, 3, 0, 8, 0)
260 0 : #define QSPI_CLK_HP46 SIWX91X_GPIO(1, 0xFF, 10, 2, 14, 0)
261 0 : #define QSPI_CLK_HP52 SIWX91X_GPIO(9, 0xFF, 16, 3, 4, 0)
262 0 : #define QSPI_CSN0_HP7 SIWX91X_GPIO(11, 0xFF, 2, 0, 7, 0)
263 0 : #define QSPI_CSN0_HP49 SIWX91X_GPIO(1, 0xFF, 13, 3, 1, 0)
264 0 : #define QSPI_CSN0_HP55 SIWX91X_GPIO(9, 0xFF, 19, 3, 7, 0)
265 0 : #define QSPI_CSN1_HP7 SIWX91X_GPIO(12, 0xFF, 2, 0, 7, 0)
266 0 : #define QSPI_CSN1_HP53 SIWX91X_GPIO(1, 0xFF, 17, 3, 5, 0)
267 0 : #define QSPI_CSN9_HP49 SIWX91X_GPIO(10, 0xFF, 13, 3, 1, 0)
268 0 : #define QSPI_D0_HP6 SIWX91X_GPIO(11, 0xFF, 1, 0, 6, 0)
269 0 : #define QSPI_D0_HP47 SIWX91X_GPIO(1, 0xFF, 11, 2, 15, 0)
270 0 : #define QSPI_D0_HP53 SIWX91X_GPIO(9, 0xFF, 17, 3, 5, 0)
271 0 : #define QSPI_D1_HP9 SIWX91X_GPIO(11, 0xFF, 4, 0, 9, 0)
272 0 : #define QSPI_D1_HP48 SIWX91X_GPIO(1, 0xFF, 12, 3, 0, 0)
273 0 : #define QSPI_D1_HP54 SIWX91X_GPIO(9, 0xFF, 18, 3, 6, 0)
274 0 : #define QSPI_D2_HP10 SIWX91X_GPIO(11, 0xFF, 5, 0, 10, 0)
275 0 : #define QSPI_D2_HP50 SIWX91X_GPIO(1, 0xFF, 14, 3, 2, 0)
276 0 : #define QSPI_D2_HP56 SIWX91X_GPIO(9, 0xFF, 20, 3, 8, 0)
277 0 : #define QSPI_D3_HP11 SIWX91X_GPIO(11, 0xFF, 6, 0, 11, 0)
278 0 : #define QSPI_D3_HP51 SIWX91X_GPIO(1, 0xFF, 15, 3, 3, 0)
279 0 : #define QSPI_D3_HP57 SIWX91X_GPIO(9, 0xFF, 21, 3, 9, 0)
280 0 : #define QSPI_D4_HP54 SIWX91X_GPIO(1, 0xFF, 18, 3, 6, 0)
281 0 : #define QSPI_D5_HP55 SIWX91X_GPIO(1, 0xFF, 19, 3, 7, 0)
282 0 : #define QSPI_D6_HP56 SIWX91X_GPIO(1, 0xFF, 20, 3, 8, 0)
283 0 : #define QSPI_D7_HP57 SIWX91X_GPIO(1, 0xFF, 21, 3, 9, 0)
284 :
285 0 : #define SCT_IN0_HP25 SIWX91X_GPIO(9, 0xFF, 0, 1, 9, 0)
286 0 : #define SCT_IN0_ULP0 SIWX91X_GPIO(7, 6, 22, 4, 0, 0)
287 0 : #define SCT_IN0_ULP4 SIWX91X_GPIO(9, 6, 26, 4, 4, 4)
288 0 : #define SCT_IN1_HP26 SIWX91X_GPIO(9, 0xFF, 0, 1, 10, 0)
289 0 : #define SCT_IN1_ULP1 SIWX91X_GPIO(7, 6, 23, 4, 1, 1)
290 0 : #define SCT_IN1_ULP5 SIWX91X_GPIO(9, 6, 27, 4, 5, 5)
291 0 : #define SCT_IN2_HP27 SIWX91X_GPIO(9, 0xFF, 0, 1, 11, 0)
292 0 : #define SCT_IN2_ULP2 SIWX91X_GPIO(7, 6, 24, 4, 2, 2)
293 0 : #define SCT_IN2_ULP6 SIWX91X_GPIO(9, 6, 28, 4, 6, 6)
294 0 : #define SCT_IN3_HP28 SIWX91X_GPIO(9, 0xFF, 0, 1, 12, 0)
295 0 : #define SCT_IN3_ULP3 SIWX91X_GPIO(7, 6, 25, 4, 3, 3)
296 0 : #define SCT_IN3_ULP7 SIWX91X_GPIO(9, 6, 29, 4, 7, 7)
297 0 : #define SCT_OUT0_HP29 SIWX91X_GPIO(9, 0xFF, 0, 1, 13, 0)
298 0 : #define SCT_OUT0_ULP4 SIWX91X_GPIO(7, 6, 26, 4, 4, 4)
299 0 : #define SCT_OUT1_HP30 SIWX91X_GPIO(9, 0xFF, 0, 1, 14, 0)
300 0 : #define SCT_OUT1_ULP5 SIWX91X_GPIO(7, 6, 27, 4, 5, 5)
301 0 : #define SCT_OUT2_HP8 SIWX91X_GPIO(12, 0xFF, 3, 0, 8, 0)
302 0 : #define SCT_OUT2_ULP6 SIWX91X_GPIO(7, 6, 28, 4, 6, 6)
303 0 : #define SCT_OUT3_HP9 SIWX91X_GPIO(12, 0xFF, 4, 0, 9, 0)
304 0 : #define SCT_OUT3_ULP7 SIWX91X_GPIO(7, 6, 29, 4, 7, 7)
305 0 : #define SCT_OUT4_ULP4 SIWX91X_GPIO(13, 6, 26, 4, 4, 4)
306 0 : #define SCT_OUT4_ULP8 SIWX91X_GPIO(7, 6, 30, 4, 8, 8)
307 0 : #define SCT_OUT5_ULP5 SIWX91X_GPIO(13, 6, 27, 4, 5, 5)
308 0 : #define SCT_OUT5_ULP9 SIWX91X_GPIO(7, 6, 31, 4, 9, 9)
309 0 : #define SCT_OUT6_ULP6 SIWX91X_GPIO(13, 6, 28, 4, 6, 6)
310 0 : #define SCT_OUT6_ULP10 SIWX91X_GPIO(7, 6, 32, 4, 10, 10)
311 0 : #define SCT_OUT7_ULP7 SIWX91X_GPIO(13, 6, 29, 4, 7, 7)
312 0 : #define SCT_OUT7_ULP11 SIWX91X_GPIO(7, 6, 33, 4, 11, 11)
313 :
314 0 : #define SIO_0_HP6 SIWX91X_GPIO(1, 0xFF, 1, 0, 6, 0)
315 0 : #define SIO_0_HP25 SIWX91X_GPIO(1, 0xFF, 0, 1, 9, 0)
316 0 : #define SIO_0_ULP0 SIWX91X_GPIO(1, 6, 22, 4, 0, 0)
317 0 : #define SIO_0_ULP8 SIWX91X_GPIO(1, 6, 30, 4, 8, 8)
318 0 : #define SIO_1_HP7 SIWX91X_GPIO(1, 0xFF, 2, 0, 7, 0)
319 0 : #define SIO_1_HP26 SIWX91X_GPIO(1, 0xFF, 0, 1, 10, 0)
320 0 : #define SIO_1_ULP1 SIWX91X_GPIO(1, 6, 23, 4, 1, 1)
321 0 : #define SIO_1_ULP9 SIWX91X_GPIO(1, 6, 31, 4, 9, 9)
322 0 : #define SIO_2_HP8 SIWX91X_GPIO(1, 0xFF, 3, 0, 8, 0)
323 0 : #define SIO_2_HP27 SIWX91X_GPIO(1, 0xFF, 0, 1, 11, 0)
324 0 : #define SIO_2_ULP2 SIWX91X_GPIO(1, 6, 24, 4, 2, 2)
325 0 : #define SIO_2_ULP10 SIWX91X_GPIO(1, 6, 32, 4, 10, 10)
326 0 : #define SIO_3_HP9 SIWX91X_GPIO(1, 0xFF, 4, 0, 9, 0)
327 0 : #define SIO_3_HP28 SIWX91X_GPIO(1, 0xFF, 0, 1, 12, 0)
328 0 : #define SIO_3_ULP3 SIWX91X_GPIO(1, 6, 25, 4, 3, 3)
329 0 : #define SIO_3_ULP11 SIWX91X_GPIO(1, 6, 33, 4, 11, 11)
330 0 : #define SIO_4_HP10 SIWX91X_GPIO(1, 0xFF, 5, 0, 10, 0)
331 0 : #define SIO_4_HP29 SIWX91X_GPIO(1, 0xFF, 0, 1, 13, 0)
332 0 : #define SIO_4_ULP4 SIWX91X_GPIO(1, 6, 26, 4, 4, 4)
333 0 : #define SIO_5_HP11 SIWX91X_GPIO(1, 0xFF, 6, 0, 11, 0)
334 0 : #define SIO_5_HP30 SIWX91X_GPIO(1, 0xFF, 0, 1, 14, 0)
335 0 : #define SIO_5_ULP5 SIWX91X_GPIO(1, 6, 27, 4, 5, 5)
336 0 : #define SIO_6_ULP6 SIWX91X_GPIO(1, 6, 28, 4, 6, 6)
337 0 : #define SIO_7_HP15 SIWX91X_GPIO(1, 0xFF, 8, 0, 15, 0)
338 0 : #define SIO_7_ULP7 SIWX91X_GPIO(1, 6, 29, 4, 7, 7)
339 :
340 0 : #define SSI_CLK_HP8 SIWX91X_GPIO(3, 0xFF, 3, 0, 8, 0)
341 0 : #define SSI_CLK_HP25 SIWX91X_GPIO(3, 0xFF, 0, 1, 9, 0)
342 0 : #define SSI_CLK_HP52 SIWX91X_GPIO(3, 0xFF, 16, 3, 4, 0)
343 0 : #define SSI_CS0_HP9 SIWX91X_GPIO(3, 0xFF, 4, 0, 9, 0)
344 0 : #define SSI_CS0_HP28 SIWX91X_GPIO(3, 0xFF, 0, 1, 12, 0)
345 0 : #define SSI_CS0_HP53 SIWX91X_GPIO(3, 0xFF, 17, 3, 5, 0)
346 0 : #define SSI_CS1_HP10 SIWX91X_GPIO(3, 0xFF, 5, 0, 10, 0)
347 0 : #define SSI_CS2_HP15 SIWX91X_GPIO(3, 0xFF, 8, 0, 15, 0)
348 0 : #define SSI_CS2_HP50 SIWX91X_GPIO(3, 0xFF, 14, 3, 2, 0)
349 0 : #define SSI_CS3_HP51 SIWX91X_GPIO(3, 0xFF, 15, 3, 3, 0)
350 0 : #define SSI_DATA0_HP11 SIWX91X_GPIO(3, 0xFF, 6, 0, 11, 0)
351 0 : #define SSI_DATA0_HP26 SIWX91X_GPIO(3, 0xFF, 0, 1, 10, 0)
352 0 : #define SSI_DATA0_HP56 SIWX91X_GPIO(3, 0xFF, 20, 3, 8, 0)
353 0 : #define SSI_DATA1_HP10 SIWX91X_GPIO(12, 0xFF, 5, 0, 10, 0)
354 0 : #define SSI_DATA1_HP12 SIWX91X_GPIO(3, 0xFF, 7, 0, 12, 0)
355 0 : #define SSI_DATA1_HP27 SIWX91X_GPIO(3, 0xFF, 0, 1, 11, 0)
356 0 : #define SSI_DATA1_HP57 SIWX91X_GPIO(3, 0xFF, 21, 3, 9, 0)
357 0 : #define SSI_DATA2_HP6 SIWX91X_GPIO(3, 0xFF, 1, 0, 6, 0)
358 0 : #define SSI_DATA2_HP29 SIWX91X_GPIO(3, 0xFF, 0, 1, 13, 0)
359 0 : #define SSI_DATA2_HP54 SIWX91X_GPIO(3, 0xFF, 18, 3, 6, 0)
360 0 : #define SSI_DATA3_HP7 SIWX91X_GPIO(3, 0xFF, 2, 0, 7, 0)
361 0 : #define SSI_DATA3_HP30 SIWX91X_GPIO(3, 0xFF, 0, 1, 14, 0)
362 0 : #define SSI_DATA3_HP55 SIWX91X_GPIO(3, 0xFF, 19, 3, 7, 0)
363 :
364 0 : #define SSIS_CLK_HP8 SIWX91X_GPIO(8, 0xFF, 3, 0, 8, 0)
365 0 : #define SSIS_CLK_HP26 SIWX91X_GPIO(8, 0xFF, 0, 1, 10, 0)
366 0 : #define SSIS_CLK_HP47 SIWX91X_GPIO(8, 0xFF, 11, 2, 15, 0)
367 0 : #define SSIS_CLK_HP52 SIWX91X_GPIO(8, 0xFF, 16, 3, 4, 0)
368 0 : #define SSIS_CS_HP9 SIWX91X_GPIO(8, 0xFF, 4, 0, 9, 0)
369 0 : #define SSIS_CS_HP25 SIWX91X_GPIO(8, 0xFF, 0, 1, 9, 0)
370 0 : #define SSIS_CS_HP46 SIWX91X_GPIO(8, 0xFF, 10, 2, 14, 0)
371 0 : #define SSIS_CS_HP53 SIWX91X_GPIO(8, 0xFF, 17, 3, 5, 0)
372 0 : #define SSIS_MISO_HP11 SIWX91X_GPIO(8, 0xFF, 6, 0, 11, 0)
373 0 : #define SSIS_MISO_HP28 SIWX91X_GPIO(8, 0xFF, 0, 1, 12, 0)
374 0 : #define SSIS_MISO_HP49 SIWX91X_GPIO(8, 0xFF, 13, 3, 1, 0)
375 0 : #define SSIS_MISO_HP57 SIWX91X_GPIO(8, 0xFF, 21, 3, 9, 0)
376 0 : #define SSIS_MOSI_HP10 SIWX91X_GPIO(8, 0xFF, 5, 0, 10, 0)
377 0 : #define SSIS_MOSI_HP27 SIWX91X_GPIO(8, 0xFF, 0, 1, 11, 0)
378 0 : #define SSIS_MOSI_HP48 SIWX91X_GPIO(8, 0xFF, 12, 3, 0, 0)
379 0 : #define SSIS_MOSI_HP56 SIWX91X_GPIO(8, 0xFF, 20, 3, 8, 0)
380 :
381 0 : #define TIMER0_HP7 SIWX91X_GPIO(9, 5, 2, 0, 7, 1)
382 0 : #define TIMER0_HP27 SIWX91X_GPIO(11, 5, 0, 1, 11, 8)
383 0 : #define TIMER0_HP46 SIWX91X_GPIO(9, 5, 10, 2, 14, 8)
384 0 : #define TIMER0_ULP4 SIWX91X_GPIO(0xFF, 9, 0xFF, 4, 0, 4)
385 0 : #define TIMER0_ULP8 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 8)
386 :
387 0 : #define TIMER1_HP15 SIWX91X_GPIO(9, 5, 8, 0, 15, 7)
388 0 : #define TIMER1_HP26 SIWX91X_GPIO(11, 5, 0, 1, 10, 7)
389 0 : #define TIMER1_ULP5 SIWX91X_GPIO(0xFF, 9, 0xFF, 4, 0, 5)
390 0 : #define TIMER1_ULP7 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 7)
391 :
392 0 : #define TIMER2_ULP1 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 1)
393 :
394 0 : #define TRACE_CLK_HP7 SIWX91X_GPIO(13, 0xFF, 2, 0, 7, 0)
395 0 : #define TRACE_CLK_HP47 SIWX91X_GPIO(6, 0xFF, 11, 2, 15, 0)
396 0 : #define TRACE_CLK_HP53 SIWX91X_GPIO(6, 0xFF, 17, 3, 5, 0)
397 0 : #define TRACE_CLKIN_HP6 SIWX91X_GPIO(13, 0xFF, 1, 0, 6, 0)
398 0 : #define TRACE_CLKIN_HP15 SIWX91X_GPIO(6, 0xFF, 8, 0, 15, 0)
399 0 : #define TRACE_CLKIN_HP46 SIWX91X_GPIO(6, 0xFF, 10, 2, 14, 0)
400 0 : #define TRACE_CLKIN_HP52 SIWX91X_GPIO(6, 0xFF, 16, 3, 4, 0)
401 0 : #define TRACE_D0_HP8 SIWX91X_GPIO(13, 0xFF, 3, 0, 8, 0)
402 0 : #define TRACE_D0_HP48 SIWX91X_GPIO(6, 0xFF, 12, 3, 0, 0)
403 0 : #define TRACE_D0_HP54 SIWX91X_GPIO(6, 0xFF, 18, 3, 6, 0)
404 0 : #define TRACE_D1_HP9 SIWX91X_GPIO(13, 0xFF, 4, 0, 9, 0)
405 0 : #define TRACE_D1_HP49 SIWX91X_GPIO(6, 0xFF, 13, 3, 1, 0)
406 0 : #define TRACE_D1_HP55 SIWX91X_GPIO(6, 0xFF, 19, 3, 7, 0)
407 0 : #define TRACE_D2_HP10 SIWX91X_GPIO(13, 0xFF, 5, 0, 10, 0)
408 0 : #define TRACE_D2_HP50 SIWX91X_GPIO(6, 0xFF, 14, 3, 2, 0)
409 0 : #define TRACE_D2_HP56 SIWX91X_GPIO(6, 0xFF, 20, 3, 8, 0)
410 0 : #define TRACE_D3_HP11 SIWX91X_GPIO(13, 0xFF, 6, 0, 11, 0)
411 0 : #define TRACE_D3_HP51 SIWX91X_GPIO(6, 0xFF, 15, 3, 3, 0)
412 0 : #define TRACE_D3_HP57 SIWX91X_GPIO(6, 0xFF, 21, 3, 9, 0)
413 :
414 0 : #define UART0_CLK_HP8 SIWX91X_GPIO(2, 0xFF, 3, 0, 8, 0)
415 0 : #define UART0_CLK_HP25 SIWX91X_GPIO(2, 0xFF, 0, 1, 9, 0)
416 0 : #define UART0_CLK_HP52 SIWX91X_GPIO(2, 0xFF, 16, 3, 4, 0)
417 0 : #define UART0_CLK_ULP0 SIWX91X_GPIO(2, 6, 22, 4, 0, 0)
418 0 : #define UART0_CTS_HP6 SIWX91X_GPIO(2, 0xFF, 1, 0, 6, 0)
419 0 : #define UART0_CTS_HP26 SIWX91X_GPIO(2, 0xFF, 0, 1, 10, 0)
420 0 : #define UART0_CTS_HP56 SIWX91X_GPIO(2, 0xFF, 20, 3, 8, 0)
421 0 : #define UART0_CTS_ULP6 SIWX91X_GPIO(2, 6, 28, 4, 6, 6)
422 0 : #define UART0_DCD_HP12 SIWX91X_GPIO(2, 0xFF, 7, 0, 12, 0)
423 0 : #define UART0_DCD_HP29 SIWX91X_GPIO(12, 0xFF, 0, 1, 13, 0)
424 0 : #define UART0_DSR_HP11 SIWX91X_GPIO(2, 0xFF, 6, 0, 11, 0)
425 0 : #define UART0_DSR_HP57 SIWX91X_GPIO(2, 0xFF, 21, 3, 9, 0)
426 0 : #define UART0_DTR_HP7 SIWX91X_GPIO(2, 0xFF, 2, 0, 7, 0)
427 0 : #define UART0_IRRX_HP25 SIWX91X_GPIO(13, 0xFF, 0, 1, 9, 0)
428 0 : #define UART0_IRRX_HP47 SIWX91X_GPIO(2, 0xFF, 11, 2, 15, 0)
429 0 : #define UART0_IRRX_ULP0 SIWX91X_GPIO(11, 6, 22, 4, 0, 0)
430 0 : #define UART0_IRRX_ULP7 SIWX91X_GPIO(2, 6, 29, 4, 7, 7)
431 0 : #define UART0_IRTX_HP26 SIWX91X_GPIO(13, 0xFF, 0, 1, 10, 0)
432 0 : #define UART0_IRTX_HP48 SIWX91X_GPIO(2, 0xFF, 12, 3, 0, 0)
433 0 : #define UART0_IRTX_ULP1 SIWX91X_GPIO(11, 6, 23, 4, 1, 1)
434 0 : #define UART0_IRTX_ULP8 SIWX91X_GPIO(2, 6, 30, 4, 8, 8)
435 0 : #define UART0_RI_HP27 SIWX91X_GPIO(2, 0xFF, 0, 1, 11, 0)
436 0 : #define UART0_RI_HP46 SIWX91X_GPIO(2, 0xFF, 10, 2, 14, 0)
437 0 : #define UART0_RI_ULP4 SIWX91X_GPIO(11, 6, 26, 4, 4, 4)
438 0 : #define UART0_RS485DE_HP29 SIWX91X_GPIO(13, 0xFF, 0, 1, 13, 0)
439 0 : #define UART0_RS485DE_HP51 SIWX91X_GPIO(2, 0xFF, 15, 3, 3, 0)
440 0 : #define UART0_RS485DE_ULP7 SIWX91X_GPIO(11, 6, 29, 4, 7, 7)
441 0 : #define UART0_RS485DE_ULP11 SIWX91X_GPIO(2, 6, 33, 4, 11, 11)
442 0 : #define UART0_RS485EN_HP27 SIWX91X_GPIO(13, 0xFF, 0, 1, 11, 0)
443 0 : #define UART0_RS485EN_HP49 SIWX91X_GPIO(2, 0xFF, 13, 3, 1, 0)
444 0 : #define UART0_RS485EN_ULP5 SIWX91X_GPIO(11, 6, 27, 4, 5, 5)
445 0 : #define UART0_RS485EN_ULP9 SIWX91X_GPIO(2, 6, 31, 4, 9, 9)
446 0 : #define UART0_RS485RE_HP28 SIWX91X_GPIO(13, 0xFF, 0, 1, 12, 0)
447 0 : #define UART0_RS485RE_HP50 SIWX91X_GPIO(2, 0xFF, 14, 3, 2, 0)
448 0 : #define UART0_RS485RE_ULP6 SIWX91X_GPIO(11, 6, 28, 4, 6, 6)
449 0 : #define UART0_RS485RE_ULP10 SIWX91X_GPIO(2, 6, 32, 4, 10, 10)
450 0 : #define UART0_RTS_HP9 SIWX91X_GPIO(2, 0xFF, 4, 0, 9, 0)
451 0 : #define UART0_RTS_HP28 SIWX91X_GPIO(2, 0xFF, 0, 1, 12, 0)
452 0 : #define UART0_RTS_HP53 SIWX91X_GPIO(2, 0xFF, 17, 3, 5, 0)
453 0 : #define UART0_RTS_ULP5 SIWX91X_GPIO(2, 6, 27, 4, 5, 5)
454 0 : #define UART0_RX_HP10 SIWX91X_GPIO(2, 0xFF, 5, 0, 10, 0)
455 0 : #define UART0_RX_HP29 SIWX91X_GPIO(2, 0xFF, 0, 1, 13, 0)
456 0 : #define UART0_RX_HP55 SIWX91X_GPIO(2, 0xFF, 19, 3, 7, 0)
457 0 : #define UART0_RX_ULP1 SIWX91X_GPIO(2, 6, 23, 4, 1, 1)
458 0 : #define UART0_RX_ULP6 SIWX91X_GPIO(4, 6, 28, 4, 6, 6)
459 0 : #define UART0_TX_HP30 SIWX91X_GPIO(2, 0xFF, 0, 1, 14, 0)
460 0 : #define UART0_TX_HP54 SIWX91X_GPIO(2, 0xFF, 18, 3, 6, 0)
461 0 : #define UART0_TX_ULP4 SIWX91X_GPIO(2, 6, 26, 4, 4, 4)
462 0 : #define UART0_TX_ULP7 SIWX91X_GPIO(4, 6, 29, 4, 7, 7)
463 :
464 0 : #define UART1_CTS_HP11 SIWX91X_GPIO(6, 0xFF, 6, 0, 11, 0)
465 0 : #define UART1_CTS_HP32 SIWX91X_GPIO(12, 0xFF, 9, 2, 0, 0)
466 0 : #define UART1_CTS_HP51 SIWX91X_GPIO(9, 0xFF, 15, 3, 3, 0)
467 0 : #define UART1_CTS_ULP1 SIWX91X_GPIO(9, 6, 23, 4, 1, 1)
468 0 : #define UART1_CTS_ULP7 SIWX91X_GPIO(6, 6, 29, 4, 7, 7)
469 0 : #define UART1_CTS_ULP9 SIWX91X_GPIO(9, 6, 31, 4, 9, 9)
470 0 : #define UART1_RS485DE_HP9 SIWX91X_GPIO(6, 0xFF, 4, 0, 9, 0)
471 0 : #define UART1_RS485DE_ULP2 SIWX91X_GPIO(6, 6, 24, 4, 2, 2)
472 0 : #define UART1_RS485DE_ULP11 SIWX91X_GPIO(6, 6, 33, 4, 11, 11)
473 0 : #define UART1_RS485EN_HP12 SIWX91X_GPIO(6, 0xFF, 7, 0, 12, 0)
474 0 : #define UART1_RS485EN_HP26 SIWX91X_GPIO(6, 0xFF, 0, 1, 10, 0)
475 0 : #define UART1_RS485EN_ULP0 SIWX91X_GPIO(6, 6, 22, 4, 0, 0)
476 0 : #define UART1_RS485RE_HP8 SIWX91X_GPIO(6, 0xFF, 3, 0, 8, 0)
477 0 : #define UART1_RS485RE_ULP1 SIWX91X_GPIO(6, 6, 23, 4, 1, 1)
478 0 : #define UART1_RS485RE_ULP10 SIWX91X_GPIO(6, 6, 32, 4, 10, 10)
479 0 : #define UART1_RTS_HP10 SIWX91X_GPIO(6, 0xFF, 5, 0, 10, 0)
480 0 : #define UART1_RTS_HP27 SIWX91X_GPIO(6, 0xFF, 0, 1, 11, 0)
481 0 : #define UART1_RTS_HP28 SIWX91X_GPIO(6, 0xFF, 0, 1, 12, 0)
482 0 : #define UART1_RTS_HP31 SIWX91X_GPIO(12, 0xFF, 9, 1, 15, 0)
483 0 : #define UART1_RTS_HP50 SIWX91X_GPIO(9, 0xFF, 14, 3, 2, 0)
484 0 : #define UART1_RTS_ULP0 SIWX91X_GPIO(9, 6, 22, 4, 0, 0)
485 0 : #define UART1_RTS_ULP6 SIWX91X_GPIO(6, 6, 28, 4, 6, 6)
486 0 : #define UART1_RTS_ULP8 SIWX91X_GPIO(9, 6, 30, 4, 8, 8)
487 0 : #define UART1_RX_HP6 SIWX91X_GPIO(6, 0xFF, 1, 0, 6, 0)
488 0 : #define UART1_RX_HP29 SIWX91X_GPIO(6, 0xFF, 0, 1, 13, 0)
489 0 : #define UART1_RX_HP33 SIWX91X_GPIO(12, 0xFF, 9, 2, 1, 0)
490 0 : #define UART1_RX_ULP2 SIWX91X_GPIO(9, 6, 24, 4, 1, 1)
491 0 : #define UART1_RX_ULP4 SIWX91X_GPIO(6, 6, 26, 4, 4, 4)
492 0 : #define UART1_RX_ULP8 SIWX91X_GPIO(6, 6, 30, 4, 8, 8)
493 0 : #define UART1_RX_ULP10 SIWX91X_GPIO(9, 6, 32, 4, 10, 10)
494 0 : #define UART1_TX_HP15 SIWX91X_GPIO(2, 0xFF, 8, 0, 15, 0)
495 0 : #define UART1_TX_HP7 SIWX91X_GPIO(6, 0xFF, 2, 0, 7, 0)
496 0 : #define UART1_TX_HP30 SIWX91X_GPIO(6, 0xFF, 0, 1, 14, 0)
497 0 : #define UART1_TX_HP34 SIWX91X_GPIO(12, 0xFF, 9, 2, 2, 0)
498 0 : #define UART1_TX_ULP3 SIWX91X_GPIO(9, 6, 25, 4, 1, 1)
499 0 : #define UART1_TX_ULP5 SIWX91X_GPIO(6, 6, 27, 4, 5, 5)
500 0 : #define UART1_TX_ULP9 SIWX91X_GPIO(6, 6, 31, 4, 9, 9)
501 0 : #define UART1_TX_ULP11 SIWX91X_GPIO(9, 6, 33, 4, 11, 11)
502 :
503 0 : #define ULPI2C_SCL_HP11 SIWX91X_GPIO(9, 4, 6, 0, 11, 5)
504 0 : #define ULPI2C_SCL_HP15 SIWX91X_GPIO(9, 4, 8, 0, 15, 7)
505 0 : #define ULPI2C_SCL_HP7 SIWX91X_GPIO(9, 4, 2, 0, 7, 1)
506 0 : #define ULPI2C_SCL_HP26 SIWX91X_GPIO(11, 4, 0, 1, 10, 7)
507 0 : #define ULPI2C_SCL_HP27 SIWX91X_GPIO(11, 4, 0, 1, 11, 8)
508 0 : #define ULPI2C_SCL_HP46 SIWX91X_GPIO(9, 4, 10, 2, 14, 8)
509 0 : #define ULPI2C_SCL_ULP1 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 1)
510 0 : #define ULPI2C_SCL_ULP5 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 5)
511 0 : #define ULPI2C_SCL_ULP7 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 7)
512 0 : #define ULPI2C_SCL_ULP8 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 8)
513 0 : #define ULPI2C_SDA_HP6 SIWX91X_GPIO(9, 4, 1, 0, 6, 0)
514 0 : #define ULPI2C_SDA_HP10 SIWX91X_GPIO(9, 4, 5, 0, 10, 4)
515 0 : #define ULPI2C_SDA_HP12 SIWX91X_GPIO(9, 4, 7, 0, 12, 6)
516 0 : #define ULPI2C_SDA_HP25 SIWX91X_GPIO(11, 4, 0, 1, 9, 6)
517 0 : #define ULPI2C_SDA_HP28 SIWX91X_GPIO(11, 4, 0, 1, 12, 9)
518 0 : #define ULPI2C_SDA_HP30 SIWX91X_GPIO(11, 4, 0, 1, 14, 11)
519 0 : #define ULPI2C_SDA_HP47 SIWX91X_GPIO(9, 4, 11, 2, 15, 9)
520 0 : #define ULPI2C_SDA_HP49 SIWX91X_GPIO(9, 4, 13, 3, 1, 11)
521 0 : #define ULPI2C_SDA_ULP0 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 0)
522 0 : #define ULPI2C_SDA_ULP4 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 4)
523 0 : #define ULPI2C_SDA_ULP6 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 6)
524 0 : #define ULPI2C_SDA_ULP9 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 9)
525 0 : #define ULPI2C_SDA_ULP11 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 11)
526 :
527 0 : #define ULPI2S_CLK_HP15 SIWX91X_GPIO(9, 2, 8, 0, 15, 7)
528 0 : #define ULPI2S_CLK_HP26 SIWX91X_GPIO(11, 2, 0, 1, 10, 7)
529 0 : #define ULPI2S_CLK_HP27 SIWX91X_GPIO(11, 2, 0, 1, 11, 8)
530 0 : #define ULPI2S_CLK_HP46 SIWX91X_GPIO(9, 2, 10, 2, 14, 8)
531 0 : #define ULPI2S_CLK_ULP7 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 7)
532 0 : #define ULPI2S_CLK_ULP8 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 8)
533 0 : #define ULPI2S_DIN_HP12 SIWX91X_GPIO(9, 2, 7, 0, 12, 6)
534 0 : #define ULPI2S_DIN_HP6 SIWX91X_GPIO(9, 2, 1, 0, 6, 0)
535 0 : #define ULPI2S_DIN_HP25 SIWX91X_GPIO(11, 2, 0, 1, 9, 6)
536 0 : #define ULPI2S_DIN_HP28 SIWX91X_GPIO(11, 2, 0, 1, 12, 9)
537 0 : #define ULPI2S_DIN_HP47 SIWX91X_GPIO(9, 2, 11, 2, 15, 9)
538 0 : #define ULPI2S_DIN_ULP0 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 0)
539 0 : #define ULPI2S_DIN_ULP6 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 6)
540 0 : #define ULPI2S_DIN_ULP9 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 9)
541 0 : #define ULPI2S_DOUT_HP7 SIWX91X_GPIO(9, 2, 2, 0, 7, 1)
542 0 : #define ULPI2S_DOUT_HP11 SIWX91X_GPIO(9, 2, 6, 0, 11, 5)
543 0 : #define ULPI2S_DOUT_HP30 SIWX91X_GPIO(11, 2, 0, 1, 14, 11)
544 0 : #define ULPI2S_DOUT_HP49 SIWX91X_GPIO(9, 2, 13, 3, 1, 11)
545 0 : #define ULPI2S_DOUT_ULP1 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 1)
546 0 : #define ULPI2S_DOUT_ULP5 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 5)
547 0 : #define ULPI2S_DOUT_ULP11 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 11)
548 0 : #define ULPI2S_WS_HP8 SIWX91X_GPIO(9, 2, 3, 0, 8, 2)
549 0 : #define ULPI2S_WS_HP10 SIWX91X_GPIO(9, 2, 5, 0, 10, 4)
550 0 : #define ULPI2S_WS_HP29 SIWX91X_GPIO(11, 2, 0, 1, 13, 10)
551 0 : #define ULPI2S_WS_HP48 SIWX91X_GPIO(9, 2, 12, 3, 0, 10)
552 0 : #define ULPI2S_WS_ULP2 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 2)
553 0 : #define ULPI2S_WS_ULP4 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 4)
554 0 : #define ULPI2S_WS_ULP10 SIWX91X_GPIO(0xFF, 2, 0xFF, 4, 0, 10)
555 :
556 0 : #define ULPSSI_CLK_HP6 SIWX91X_GPIO(9, 1, 1, 0, 6, 0)
557 0 : #define ULPSSI_CLK_HP27 SIWX91X_GPIO(11, 1, 0, 1, 11, 8)
558 0 : #define ULPSSI_CLK_HP46 SIWX91X_GPIO(9, 1, 10, 2, 14, 8)
559 0 : #define ULPSSI_CLK_ULP0 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 0)
560 0 : #define ULPSSI_CLK_ULP4 SIWX91X_GPIO(0xFF, 8, 0xFF, 4, 0, 4)
561 0 : #define ULPSSI_CLK_ULP8 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 8)
562 0 : #define ULPSSI_CS0_HP29 SIWX91X_GPIO(11, 1, 0, 1, 13, 10)
563 0 : #define ULPSSI_CS0_HP48 SIWX91X_GPIO(9, 1, 12, 3, 0, 10)
564 0 : #define ULPSSI_CS0_ULP7 SIWX91X_GPIO(0xFF, 8, 0xFF, 4, 0, 7)
565 0 : #define ULPSSI_CS0_ULP10 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 10)
566 0 : #define ULPSSI_CS1_HP10 SIWX91X_GPIO(9, 1, 5, 0, 10, 4)
567 0 : #define ULPSSI_CS1_ULP4 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 4)
568 0 : #define ULPSSI_CS2_HP12 SIWX91X_GPIO(9, 1, 7, 0, 12, 6)
569 0 : #define ULPSSI_CS2_HP25 SIWX91X_GPIO(11, 1, 0, 1, 9, 6)
570 0 : #define ULPSSI_CS2_ULP6 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 6)
571 0 : #define ULPSSI_DIN_HP8 SIWX91X_GPIO(9, 1, 3, 0, 8, 2)
572 0 : #define ULPSSI_DIN_HP28 SIWX91X_GPIO(11, 1, 0, 1, 12, 9)
573 0 : #define ULPSSI_DIN_HP47 SIWX91X_GPIO(9, 1, 11, 2, 15, 9)
574 0 : #define ULPSSI_DIN_ULP2 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 2)
575 0 : #define ULPSSI_DIN_ULP6 SIWX91X_GPIO(0xFF, 8, 0xFF, 4, 0, 6)
576 0 : #define ULPSSI_DIN_ULP9 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 9)
577 0 : #define ULPSSI_DOUT_HP7 SIWX91X_GPIO(9, 1, 2, 0, 7, 1)
578 0 : #define ULPSSI_DOUT_HP30 SIWX91X_GPIO(11, 1, 0, 1, 14, 11)
579 0 : #define ULPSSI_DOUT_HP49 SIWX91X_GPIO(9, 1, 13, 3, 1, 11)
580 0 : #define ULPSSI_DOUT_ULP1 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 1)
581 0 : #define ULPSSI_DOUT_ULP5 SIWX91X_GPIO(0xFF, 8, 0xFF, 4, 0, 5)
582 0 : #define ULPSSI_DOUT_ULP11 SIWX91X_GPIO(0xFF, 1, 0xFF, 4, 0, 11)
583 :
584 0 : #define ULPUART_CTS_HP7 SIWX91X_GPIO(9, 3, 2, 0, 7, 1)
585 0 : #define ULPUART_CTS_HP11 SIWX91X_GPIO(9, 3, 6, 0, 11, 5)
586 0 : #define ULPUART_CTS_HP27 SIWX91X_GPIO(11, 3, 0, 1, 11, 8)
587 0 : #define ULPUART_CTS_HP46 SIWX91X_GPIO(9, 3, 10, 2, 14, 8)
588 0 : #define ULPUART_CTS_ULP1 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 1)
589 0 : #define ULPUART_CTS_ULP5 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 5)
590 0 : #define ULPUART_CTS_ULP8 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 8)
591 0 : #define ULPUART_RTS_HP6 SIWX91X_GPIO(9, 3, 1, 0, 6, 0)
592 0 : #define ULPUART_RTS_HP10 SIWX91X_GPIO(9, 3, 5, 0, 10, 4)
593 0 : #define ULPUART_RTS_HP29 SIWX91X_GPIO(11, 3, 0, 1, 13, 10)
594 0 : #define ULPUART_RTS_HP48 SIWX91X_GPIO(9, 3, 12, 3, 0, 10)
595 0 : #define ULPUART_RTS_ULP0 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 0)
596 0 : #define ULPUART_RTS_ULP4 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 4)
597 0 : #define ULPUART_RTS_ULP10 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 10)
598 0 : #define ULPUART_RX_HP8 SIWX91X_GPIO(9, 3, 3, 0, 8, 2)
599 0 : #define ULPUART_RX_HP12 SIWX91X_GPIO(9, 3, 7, 0, 12, 6)
600 0 : #define ULPUART_RX_HP25 SIWX91X_GPIO(11, 3, 0, 1, 9, 6)
601 0 : #define ULPUART_RX_HP28 SIWX91X_GPIO(11, 3, 0, 1, 12, 9)
602 0 : #define ULPUART_RX_HP47 SIWX91X_GPIO(9, 3, 11, 2, 15, 9)
603 0 : #define ULPUART_RX_ULP2 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 2)
604 0 : #define ULPUART_RX_ULP6 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 6)
605 0 : #define ULPUART_RX_ULP9 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 9)
606 0 : #define ULPUART_TX_HP15 SIWX91X_GPIO(9, 3, 8, 0, 15, 7)
607 0 : #define ULPUART_TX_HP26 SIWX91X_GPIO(11, 3, 0, 1, 10, 7)
608 0 : #define ULPUART_TX_HP30 SIWX91X_GPIO(11, 3, 0, 1, 14, 11)
609 0 : #define ULPUART_TX_HP49 SIWX91X_GPIO(9, 3, 13, 3, 1, 11)
610 0 : #define ULPUART_TX_ULP7 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 7)
611 0 : #define ULPUART_TX_ULP11 SIWX91X_GPIO(0xFF, 3, 0xFF, 4, 0, 11)
612 :
613 0 : #define UULP_GPIO4_ULP2 SIWX91X_GPIO(0xFF, 4, 0xFF, 4, 0, 2)
614 0 : #define UULP_TESTMODE0_ULP7 SIWX91X_GPIO(0xFF, 11, 0xFF, 4, 0, 7)
615 0 : #define UULP_TESTMODE0_ULP9 SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 9)
616 :
617 : /* clang-format on */
618 :
619 : /* The following definitions are duplicates of signals that are also
620 : * available on the same pins using other GPIO modes.
621 : * #define IR_OUTPUT_ULP5 SIWX91X_GPIO(0xFF, 10, 0xFF, 4, 0, 5)
622 : * #define PMU_TEST2_HP30 SIWX91X_GPIO(13, 0xFF, 0, 1, 14, 0)
623 : * #define PWM_1H_ULP1 SIWX91X_GPIO(8, 6, 23, 4, 1, 1)
624 : * #define PWM_1L_ULP0 SIWX91X_GPIO(8, 6, 22, 4, 0, 0)
625 : */
626 :
627 : #endif /* INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_SIWX91X_PINCTRL_H_ */
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