Line data Source code
1 0 : /*
2 : * Copyright (c) 2024 Silicon Laboratories Inc.
3 : * SPDX-License-Identifier: Apache-2.0
4 : *
5 : * Pin Control for Silicon Labs XG21 devices
6 : *
7 : * This file was generated by the script gen_pinctrl.py in the hal_silabs module.
8 : * Do not manually edit.
9 : */
10 :
11 : #ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_
12 : #define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_
13 :
14 : #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
15 :
16 0 : #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
17 :
18 0 : #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
19 :
20 0 : #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
21 0 : #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 10, 1, 1, 3)
22 0 : #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 10, 1, 2, 4)
23 0 : #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
24 :
25 0 : #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 17, 1, 0, 1)
26 0 : #define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 17, 1, 1, 2)
27 0 : #define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 17, 1, 2, 3)
28 :
29 0 : #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 1)
30 0 : #define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 22, 1, 1, 2)
31 :
32 0 : #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 26, 1, 0, 1)
33 0 : #define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 26, 1, 1, 2)
34 :
35 0 : #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 30, 1, 0, 1)
36 0 : #define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 30, 1, 1, 2)
37 :
38 0 : #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 34, 1, 0, 1)
39 0 : #define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 34, 1, 1, 2)
40 0 : #define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 34, 1, 2, 3)
41 0 : #define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 34, 1, 3, 5)
42 0 : #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 34, 0, 0, 4)
43 :
44 0 : #define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1)
45 0 : #define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 41, 1, 1, 2)
46 0 : #define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 41, 1, 2, 3)
47 0 : #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 41, 1, 3, 4)
48 0 : #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 41, 1, 4, 5)
49 0 : #define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 41, 1, 5, 6)
50 0 : #define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 41, 1, 6, 7)
51 0 : #define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 41, 1, 7, 8)
52 0 : #define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 41, 1, 8, 9)
53 0 : #define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 41, 1, 9, 10)
54 0 : #define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 41, 1, 10, 11)
55 0 : #define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 41, 1, 11, 12)
56 0 : #define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 41, 1, 12, 13)
57 0 : #define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 41, 1, 13, 14)
58 0 : #define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 41, 1, 14, 15)
59 0 : #define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 41, 1, 15, 16)
60 :
61 0 : #define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 59, 1, 0, 1)
62 0 : #define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 59, 1, 1, 2)
63 0 : #define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 59, 1, 2, 3)
64 0 : #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 59, 1, 3, 4)
65 0 : #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 59, 1, 4, 5)
66 0 : #define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 59, 1, 5, 6)
67 :
68 0 : #define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 67, 1, 0, 1)
69 0 : #define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 67, 1, 1, 2)
70 0 : #define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 67, 1, 2, 3)
71 0 : #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 67, 1, 3, 4)
72 0 : #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 67, 1, 4, 5)
73 0 : #define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 67, 1, 5, 6)
74 :
75 0 : #define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 75, 1, 0, 1)
76 0 : #define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 75, 1, 1, 2)
77 0 : #define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 75, 1, 2, 3)
78 0 : #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 75, 1, 3, 4)
79 0 : #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 75, 1, 4, 5)
80 0 : #define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 75, 1, 5, 6)
81 :
82 0 : #define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 83, 1, 0, 1)
83 0 : #define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 83, 1, 1, 2)
84 0 : #define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 83, 1, 2, 3)
85 0 : #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 83, 1, 3, 4)
86 0 : #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 83, 1, 4, 5)
87 0 : #define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 83, 1, 5, 6)
88 :
89 0 : #define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 91, 1, 0, 1)
90 0 : #define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 91, 1, 1, 3)
91 0 : #define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 91, 1, 2, 4)
92 0 : #define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 91, 1, 3, 5)
93 0 : #define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 91, 1, 4, 6)
94 0 : #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 91, 0, 0, 2)
95 :
96 0 : #define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 99, 1, 0, 1)
97 0 : #define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 99, 1, 1, 3)
98 0 : #define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 99, 1, 2, 4)
99 0 : #define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 99, 1, 3, 5)
100 0 : #define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 99, 1, 4, 6)
101 0 : #define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 99, 0, 0, 2)
102 :
103 0 : #define SILABS_DBUS_USART2_CS(port, pin) SILABS_DBUS(port, pin, 107, 1, 0, 1)
104 0 : #define SILABS_DBUS_USART2_RTS(port, pin) SILABS_DBUS(port, pin, 107, 1, 1, 3)
105 0 : #define SILABS_DBUS_USART2_RX(port, pin) SILABS_DBUS(port, pin, 107, 1, 2, 4)
106 0 : #define SILABS_DBUS_USART2_CLK(port, pin) SILABS_DBUS(port, pin, 107, 1, 3, 5)
107 0 : #define SILABS_DBUS_USART2_TX(port, pin) SILABS_DBUS(port, pin, 107, 1, 4, 6)
108 0 : #define SILABS_DBUS_USART2_CTS(port, pin) SILABS_DBUS(port, pin, 107, 0, 0, 2)
109 :
110 0 : #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
111 0 : #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
112 0 : #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
113 0 : #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
114 0 : #define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4)
115 0 : #define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
116 0 : #define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
117 0 : #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
118 0 : #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
119 0 : #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
120 0 : #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
121 0 : #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
122 0 : #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
123 0 : #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
124 0 : #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
125 0 : #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
126 0 : #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
127 0 : #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
128 0 : #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
129 0 : #define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4)
130 :
131 0 : #define ACMP1_ACMPOUT_PA0 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x0)
132 0 : #define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1)
133 0 : #define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2)
134 0 : #define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3)
135 0 : #define ACMP1_ACMPOUT_PA4 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x4)
136 0 : #define ACMP1_ACMPOUT_PA5 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x5)
137 0 : #define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6)
138 0 : #define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0)
139 0 : #define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1)
140 0 : #define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0)
141 0 : #define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1)
142 0 : #define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2)
143 0 : #define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3)
144 0 : #define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4)
145 0 : #define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5)
146 0 : #define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0)
147 0 : #define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1)
148 0 : #define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2)
149 0 : #define ACMP1_ACMPOUT_PD3 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x3)
150 0 : #define ACMP1_ACMPOUT_PD4 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x4)
151 :
152 0 : #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
153 0 : #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
154 0 : #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
155 0 : #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
156 0 : #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
157 0 : #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
158 0 : #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
159 0 : #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
160 0 : #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
161 0 : #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
162 0 : #define CMU_CLKOUT0_PD4 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x4)
163 0 : #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
164 0 : #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
165 0 : #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
166 0 : #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
167 0 : #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
168 0 : #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
169 0 : #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
170 0 : #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
171 0 : #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
172 0 : #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
173 0 : #define CMU_CLKOUT1_PD4 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x4)
174 0 : #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
175 0 : #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
176 0 : #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
177 0 : #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
178 0 : #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
179 0 : #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
180 0 : #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
181 0 : #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
182 0 : #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
183 0 : #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
184 0 : #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
185 0 : #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
186 0 : #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
187 0 : #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
188 0 : #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
189 0 : #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
190 0 : #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
191 0 : #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
192 0 : #define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
193 0 : #define CMU_CLKIN0_PD4 SILABS_DBUS_CMU_CLKIN0(0x3, 0x4)
194 :
195 0 : #define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0)
196 0 : #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
197 0 : #define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2)
198 0 : #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
199 0 : #define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4)
200 0 : #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
201 0 : #define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0)
202 0 : #define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1)
203 0 : #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
204 0 : #define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3)
205 0 : #define PTI_DCLK_PD4 SILABS_DBUS_PTI_DCLK(0x3, 0x4)
206 0 : #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
207 0 : #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
208 0 : #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
209 0 : #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
210 0 : #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
211 0 : #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
212 0 : #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
213 0 : #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
214 0 : #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
215 0 : #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
216 0 : #define PTI_DFRAME_PD4 SILABS_DBUS_PTI_DFRAME(0x3, 0x4)
217 0 : #define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0)
218 0 : #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
219 0 : #define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2)
220 0 : #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
221 0 : #define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4)
222 0 : #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
223 0 : #define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0)
224 0 : #define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1)
225 0 : #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
226 0 : #define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3)
227 0 : #define PTI_DOUT_PD4 SILABS_DBUS_PTI_DOUT(0x3, 0x4)
228 :
229 0 : #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
230 0 : #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
231 0 : #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
232 0 : #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
233 0 : #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
234 0 : #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
235 0 : #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
236 0 : #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
237 0 : #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
238 0 : #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
239 0 : #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
240 0 : #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
241 0 : #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
242 0 : #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
243 0 : #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
244 0 : #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
245 0 : #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
246 0 : #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
247 0 : #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
248 0 : #define I2C0_SCL_PD4 SILABS_DBUS_I2C0_SCL(0x3, 0x4)
249 0 : #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
250 0 : #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
251 0 : #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
252 0 : #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
253 0 : #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
254 0 : #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
255 0 : #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
256 0 : #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
257 0 : #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
258 0 : #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
259 0 : #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
260 0 : #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
261 0 : #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
262 0 : #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
263 0 : #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
264 0 : #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
265 0 : #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
266 0 : #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
267 0 : #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
268 0 : #define I2C0_SDA_PD4 SILABS_DBUS_I2C0_SDA(0x3, 0x4)
269 :
270 0 : #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
271 0 : #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
272 0 : #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
273 0 : #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
274 0 : #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
275 0 : #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
276 0 : #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
277 0 : #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
278 0 : #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
279 0 : #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
280 0 : #define I2C1_SCL_PD4 SILABS_DBUS_I2C1_SCL(0x3, 0x4)
281 0 : #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
282 0 : #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
283 0 : #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
284 0 : #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
285 0 : #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
286 0 : #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
287 0 : #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
288 0 : #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
289 0 : #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
290 0 : #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
291 0 : #define I2C1_SDA_PD4 SILABS_DBUS_I2C1_SDA(0x3, 0x4)
292 :
293 0 : #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
294 0 : #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
295 0 : #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
296 0 : #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
297 0 : #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
298 0 : #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
299 0 : #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
300 0 : #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
301 0 : #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
302 0 : #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
303 0 : #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
304 0 : #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
305 0 : #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
306 0 : #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
307 0 : #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
308 0 : #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
309 0 : #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
310 0 : #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
311 :
312 0 : #define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
313 0 : #define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
314 0 : #define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
315 0 : #define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
316 0 : #define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
317 0 : #define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
318 0 : #define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
319 0 : #define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
320 0 : #define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
321 0 : #define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
322 0 : #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
323 0 : #define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
324 0 : #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
325 0 : #define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
326 0 : #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
327 0 : #define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
328 0 : #define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
329 0 : #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
330 0 : #define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
331 0 : #define MODEM_ANT0_PD4 SILABS_DBUS_MODEM_ANT0(0x3, 0x4)
332 0 : #define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
333 0 : #define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
334 0 : #define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
335 0 : #define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
336 0 : #define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
337 0 : #define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
338 0 : #define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
339 0 : #define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
340 0 : #define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
341 0 : #define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
342 0 : #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
343 0 : #define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
344 0 : #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
345 0 : #define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
346 0 : #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
347 0 : #define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
348 0 : #define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
349 0 : #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
350 0 : #define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
351 0 : #define MODEM_ANT1_PD4 SILABS_DBUS_MODEM_ANT1(0x3, 0x4)
352 0 : #define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
353 0 : #define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
354 0 : #define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
355 0 : #define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
356 0 : #define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
357 0 : #define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
358 0 : #define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
359 0 : #define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
360 0 : #define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
361 0 : #define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
362 0 : #define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
363 0 : #define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
364 0 : #define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
365 0 : #define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
366 0 : #define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
367 0 : #define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
368 0 : #define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
369 0 : #define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
370 0 : #define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0)
371 0 : #define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1)
372 0 : #define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2)
373 0 : #define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3)
374 0 : #define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4)
375 0 : #define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5)
376 0 : #define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6)
377 0 : #define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0)
378 0 : #define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1)
379 :
380 0 : #define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
381 0 : #define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
382 0 : #define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
383 0 : #define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
384 0 : #define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
385 0 : #define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
386 0 : #define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
387 0 : #define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
388 0 : #define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
389 0 : #define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
390 0 : #define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
391 0 : #define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
392 0 : #define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
393 0 : #define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
394 0 : #define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
395 0 : #define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
396 0 : #define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
397 0 : #define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
398 0 : #define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
399 0 : #define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
400 0 : #define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
401 0 : #define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
402 0 : #define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
403 0 : #define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
404 0 : #define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
405 0 : #define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
406 0 : #define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
407 0 : #define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
408 0 : #define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
409 0 : #define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
410 0 : #define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
411 0 : #define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
412 0 : #define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
413 0 : #define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
414 0 : #define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
415 0 : #define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
416 0 : #define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
417 0 : #define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
418 0 : #define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
419 0 : #define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
420 0 : #define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
421 0 : #define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
422 0 : #define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
423 0 : #define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
424 0 : #define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
425 0 : #define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
426 0 : #define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
427 0 : #define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
428 0 : #define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
429 0 : #define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
430 0 : #define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
431 0 : #define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
432 0 : #define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
433 0 : #define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
434 0 : #define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
435 0 : #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
436 0 : #define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
437 0 : #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
438 0 : #define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
439 0 : #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
440 0 : #define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
441 0 : #define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
442 0 : #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
443 0 : #define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
444 0 : #define PRS0_ASYNCH6_PD4 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x4)
445 0 : #define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
446 0 : #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
447 0 : #define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
448 0 : #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
449 0 : #define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
450 0 : #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
451 0 : #define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
452 0 : #define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
453 0 : #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
454 0 : #define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
455 0 : #define PRS0_ASYNCH7_PD4 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x4)
456 0 : #define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
457 0 : #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
458 0 : #define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
459 0 : #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
460 0 : #define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
461 0 : #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
462 0 : #define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
463 0 : #define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
464 0 : #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
465 0 : #define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
466 0 : #define PRS0_ASYNCH8_PD4 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x4)
467 0 : #define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
468 0 : #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
469 0 : #define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
470 0 : #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
471 0 : #define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
472 0 : #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
473 0 : #define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
474 0 : #define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
475 0 : #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
476 0 : #define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
477 0 : #define PRS0_ASYNCH9_PD4 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x4)
478 0 : #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
479 0 : #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
480 0 : #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
481 0 : #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
482 0 : #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
483 0 : #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
484 0 : #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
485 0 : #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
486 0 : #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
487 0 : #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
488 0 : #define PRS0_ASYNCH10_PD4 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x4)
489 0 : #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
490 0 : #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
491 0 : #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
492 0 : #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
493 0 : #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
494 0 : #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
495 0 : #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
496 0 : #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
497 0 : #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
498 0 : #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
499 0 : #define PRS0_ASYNCH11_PD4 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x4)
500 0 : #define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
501 0 : #define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
502 0 : #define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
503 0 : #define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
504 0 : #define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
505 0 : #define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
506 0 : #define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
507 0 : #define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
508 0 : #define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
509 0 : #define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
510 0 : #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
511 0 : #define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
512 0 : #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
513 0 : #define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
514 0 : #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
515 0 : #define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
516 0 : #define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
517 0 : #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
518 0 : #define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
519 0 : #define PRS0_SYNCH0_PD4 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x4)
520 0 : #define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
521 0 : #define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
522 0 : #define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
523 0 : #define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
524 0 : #define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
525 0 : #define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
526 0 : #define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
527 0 : #define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
528 0 : #define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
529 0 : #define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
530 0 : #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
531 0 : #define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
532 0 : #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
533 0 : #define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
534 0 : #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
535 0 : #define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
536 0 : #define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
537 0 : #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
538 0 : #define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
539 0 : #define PRS0_SYNCH1_PD4 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x4)
540 0 : #define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
541 0 : #define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
542 0 : #define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
543 0 : #define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
544 0 : #define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
545 0 : #define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
546 0 : #define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
547 0 : #define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
548 0 : #define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
549 0 : #define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
550 0 : #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
551 0 : #define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
552 0 : #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
553 0 : #define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
554 0 : #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
555 0 : #define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
556 0 : #define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
557 0 : #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
558 0 : #define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
559 0 : #define PRS0_SYNCH2_PD4 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x4)
560 0 : #define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
561 0 : #define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
562 0 : #define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
563 0 : #define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
564 0 : #define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
565 0 : #define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
566 0 : #define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
567 0 : #define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
568 0 : #define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
569 0 : #define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
570 0 : #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
571 0 : #define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
572 0 : #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
573 0 : #define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
574 0 : #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
575 0 : #define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
576 0 : #define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
577 0 : #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
578 0 : #define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
579 0 : #define PRS0_SYNCH3_PD4 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x4)
580 :
581 0 : #define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
582 0 : #define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
583 0 : #define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
584 0 : #define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
585 0 : #define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
586 0 : #define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
587 0 : #define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
588 0 : #define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
589 0 : #define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
590 0 : #define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
591 0 : #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
592 0 : #define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
593 0 : #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
594 0 : #define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
595 0 : #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
596 0 : #define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
597 0 : #define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
598 0 : #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
599 0 : #define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
600 0 : #define TIMER0_CC0_PD4 SILABS_DBUS_TIMER0_CC0(0x3, 0x4)
601 0 : #define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
602 0 : #define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
603 0 : #define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
604 0 : #define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
605 0 : #define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
606 0 : #define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
607 0 : #define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
608 0 : #define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
609 0 : #define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
610 0 : #define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
611 0 : #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
612 0 : #define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
613 0 : #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
614 0 : #define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
615 0 : #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
616 0 : #define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
617 0 : #define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
618 0 : #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
619 0 : #define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
620 0 : #define TIMER0_CC1_PD4 SILABS_DBUS_TIMER0_CC1(0x3, 0x4)
621 0 : #define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
622 0 : #define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
623 0 : #define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
624 0 : #define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
625 0 : #define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
626 0 : #define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
627 0 : #define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
628 0 : #define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
629 0 : #define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
630 0 : #define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
631 0 : #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
632 0 : #define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
633 0 : #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
634 0 : #define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
635 0 : #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
636 0 : #define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
637 0 : #define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
638 0 : #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
639 0 : #define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
640 0 : #define TIMER0_CC2_PD4 SILABS_DBUS_TIMER0_CC2(0x3, 0x4)
641 0 : #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
642 0 : #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
643 0 : #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
644 0 : #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
645 0 : #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
646 0 : #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
647 0 : #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
648 0 : #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
649 0 : #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
650 0 : #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
651 0 : #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
652 0 : #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
653 0 : #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
654 0 : #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
655 0 : #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
656 0 : #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
657 0 : #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
658 0 : #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
659 0 : #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
660 0 : #define TIMER0_CDTI0_PD4 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x4)
661 0 : #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
662 0 : #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
663 0 : #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
664 0 : #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
665 0 : #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
666 0 : #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
667 0 : #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
668 0 : #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
669 0 : #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
670 0 : #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
671 0 : #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
672 0 : #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
673 0 : #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
674 0 : #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
675 0 : #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
676 0 : #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
677 0 : #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
678 0 : #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
679 0 : #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
680 0 : #define TIMER0_CDTI1_PD4 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x4)
681 0 : #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
682 0 : #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
683 0 : #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
684 0 : #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
685 0 : #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
686 0 : #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
687 0 : #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
688 0 : #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
689 0 : #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
690 0 : #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
691 0 : #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
692 0 : #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
693 0 : #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
694 0 : #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
695 0 : #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
696 0 : #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
697 0 : #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
698 0 : #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
699 0 : #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
700 0 : #define TIMER0_CDTI2_PD4 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x4)
701 :
702 0 : #define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
703 0 : #define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
704 0 : #define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
705 0 : #define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
706 0 : #define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
707 0 : #define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
708 0 : #define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
709 0 : #define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
710 0 : #define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
711 0 : #define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
712 0 : #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
713 0 : #define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
714 0 : #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
715 0 : #define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
716 0 : #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
717 0 : #define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
718 0 : #define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
719 0 : #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
720 0 : #define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
721 0 : #define TIMER1_CC0_PD4 SILABS_DBUS_TIMER1_CC0(0x3, 0x4)
722 0 : #define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
723 0 : #define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
724 0 : #define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
725 0 : #define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
726 0 : #define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
727 0 : #define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
728 0 : #define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
729 0 : #define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
730 0 : #define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
731 0 : #define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
732 0 : #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
733 0 : #define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
734 0 : #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
735 0 : #define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
736 0 : #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
737 0 : #define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
738 0 : #define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
739 0 : #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
740 0 : #define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
741 0 : #define TIMER1_CC1_PD4 SILABS_DBUS_TIMER1_CC1(0x3, 0x4)
742 0 : #define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
743 0 : #define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
744 0 : #define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
745 0 : #define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
746 0 : #define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
747 0 : #define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
748 0 : #define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
749 0 : #define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
750 0 : #define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
751 0 : #define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
752 0 : #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
753 0 : #define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
754 0 : #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
755 0 : #define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
756 0 : #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
757 0 : #define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
758 0 : #define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
759 0 : #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
760 0 : #define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
761 0 : #define TIMER1_CC2_PD4 SILABS_DBUS_TIMER1_CC2(0x3, 0x4)
762 0 : #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
763 0 : #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
764 0 : #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
765 0 : #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
766 0 : #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
767 0 : #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
768 0 : #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
769 0 : #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
770 0 : #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
771 0 : #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
772 0 : #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
773 0 : #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
774 0 : #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
775 0 : #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
776 0 : #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
777 0 : #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
778 0 : #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
779 0 : #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
780 0 : #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
781 0 : #define TIMER1_CDTI0_PD4 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x4)
782 0 : #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
783 0 : #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
784 0 : #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
785 0 : #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
786 0 : #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
787 0 : #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
788 0 : #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
789 0 : #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
790 0 : #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
791 0 : #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
792 0 : #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
793 0 : #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
794 0 : #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
795 0 : #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
796 0 : #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
797 0 : #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
798 0 : #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
799 0 : #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
800 0 : #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
801 0 : #define TIMER1_CDTI1_PD4 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x4)
802 0 : #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
803 0 : #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
804 0 : #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
805 0 : #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
806 0 : #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
807 0 : #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
808 0 : #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
809 0 : #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
810 0 : #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
811 0 : #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
812 0 : #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
813 0 : #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
814 0 : #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
815 0 : #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
816 0 : #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
817 0 : #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
818 0 : #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
819 0 : #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
820 0 : #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
821 0 : #define TIMER1_CDTI2_PD4 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x4)
822 :
823 0 : #define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
824 0 : #define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
825 0 : #define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
826 0 : #define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
827 0 : #define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
828 0 : #define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
829 0 : #define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
830 0 : #define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
831 0 : #define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
832 0 : #define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
833 0 : #define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
834 0 : #define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
835 0 : #define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
836 0 : #define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
837 0 : #define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
838 0 : #define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
839 0 : #define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
840 0 : #define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
841 0 : #define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
842 0 : #define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
843 0 : #define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
844 0 : #define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
845 0 : #define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
846 0 : #define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
847 0 : #define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
848 0 : #define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
849 0 : #define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
850 0 : #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
851 0 : #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
852 0 : #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
853 0 : #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
854 0 : #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
855 0 : #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
856 0 : #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
857 0 : #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
858 0 : #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
859 0 : #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
860 0 : #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
861 0 : #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
862 0 : #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
863 0 : #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
864 0 : #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
865 0 : #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
866 0 : #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
867 0 : #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
868 0 : #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
869 0 : #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
870 0 : #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
871 0 : #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
872 0 : #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
873 0 : #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
874 0 : #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
875 0 : #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
876 0 : #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
877 :
878 0 : #define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
879 0 : #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
880 0 : #define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
881 0 : #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
882 0 : #define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
883 0 : #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
884 0 : #define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
885 0 : #define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
886 0 : #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
887 0 : #define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
888 0 : #define TIMER3_CC0_PD4 SILABS_DBUS_TIMER3_CC0(0x3, 0x4)
889 0 : #define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
890 0 : #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
891 0 : #define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
892 0 : #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
893 0 : #define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
894 0 : #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
895 0 : #define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
896 0 : #define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
897 0 : #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
898 0 : #define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
899 0 : #define TIMER3_CC1_PD4 SILABS_DBUS_TIMER3_CC1(0x3, 0x4)
900 0 : #define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
901 0 : #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
902 0 : #define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
903 0 : #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
904 0 : #define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
905 0 : #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
906 0 : #define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
907 0 : #define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
908 0 : #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
909 0 : #define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
910 0 : #define TIMER3_CC2_PD4 SILABS_DBUS_TIMER3_CC2(0x3, 0x4)
911 0 : #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
912 0 : #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
913 0 : #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
914 0 : #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
915 0 : #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
916 0 : #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
917 0 : #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
918 0 : #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
919 0 : #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
920 0 : #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
921 0 : #define TIMER3_CDTI0_PD4 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x4)
922 0 : #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
923 0 : #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
924 0 : #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
925 0 : #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
926 0 : #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
927 0 : #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
928 0 : #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
929 0 : #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
930 0 : #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
931 0 : #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
932 0 : #define TIMER3_CDTI1_PD4 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x4)
933 0 : #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
934 0 : #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
935 0 : #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
936 0 : #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
937 0 : #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
938 0 : #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
939 0 : #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
940 0 : #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
941 0 : #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
942 0 : #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
943 0 : #define TIMER3_CDTI2_PD4 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x4)
944 :
945 0 : #define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0)
946 0 : #define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1)
947 0 : #define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2)
948 0 : #define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3)
949 0 : #define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4)
950 0 : #define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5)
951 0 : #define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6)
952 0 : #define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0)
953 0 : #define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1)
954 0 : #define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0)
955 0 : #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
956 0 : #define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2)
957 0 : #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
958 0 : #define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4)
959 0 : #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
960 0 : #define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0)
961 0 : #define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1)
962 0 : #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
963 0 : #define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3)
964 0 : #define USART0_CS_PD4 SILABS_DBUS_USART0_CS(0x3, 0x4)
965 0 : #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
966 0 : #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
967 0 : #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
968 0 : #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
969 0 : #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
970 0 : #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
971 0 : #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
972 0 : #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
973 0 : #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
974 0 : #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
975 0 : #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
976 0 : #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
977 0 : #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
978 0 : #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
979 0 : #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
980 0 : #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
981 0 : #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
982 0 : #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
983 0 : #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
984 0 : #define USART0_RTS_PD4 SILABS_DBUS_USART0_RTS(0x3, 0x4)
985 0 : #define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0)
986 0 : #define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1)
987 0 : #define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2)
988 0 : #define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3)
989 0 : #define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4)
990 0 : #define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5)
991 0 : #define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6)
992 0 : #define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0)
993 0 : #define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1)
994 0 : #define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0)
995 0 : #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
996 0 : #define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2)
997 0 : #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
998 0 : #define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4)
999 0 : #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
1000 0 : #define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0)
1001 0 : #define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1)
1002 0 : #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
1003 0 : #define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3)
1004 0 : #define USART0_RX_PD4 SILABS_DBUS_USART0_RX(0x3, 0x4)
1005 0 : #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
1006 0 : #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
1007 0 : #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
1008 0 : #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
1009 0 : #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
1010 0 : #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
1011 0 : #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
1012 0 : #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
1013 0 : #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
1014 0 : #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
1015 0 : #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
1016 0 : #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
1017 0 : #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
1018 0 : #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
1019 0 : #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
1020 0 : #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
1021 0 : #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
1022 0 : #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
1023 0 : #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
1024 0 : #define USART0_CLK_PD4 SILABS_DBUS_USART0_CLK(0x3, 0x4)
1025 0 : #define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0)
1026 0 : #define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1)
1027 0 : #define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2)
1028 0 : #define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3)
1029 0 : #define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4)
1030 0 : #define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5)
1031 0 : #define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6)
1032 0 : #define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0)
1033 0 : #define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1)
1034 0 : #define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0)
1035 0 : #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
1036 0 : #define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2)
1037 0 : #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
1038 0 : #define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4)
1039 0 : #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
1040 0 : #define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0)
1041 0 : #define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1)
1042 0 : #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
1043 0 : #define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3)
1044 0 : #define USART0_TX_PD4 SILABS_DBUS_USART0_TX(0x3, 0x4)
1045 0 : #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
1046 0 : #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
1047 0 : #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
1048 0 : #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
1049 0 : #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
1050 0 : #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
1051 0 : #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
1052 0 : #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
1053 0 : #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
1054 0 : #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
1055 0 : #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
1056 0 : #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
1057 0 : #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
1058 0 : #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
1059 0 : #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
1060 0 : #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
1061 0 : #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
1062 0 : #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
1063 0 : #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
1064 0 : #define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4)
1065 :
1066 0 : #define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0)
1067 0 : #define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1)
1068 0 : #define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2)
1069 0 : #define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3)
1070 0 : #define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4)
1071 0 : #define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5)
1072 0 : #define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6)
1073 0 : #define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0)
1074 0 : #define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1)
1075 0 : #define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0)
1076 0 : #define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1)
1077 0 : #define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2)
1078 0 : #define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3)
1079 0 : #define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4)
1080 0 : #define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5)
1081 0 : #define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
1082 0 : #define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0)
1083 0 : #define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1)
1084 0 : #define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0)
1085 0 : #define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1)
1086 0 : #define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2)
1087 0 : #define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3)
1088 0 : #define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4)
1089 0 : #define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5)
1090 0 : #define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6)
1091 0 : #define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0)
1092 0 : #define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1)
1093 0 : #define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0)
1094 0 : #define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1)
1095 0 : #define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2)
1096 0 : #define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3)
1097 0 : #define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4)
1098 0 : #define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5)
1099 0 : #define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
1100 0 : #define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0)
1101 0 : #define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1)
1102 0 : #define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0)
1103 0 : #define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1)
1104 0 : #define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2)
1105 0 : #define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3)
1106 0 : #define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4)
1107 0 : #define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5)
1108 0 : #define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6)
1109 0 : #define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0)
1110 0 : #define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1)
1111 0 : #define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0)
1112 0 : #define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1)
1113 0 : #define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2)
1114 0 : #define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3)
1115 0 : #define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4)
1116 0 : #define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5)
1117 0 : #define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)
1118 0 : #define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0)
1119 0 : #define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1)
1120 :
1121 0 : #define USART2_CS_PC0 SILABS_DBUS_USART2_CS(0x2, 0x0)
1122 0 : #define USART2_CS_PC1 SILABS_DBUS_USART2_CS(0x2, 0x1)
1123 0 : #define USART2_CS_PC2 SILABS_DBUS_USART2_CS(0x2, 0x2)
1124 0 : #define USART2_CS_PC3 SILABS_DBUS_USART2_CS(0x2, 0x3)
1125 0 : #define USART2_CS_PC4 SILABS_DBUS_USART2_CS(0x2, 0x4)
1126 0 : #define USART2_CS_PC5 SILABS_DBUS_USART2_CS(0x2, 0x5)
1127 0 : #define USART2_CS_PD0 SILABS_DBUS_USART2_CS(0x3, 0x0)
1128 0 : #define USART2_CS_PD1 SILABS_DBUS_USART2_CS(0x3, 0x1)
1129 0 : #define USART2_CS_PD2 SILABS_DBUS_USART2_CS(0x3, 0x2)
1130 0 : #define USART2_CS_PD3 SILABS_DBUS_USART2_CS(0x3, 0x3)
1131 0 : #define USART2_CS_PD4 SILABS_DBUS_USART2_CS(0x3, 0x4)
1132 0 : #define USART2_RTS_PC0 SILABS_DBUS_USART2_RTS(0x2, 0x0)
1133 0 : #define USART2_RTS_PC1 SILABS_DBUS_USART2_RTS(0x2, 0x1)
1134 0 : #define USART2_RTS_PC2 SILABS_DBUS_USART2_RTS(0x2, 0x2)
1135 0 : #define USART2_RTS_PC3 SILABS_DBUS_USART2_RTS(0x2, 0x3)
1136 0 : #define USART2_RTS_PC4 SILABS_DBUS_USART2_RTS(0x2, 0x4)
1137 0 : #define USART2_RTS_PC5 SILABS_DBUS_USART2_RTS(0x2, 0x5)
1138 0 : #define USART2_RTS_PD0 SILABS_DBUS_USART2_RTS(0x3, 0x0)
1139 0 : #define USART2_RTS_PD1 SILABS_DBUS_USART2_RTS(0x3, 0x1)
1140 0 : #define USART2_RTS_PD2 SILABS_DBUS_USART2_RTS(0x3, 0x2)
1141 0 : #define USART2_RTS_PD3 SILABS_DBUS_USART2_RTS(0x3, 0x3)
1142 0 : #define USART2_RTS_PD4 SILABS_DBUS_USART2_RTS(0x3, 0x4)
1143 0 : #define USART2_RX_PC0 SILABS_DBUS_USART2_RX(0x2, 0x0)
1144 0 : #define USART2_RX_PC1 SILABS_DBUS_USART2_RX(0x2, 0x1)
1145 0 : #define USART2_RX_PC2 SILABS_DBUS_USART2_RX(0x2, 0x2)
1146 0 : #define USART2_RX_PC3 SILABS_DBUS_USART2_RX(0x2, 0x3)
1147 0 : #define USART2_RX_PC4 SILABS_DBUS_USART2_RX(0x2, 0x4)
1148 0 : #define USART2_RX_PC5 SILABS_DBUS_USART2_RX(0x2, 0x5)
1149 0 : #define USART2_RX_PD0 SILABS_DBUS_USART2_RX(0x3, 0x0)
1150 0 : #define USART2_RX_PD1 SILABS_DBUS_USART2_RX(0x3, 0x1)
1151 0 : #define USART2_RX_PD2 SILABS_DBUS_USART2_RX(0x3, 0x2)
1152 0 : #define USART2_RX_PD3 SILABS_DBUS_USART2_RX(0x3, 0x3)
1153 0 : #define USART2_RX_PD4 SILABS_DBUS_USART2_RX(0x3, 0x4)
1154 0 : #define USART2_CLK_PC0 SILABS_DBUS_USART2_CLK(0x2, 0x0)
1155 0 : #define USART2_CLK_PC1 SILABS_DBUS_USART2_CLK(0x2, 0x1)
1156 0 : #define USART2_CLK_PC2 SILABS_DBUS_USART2_CLK(0x2, 0x2)
1157 0 : #define USART2_CLK_PC3 SILABS_DBUS_USART2_CLK(0x2, 0x3)
1158 0 : #define USART2_CLK_PC4 SILABS_DBUS_USART2_CLK(0x2, 0x4)
1159 0 : #define USART2_CLK_PC5 SILABS_DBUS_USART2_CLK(0x2, 0x5)
1160 0 : #define USART2_CLK_PD0 SILABS_DBUS_USART2_CLK(0x3, 0x0)
1161 0 : #define USART2_CLK_PD1 SILABS_DBUS_USART2_CLK(0x3, 0x1)
1162 0 : #define USART2_CLK_PD2 SILABS_DBUS_USART2_CLK(0x3, 0x2)
1163 0 : #define USART2_CLK_PD3 SILABS_DBUS_USART2_CLK(0x3, 0x3)
1164 0 : #define USART2_CLK_PD4 SILABS_DBUS_USART2_CLK(0x3, 0x4)
1165 0 : #define USART2_TX_PC0 SILABS_DBUS_USART2_TX(0x2, 0x0)
1166 0 : #define USART2_TX_PC1 SILABS_DBUS_USART2_TX(0x2, 0x1)
1167 0 : #define USART2_TX_PC2 SILABS_DBUS_USART2_TX(0x2, 0x2)
1168 0 : #define USART2_TX_PC3 SILABS_DBUS_USART2_TX(0x2, 0x3)
1169 0 : #define USART2_TX_PC4 SILABS_DBUS_USART2_TX(0x2, 0x4)
1170 0 : #define USART2_TX_PC5 SILABS_DBUS_USART2_TX(0x2, 0x5)
1171 0 : #define USART2_TX_PD0 SILABS_DBUS_USART2_TX(0x3, 0x0)
1172 0 : #define USART2_TX_PD1 SILABS_DBUS_USART2_TX(0x3, 0x1)
1173 0 : #define USART2_TX_PD2 SILABS_DBUS_USART2_TX(0x3, 0x2)
1174 0 : #define USART2_TX_PD3 SILABS_DBUS_USART2_TX(0x3, 0x3)
1175 0 : #define USART2_TX_PD4 SILABS_DBUS_USART2_TX(0x3, 0x4)
1176 0 : #define USART2_CTS_PC0 SILABS_DBUS_USART2_CTS(0x2, 0x0)
1177 0 : #define USART2_CTS_PC1 SILABS_DBUS_USART2_CTS(0x2, 0x1)
1178 0 : #define USART2_CTS_PC2 SILABS_DBUS_USART2_CTS(0x2, 0x2)
1179 0 : #define USART2_CTS_PC3 SILABS_DBUS_USART2_CTS(0x2, 0x3)
1180 0 : #define USART2_CTS_PC4 SILABS_DBUS_USART2_CTS(0x2, 0x4)
1181 0 : #define USART2_CTS_PC5 SILABS_DBUS_USART2_CTS(0x2, 0x5)
1182 0 : #define USART2_CTS_PD0 SILABS_DBUS_USART2_CTS(0x3, 0x0)
1183 0 : #define USART2_CTS_PD1 SILABS_DBUS_USART2_CTS(0x3, 0x1)
1184 0 : #define USART2_CTS_PD2 SILABS_DBUS_USART2_CTS(0x3, 0x2)
1185 0 : #define USART2_CTS_PD3 SILABS_DBUS_USART2_CTS(0x3, 0x3)
1186 0 : #define USART2_CTS_PD4 SILABS_DBUS_USART2_CTS(0x3, 0x4)
1187 :
1188 : #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_ */
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