LCOV - code coverage report
Current view: top level - zephyr/dt-bindings/pinctrl/silabs - xg22-pinctrl.h Coverage Total Hit
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Test Date: 2025-09-05 16:43:28

            Line data    Source code
       1            0 : /*
       2              :  * Copyright (c) 2025 Silicon Laboratories Inc.
       3              :  * SPDX-License-Identifier: Apache-2.0
       4              :  *
       5              :  * Pin Control for Silicon Labs XG22 devices
       6              :  *
       7              :  * This file was generated by the script gen_pinctrl.py in the hal_silabs module.
       8              :  * Do not manually edit.
       9              :  */
      10              : 
      11              : #ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_
      12              : #define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_
      13              : 
      14              : #include <zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
      15              : 
      16            0 : #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2)
      17            0 : #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 4, 1, 1, 3)
      18            0 : #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 4, 1, 2, 4)
      19            0 : #define SILABS_DBUS_CMU_CLKIN0(port, pin)  SILABS_DBUS(port, pin, 4, 0, 0, 1)
      20              : 
      21            0 : #define SILABS_DBUS_PTI_DCLK(port, pin)   SILABS_DBUS(port, pin, 15, 1, 0, 1)
      22            0 : #define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 15, 1, 1, 2)
      23            0 : #define SILABS_DBUS_PTI_DOUT(port, pin)   SILABS_DBUS(port, pin, 15, 1, 2, 3)
      24              : 
      25            0 : #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 20, 1, 0, 1)
      26            0 : #define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 20, 1, 1, 2)
      27              : 
      28            0 : #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 24, 1, 0, 1)
      29            0 : #define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 24, 1, 1, 2)
      30              : 
      31            0 : #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 28, 1, 0, 1)
      32            0 : #define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 28, 1, 1, 2)
      33              : 
      34            0 : #define SILABS_DBUS_EUART0_RTS(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 2)
      35            0 : #define SILABS_DBUS_EUART0_TX(port, pin)  SILABS_DBUS(port, pin, 32, 1, 1, 4)
      36            0 : #define SILABS_DBUS_EUART0_CTS(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 1)
      37            0 : #define SILABS_DBUS_EUART0_RX(port, pin)  SILABS_DBUS(port, pin, 32, 0, 0, 3)
      38              : 
      39            0 : #define SILABS_DBUS_MODEM_ANT0(port, pin)        SILABS_DBUS(port, pin, 38, 1, 0, 1)
      40            0 : #define SILABS_DBUS_MODEM_ANT1(port, pin)        SILABS_DBUS(port, pin, 38, 1, 1, 2)
      41            0 : #define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 38, 1, 2, 3)
      42            0 : #define SILABS_DBUS_MODEM_ANTRR0(port, pin)      SILABS_DBUS(port, pin, 38, 1, 3, 4)
      43            0 : #define SILABS_DBUS_MODEM_ANTRR1(port, pin)      SILABS_DBUS(port, pin, 38, 1, 4, 5)
      44            0 : #define SILABS_DBUS_MODEM_ANTRR2(port, pin)      SILABS_DBUS(port, pin, 38, 1, 5, 6)
      45            0 : #define SILABS_DBUS_MODEM_ANTRR3(port, pin)      SILABS_DBUS(port, pin, 38, 1, 6, 7)
      46            0 : #define SILABS_DBUS_MODEM_ANTRR4(port, pin)      SILABS_DBUS(port, pin, 38, 1, 7, 8)
      47            0 : #define SILABS_DBUS_MODEM_ANTRR5(port, pin)      SILABS_DBUS(port, pin, 38, 1, 8, 9)
      48            0 : #define SILABS_DBUS_MODEM_ANTSWEN(port, pin)     SILABS_DBUS(port, pin, 38, 1, 9, 10)
      49            0 : #define SILABS_DBUS_MODEM_ANTSWUS(port, pin)     SILABS_DBUS(port, pin, 38, 1, 10, 11)
      50            0 : #define SILABS_DBUS_MODEM_ANTTRIG(port, pin)     SILABS_DBUS(port, pin, 38, 1, 11, 12)
      51            0 : #define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 38, 1, 12, 13)
      52            0 : #define SILABS_DBUS_MODEM_DCLK(port, pin)        SILABS_DBUS(port, pin, 38, 1, 13, 14)
      53            0 : #define SILABS_DBUS_MODEM_DOUT(port, pin)        SILABS_DBUS(port, pin, 38, 1, 14, 16)
      54            0 : #define SILABS_DBUS_MODEM_DIN(port, pin)         SILABS_DBUS(port, pin, 38, 0, 0, 15)
      55              : 
      56            0 : #define SILABS_DBUS_PDM_CLK(port, pin)  SILABS_DBUS(port, pin, 56, 1, 0, 1)
      57            0 : #define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 56, 0, 0, 2)
      58            0 : #define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 56, 0, 0, 3)
      59              : 
      60            0 : #define SILABS_DBUS_PRS0_ASYNCH0(port, pin)  SILABS_DBUS(port, pin, 61, 1, 0, 1)
      61            0 : #define SILABS_DBUS_PRS0_ASYNCH1(port, pin)  SILABS_DBUS(port, pin, 61, 1, 1, 2)
      62            0 : #define SILABS_DBUS_PRS0_ASYNCH2(port, pin)  SILABS_DBUS(port, pin, 61, 1, 2, 3)
      63            0 : #define SILABS_DBUS_PRS0_ASYNCH3(port, pin)  SILABS_DBUS(port, pin, 61, 1, 3, 4)
      64            0 : #define SILABS_DBUS_PRS0_ASYNCH4(port, pin)  SILABS_DBUS(port, pin, 61, 1, 4, 5)
      65            0 : #define SILABS_DBUS_PRS0_ASYNCH5(port, pin)  SILABS_DBUS(port, pin, 61, 1, 5, 6)
      66            0 : #define SILABS_DBUS_PRS0_ASYNCH6(port, pin)  SILABS_DBUS(port, pin, 61, 1, 6, 7)
      67            0 : #define SILABS_DBUS_PRS0_ASYNCH7(port, pin)  SILABS_DBUS(port, pin, 61, 1, 7, 8)
      68            0 : #define SILABS_DBUS_PRS0_ASYNCH8(port, pin)  SILABS_DBUS(port, pin, 61, 1, 8, 9)
      69            0 : #define SILABS_DBUS_PRS0_ASYNCH9(port, pin)  SILABS_DBUS(port, pin, 61, 1, 9, 10)
      70            0 : #define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 61, 1, 10, 11)
      71            0 : #define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 61, 1, 11, 12)
      72            0 : #define SILABS_DBUS_PRS0_SYNCH0(port, pin)   SILABS_DBUS(port, pin, 61, 1, 12, 13)
      73            0 : #define SILABS_DBUS_PRS0_SYNCH1(port, pin)   SILABS_DBUS(port, pin, 61, 1, 13, 14)
      74            0 : #define SILABS_DBUS_PRS0_SYNCH2(port, pin)   SILABS_DBUS(port, pin, 61, 1, 14, 15)
      75            0 : #define SILABS_DBUS_PRS0_SYNCH3(port, pin)   SILABS_DBUS(port, pin, 61, 1, 15, 16)
      76              : 
      77            0 : #define SILABS_DBUS_TIMER0_CC0(port, pin)   SILABS_DBUS(port, pin, 79, 1, 0, 1)
      78            0 : #define SILABS_DBUS_TIMER0_CC1(port, pin)   SILABS_DBUS(port, pin, 79, 1, 1, 2)
      79            0 : #define SILABS_DBUS_TIMER0_CC2(port, pin)   SILABS_DBUS(port, pin, 79, 1, 2, 3)
      80            0 : #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 79, 1, 3, 4)
      81            0 : #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 79, 1, 4, 5)
      82            0 : #define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 79, 1, 5, 6)
      83              : 
      84            0 : #define SILABS_DBUS_TIMER1_CC0(port, pin)   SILABS_DBUS(port, pin, 87, 1, 0, 1)
      85            0 : #define SILABS_DBUS_TIMER1_CC1(port, pin)   SILABS_DBUS(port, pin, 87, 1, 1, 2)
      86            0 : #define SILABS_DBUS_TIMER1_CC2(port, pin)   SILABS_DBUS(port, pin, 87, 1, 2, 3)
      87            0 : #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 87, 1, 3, 4)
      88            0 : #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 87, 1, 4, 5)
      89            0 : #define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 87, 1, 5, 6)
      90              : 
      91            0 : #define SILABS_DBUS_TIMER2_CC0(port, pin)   SILABS_DBUS(port, pin, 95, 1, 0, 1)
      92            0 : #define SILABS_DBUS_TIMER2_CC1(port, pin)   SILABS_DBUS(port, pin, 95, 1, 1, 2)
      93            0 : #define SILABS_DBUS_TIMER2_CC2(port, pin)   SILABS_DBUS(port, pin, 95, 1, 2, 3)
      94            0 : #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 95, 1, 3, 4)
      95            0 : #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 95, 1, 4, 5)
      96            0 : #define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 95, 1, 5, 6)
      97              : 
      98            0 : #define SILABS_DBUS_TIMER3_CC0(port, pin)   SILABS_DBUS(port, pin, 103, 1, 0, 1)
      99            0 : #define SILABS_DBUS_TIMER3_CC1(port, pin)   SILABS_DBUS(port, pin, 103, 1, 1, 2)
     100            0 : #define SILABS_DBUS_TIMER3_CC2(port, pin)   SILABS_DBUS(port, pin, 103, 1, 2, 3)
     101            0 : #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 103, 1, 3, 4)
     102            0 : #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 103, 1, 4, 5)
     103            0 : #define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 103, 1, 5, 6)
     104              : 
     105            0 : #define SILABS_DBUS_TIMER4_CC0(port, pin)   SILABS_DBUS(port, pin, 111, 1, 0, 1)
     106            0 : #define SILABS_DBUS_TIMER4_CC1(port, pin)   SILABS_DBUS(port, pin, 111, 1, 1, 2)
     107            0 : #define SILABS_DBUS_TIMER4_CC2(port, pin)   SILABS_DBUS(port, pin, 111, 1, 2, 3)
     108            0 : #define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 111, 1, 3, 4)
     109            0 : #define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 111, 1, 4, 5)
     110            0 : #define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 111, 1, 5, 6)
     111              : 
     112            0 : #define SILABS_DBUS_USART0_CS(port, pin)  SILABS_DBUS(port, pin, 119, 1, 0, 1)
     113            0 : #define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 119, 1, 1, 3)
     114            0 : #define SILABS_DBUS_USART0_RX(port, pin)  SILABS_DBUS(port, pin, 119, 1, 2, 4)
     115            0 : #define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 119, 1, 3, 5)
     116            0 : #define SILABS_DBUS_USART0_TX(port, pin)  SILABS_DBUS(port, pin, 119, 1, 4, 6)
     117            0 : #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 119, 0, 0, 2)
     118              : 
     119            0 : #define SILABS_DBUS_USART1_CS(port, pin)  SILABS_DBUS(port, pin, 127, 1, 0, 1)
     120            0 : #define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 127, 1, 1, 3)
     121            0 : #define SILABS_DBUS_USART1_RX(port, pin)  SILABS_DBUS(port, pin, 127, 1, 2, 4)
     122            0 : #define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 127, 1, 3, 5)
     123            0 : #define SILABS_DBUS_USART1_TX(port, pin)  SILABS_DBUS(port, pin, 127, 1, 4, 6)
     124            0 : #define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 2)
     125              : 
     126            0 : #define GPIO_SWCLKTCK_PA1   SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
     127            0 : #define GPIO_SWDIOTMS_PA2   SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
     128            0 : #define GPIO_TDO_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
     129            0 : #define GPIO_TDI_PA4        SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
     130            0 : #define GPIO_SWV_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
     131            0 : #define GPIO_TRACECLK_PA4   SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
     132            0 : #define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
     133              : 
     134            0 : #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
     135            0 : #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
     136            0 : #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
     137            0 : #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
     138            0 : #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
     139            0 : #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
     140            0 : #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
     141            0 : #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
     142            0 : #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
     143            0 : #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
     144            0 : #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
     145            0 : #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
     146            0 : #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
     147            0 : #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
     148            0 : #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
     149            0 : #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
     150            0 : #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
     151            0 : #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
     152            0 : #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
     153            0 : #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
     154            0 : #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
     155            0 : #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
     156            0 : #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
     157            0 : #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
     158            0 : #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
     159            0 : #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
     160            0 : #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
     161            0 : #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
     162            0 : #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
     163            0 : #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
     164            0 : #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
     165            0 : #define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
     166            0 : #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
     167            0 : #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
     168            0 : #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
     169            0 : #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
     170            0 : #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
     171            0 : #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
     172            0 : #define CMU_CLKIN0_PC0  SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
     173            0 : #define CMU_CLKIN0_PC1  SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
     174            0 : #define CMU_CLKIN0_PC2  SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
     175            0 : #define CMU_CLKIN0_PC3  SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
     176            0 : #define CMU_CLKIN0_PC4  SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
     177            0 : #define CMU_CLKIN0_PC5  SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
     178            0 : #define CMU_CLKIN0_PC6  SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
     179            0 : #define CMU_CLKIN0_PC7  SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
     180            0 : #define CMU_CLKIN0_PD0  SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
     181            0 : #define CMU_CLKIN0_PD1  SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
     182            0 : #define CMU_CLKIN0_PD2  SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
     183            0 : #define CMU_CLKIN0_PD3  SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
     184              : 
     185            0 : #define PTI_DCLK_PC0   SILABS_DBUS_PTI_DCLK(0x2, 0x0)
     186            0 : #define PTI_DCLK_PC1   SILABS_DBUS_PTI_DCLK(0x2, 0x1)
     187            0 : #define PTI_DCLK_PC2   SILABS_DBUS_PTI_DCLK(0x2, 0x2)
     188            0 : #define PTI_DCLK_PC3   SILABS_DBUS_PTI_DCLK(0x2, 0x3)
     189            0 : #define PTI_DCLK_PC4   SILABS_DBUS_PTI_DCLK(0x2, 0x4)
     190            0 : #define PTI_DCLK_PC5   SILABS_DBUS_PTI_DCLK(0x2, 0x5)
     191            0 : #define PTI_DCLK_PC6   SILABS_DBUS_PTI_DCLK(0x2, 0x6)
     192            0 : #define PTI_DCLK_PC7   SILABS_DBUS_PTI_DCLK(0x2, 0x7)
     193            0 : #define PTI_DCLK_PD0   SILABS_DBUS_PTI_DCLK(0x3, 0x0)
     194            0 : #define PTI_DCLK_PD1   SILABS_DBUS_PTI_DCLK(0x3, 0x1)
     195            0 : #define PTI_DCLK_PD2   SILABS_DBUS_PTI_DCLK(0x3, 0x2)
     196            0 : #define PTI_DCLK_PD3   SILABS_DBUS_PTI_DCLK(0x3, 0x3)
     197            0 : #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
     198            0 : #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
     199            0 : #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
     200            0 : #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
     201            0 : #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
     202            0 : #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
     203            0 : #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
     204            0 : #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
     205            0 : #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
     206            0 : #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
     207            0 : #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
     208            0 : #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
     209            0 : #define PTI_DOUT_PC0   SILABS_DBUS_PTI_DOUT(0x2, 0x0)
     210            0 : #define PTI_DOUT_PC1   SILABS_DBUS_PTI_DOUT(0x2, 0x1)
     211            0 : #define PTI_DOUT_PC2   SILABS_DBUS_PTI_DOUT(0x2, 0x2)
     212            0 : #define PTI_DOUT_PC3   SILABS_DBUS_PTI_DOUT(0x2, 0x3)
     213            0 : #define PTI_DOUT_PC4   SILABS_DBUS_PTI_DOUT(0x2, 0x4)
     214            0 : #define PTI_DOUT_PC5   SILABS_DBUS_PTI_DOUT(0x2, 0x5)
     215            0 : #define PTI_DOUT_PC6   SILABS_DBUS_PTI_DOUT(0x2, 0x6)
     216            0 : #define PTI_DOUT_PC7   SILABS_DBUS_PTI_DOUT(0x2, 0x7)
     217            0 : #define PTI_DOUT_PD0   SILABS_DBUS_PTI_DOUT(0x3, 0x0)
     218            0 : #define PTI_DOUT_PD1   SILABS_DBUS_PTI_DOUT(0x3, 0x1)
     219            0 : #define PTI_DOUT_PD2   SILABS_DBUS_PTI_DOUT(0x3, 0x2)
     220            0 : #define PTI_DOUT_PD3   SILABS_DBUS_PTI_DOUT(0x3, 0x3)
     221              : 
     222            0 : #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
     223            0 : #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
     224            0 : #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
     225            0 : #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
     226            0 : #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
     227            0 : #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
     228            0 : #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
     229            0 : #define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
     230            0 : #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
     231            0 : #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
     232            0 : #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
     233            0 : #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
     234            0 : #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
     235            0 : #define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
     236            0 : #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
     237            0 : #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
     238            0 : #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
     239            0 : #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
     240            0 : #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
     241            0 : #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
     242            0 : #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
     243            0 : #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
     244            0 : #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
     245            0 : #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
     246            0 : #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
     247            0 : #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
     248            0 : #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
     249            0 : #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
     250            0 : #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
     251            0 : #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
     252            0 : #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
     253            0 : #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
     254            0 : #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
     255            0 : #define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
     256            0 : #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
     257            0 : #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
     258            0 : #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
     259            0 : #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
     260            0 : #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
     261            0 : #define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
     262            0 : #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
     263            0 : #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
     264            0 : #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
     265            0 : #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
     266            0 : #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
     267            0 : #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
     268            0 : #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
     269            0 : #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
     270            0 : #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
     271            0 : #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
     272            0 : #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
     273            0 : #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
     274              : 
     275            0 : #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
     276            0 : #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
     277            0 : #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
     278            0 : #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
     279            0 : #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
     280            0 : #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
     281            0 : #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
     282            0 : #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
     283            0 : #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
     284            0 : #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
     285            0 : #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
     286            0 : #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
     287            0 : #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
     288            0 : #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
     289            0 : #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
     290            0 : #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
     291            0 : #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
     292            0 : #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
     293            0 : #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
     294            0 : #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
     295            0 : #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
     296            0 : #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
     297            0 : #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
     298            0 : #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
     299              : 
     300            0 : #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
     301            0 : #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
     302            0 : #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
     303            0 : #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
     304            0 : #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
     305            0 : #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
     306            0 : #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
     307            0 : #define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
     308            0 : #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
     309            0 : #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
     310            0 : #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
     311            0 : #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
     312            0 : #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
     313            0 : #define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
     314            0 : #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
     315            0 : #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
     316            0 : #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
     317            0 : #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
     318            0 : #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
     319            0 : #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
     320            0 : #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
     321            0 : #define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
     322            0 : #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
     323            0 : #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
     324            0 : #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
     325            0 : #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
     326            0 : #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
     327            0 : #define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
     328              : 
     329            0 : #define EUART0_RTS_PA0 SILABS_DBUS_EUART0_RTS(0x0, 0x0)
     330            0 : #define EUART0_RTS_PA1 SILABS_DBUS_EUART0_RTS(0x0, 0x1)
     331            0 : #define EUART0_RTS_PA2 SILABS_DBUS_EUART0_RTS(0x0, 0x2)
     332            0 : #define EUART0_RTS_PA3 SILABS_DBUS_EUART0_RTS(0x0, 0x3)
     333            0 : #define EUART0_RTS_PA4 SILABS_DBUS_EUART0_RTS(0x0, 0x4)
     334            0 : #define EUART0_RTS_PA5 SILABS_DBUS_EUART0_RTS(0x0, 0x5)
     335            0 : #define EUART0_RTS_PA6 SILABS_DBUS_EUART0_RTS(0x0, 0x6)
     336            0 : #define EUART0_RTS_PA7 SILABS_DBUS_EUART0_RTS(0x0, 0x7)
     337            0 : #define EUART0_RTS_PA8 SILABS_DBUS_EUART0_RTS(0x0, 0x8)
     338            0 : #define EUART0_RTS_PB0 SILABS_DBUS_EUART0_RTS(0x1, 0x0)
     339            0 : #define EUART0_RTS_PB1 SILABS_DBUS_EUART0_RTS(0x1, 0x1)
     340            0 : #define EUART0_RTS_PB2 SILABS_DBUS_EUART0_RTS(0x1, 0x2)
     341            0 : #define EUART0_RTS_PB3 SILABS_DBUS_EUART0_RTS(0x1, 0x3)
     342            0 : #define EUART0_RTS_PB4 SILABS_DBUS_EUART0_RTS(0x1, 0x4)
     343            0 : #define EUART0_RTS_PC0 SILABS_DBUS_EUART0_RTS(0x2, 0x0)
     344            0 : #define EUART0_RTS_PC1 SILABS_DBUS_EUART0_RTS(0x2, 0x1)
     345            0 : #define EUART0_RTS_PC2 SILABS_DBUS_EUART0_RTS(0x2, 0x2)
     346            0 : #define EUART0_RTS_PC3 SILABS_DBUS_EUART0_RTS(0x2, 0x3)
     347            0 : #define EUART0_RTS_PC4 SILABS_DBUS_EUART0_RTS(0x2, 0x4)
     348            0 : #define EUART0_RTS_PC5 SILABS_DBUS_EUART0_RTS(0x2, 0x5)
     349            0 : #define EUART0_RTS_PC6 SILABS_DBUS_EUART0_RTS(0x2, 0x6)
     350            0 : #define EUART0_RTS_PC7 SILABS_DBUS_EUART0_RTS(0x2, 0x7)
     351            0 : #define EUART0_RTS_PD0 SILABS_DBUS_EUART0_RTS(0x3, 0x0)
     352            0 : #define EUART0_RTS_PD1 SILABS_DBUS_EUART0_RTS(0x3, 0x1)
     353            0 : #define EUART0_RTS_PD2 SILABS_DBUS_EUART0_RTS(0x3, 0x2)
     354            0 : #define EUART0_RTS_PD3 SILABS_DBUS_EUART0_RTS(0x3, 0x3)
     355            0 : #define EUART0_TX_PA0  SILABS_DBUS_EUART0_TX(0x0, 0x0)
     356            0 : #define EUART0_TX_PA1  SILABS_DBUS_EUART0_TX(0x0, 0x1)
     357            0 : #define EUART0_TX_PA2  SILABS_DBUS_EUART0_TX(0x0, 0x2)
     358            0 : #define EUART0_TX_PA3  SILABS_DBUS_EUART0_TX(0x0, 0x3)
     359            0 : #define EUART0_TX_PA4  SILABS_DBUS_EUART0_TX(0x0, 0x4)
     360            0 : #define EUART0_TX_PA5  SILABS_DBUS_EUART0_TX(0x0, 0x5)
     361            0 : #define EUART0_TX_PA6  SILABS_DBUS_EUART0_TX(0x0, 0x6)
     362            0 : #define EUART0_TX_PA7  SILABS_DBUS_EUART0_TX(0x0, 0x7)
     363            0 : #define EUART0_TX_PA8  SILABS_DBUS_EUART0_TX(0x0, 0x8)
     364            0 : #define EUART0_TX_PB0  SILABS_DBUS_EUART0_TX(0x1, 0x0)
     365            0 : #define EUART0_TX_PB1  SILABS_DBUS_EUART0_TX(0x1, 0x1)
     366            0 : #define EUART0_TX_PB2  SILABS_DBUS_EUART0_TX(0x1, 0x2)
     367            0 : #define EUART0_TX_PB3  SILABS_DBUS_EUART0_TX(0x1, 0x3)
     368            0 : #define EUART0_TX_PB4  SILABS_DBUS_EUART0_TX(0x1, 0x4)
     369            0 : #define EUART0_TX_PC0  SILABS_DBUS_EUART0_TX(0x2, 0x0)
     370            0 : #define EUART0_TX_PC1  SILABS_DBUS_EUART0_TX(0x2, 0x1)
     371            0 : #define EUART0_TX_PC2  SILABS_DBUS_EUART0_TX(0x2, 0x2)
     372            0 : #define EUART0_TX_PC3  SILABS_DBUS_EUART0_TX(0x2, 0x3)
     373            0 : #define EUART0_TX_PC4  SILABS_DBUS_EUART0_TX(0x2, 0x4)
     374            0 : #define EUART0_TX_PC5  SILABS_DBUS_EUART0_TX(0x2, 0x5)
     375            0 : #define EUART0_TX_PC6  SILABS_DBUS_EUART0_TX(0x2, 0x6)
     376            0 : #define EUART0_TX_PC7  SILABS_DBUS_EUART0_TX(0x2, 0x7)
     377            0 : #define EUART0_TX_PD0  SILABS_DBUS_EUART0_TX(0x3, 0x0)
     378            0 : #define EUART0_TX_PD1  SILABS_DBUS_EUART0_TX(0x3, 0x1)
     379            0 : #define EUART0_TX_PD2  SILABS_DBUS_EUART0_TX(0x3, 0x2)
     380            0 : #define EUART0_TX_PD3  SILABS_DBUS_EUART0_TX(0x3, 0x3)
     381            0 : #define EUART0_CTS_PA0 SILABS_DBUS_EUART0_CTS(0x0, 0x0)
     382            0 : #define EUART0_CTS_PA1 SILABS_DBUS_EUART0_CTS(0x0, 0x1)
     383            0 : #define EUART0_CTS_PA2 SILABS_DBUS_EUART0_CTS(0x0, 0x2)
     384            0 : #define EUART0_CTS_PA3 SILABS_DBUS_EUART0_CTS(0x0, 0x3)
     385            0 : #define EUART0_CTS_PA4 SILABS_DBUS_EUART0_CTS(0x0, 0x4)
     386            0 : #define EUART0_CTS_PA5 SILABS_DBUS_EUART0_CTS(0x0, 0x5)
     387            0 : #define EUART0_CTS_PA6 SILABS_DBUS_EUART0_CTS(0x0, 0x6)
     388            0 : #define EUART0_CTS_PA7 SILABS_DBUS_EUART0_CTS(0x0, 0x7)
     389            0 : #define EUART0_CTS_PA8 SILABS_DBUS_EUART0_CTS(0x0, 0x8)
     390            0 : #define EUART0_CTS_PB0 SILABS_DBUS_EUART0_CTS(0x1, 0x0)
     391            0 : #define EUART0_CTS_PB1 SILABS_DBUS_EUART0_CTS(0x1, 0x1)
     392            0 : #define EUART0_CTS_PB2 SILABS_DBUS_EUART0_CTS(0x1, 0x2)
     393            0 : #define EUART0_CTS_PB3 SILABS_DBUS_EUART0_CTS(0x1, 0x3)
     394            0 : #define EUART0_CTS_PB4 SILABS_DBUS_EUART0_CTS(0x1, 0x4)
     395            0 : #define EUART0_CTS_PC0 SILABS_DBUS_EUART0_CTS(0x2, 0x0)
     396            0 : #define EUART0_CTS_PC1 SILABS_DBUS_EUART0_CTS(0x2, 0x1)
     397            0 : #define EUART0_CTS_PC2 SILABS_DBUS_EUART0_CTS(0x2, 0x2)
     398            0 : #define EUART0_CTS_PC3 SILABS_DBUS_EUART0_CTS(0x2, 0x3)
     399            0 : #define EUART0_CTS_PC4 SILABS_DBUS_EUART0_CTS(0x2, 0x4)
     400            0 : #define EUART0_CTS_PC5 SILABS_DBUS_EUART0_CTS(0x2, 0x5)
     401            0 : #define EUART0_CTS_PC6 SILABS_DBUS_EUART0_CTS(0x2, 0x6)
     402            0 : #define EUART0_CTS_PC7 SILABS_DBUS_EUART0_CTS(0x2, 0x7)
     403            0 : #define EUART0_CTS_PD0 SILABS_DBUS_EUART0_CTS(0x3, 0x0)
     404            0 : #define EUART0_CTS_PD1 SILABS_DBUS_EUART0_CTS(0x3, 0x1)
     405            0 : #define EUART0_CTS_PD2 SILABS_DBUS_EUART0_CTS(0x3, 0x2)
     406            0 : #define EUART0_CTS_PD3 SILABS_DBUS_EUART0_CTS(0x3, 0x3)
     407            0 : #define EUART0_RX_PA0  SILABS_DBUS_EUART0_RX(0x0, 0x0)
     408            0 : #define EUART0_RX_PA1  SILABS_DBUS_EUART0_RX(0x0, 0x1)
     409            0 : #define EUART0_RX_PA2  SILABS_DBUS_EUART0_RX(0x0, 0x2)
     410            0 : #define EUART0_RX_PA3  SILABS_DBUS_EUART0_RX(0x0, 0x3)
     411            0 : #define EUART0_RX_PA4  SILABS_DBUS_EUART0_RX(0x0, 0x4)
     412            0 : #define EUART0_RX_PA5  SILABS_DBUS_EUART0_RX(0x0, 0x5)
     413            0 : #define EUART0_RX_PA6  SILABS_DBUS_EUART0_RX(0x0, 0x6)
     414            0 : #define EUART0_RX_PA7  SILABS_DBUS_EUART0_RX(0x0, 0x7)
     415            0 : #define EUART0_RX_PA8  SILABS_DBUS_EUART0_RX(0x0, 0x8)
     416            0 : #define EUART0_RX_PB0  SILABS_DBUS_EUART0_RX(0x1, 0x0)
     417            0 : #define EUART0_RX_PB1  SILABS_DBUS_EUART0_RX(0x1, 0x1)
     418            0 : #define EUART0_RX_PB2  SILABS_DBUS_EUART0_RX(0x1, 0x2)
     419            0 : #define EUART0_RX_PB3  SILABS_DBUS_EUART0_RX(0x1, 0x3)
     420            0 : #define EUART0_RX_PB4  SILABS_DBUS_EUART0_RX(0x1, 0x4)
     421            0 : #define EUART0_RX_PC0  SILABS_DBUS_EUART0_RX(0x2, 0x0)
     422            0 : #define EUART0_RX_PC1  SILABS_DBUS_EUART0_RX(0x2, 0x1)
     423            0 : #define EUART0_RX_PC2  SILABS_DBUS_EUART0_RX(0x2, 0x2)
     424            0 : #define EUART0_RX_PC3  SILABS_DBUS_EUART0_RX(0x2, 0x3)
     425            0 : #define EUART0_RX_PC4  SILABS_DBUS_EUART0_RX(0x2, 0x4)
     426            0 : #define EUART0_RX_PC5  SILABS_DBUS_EUART0_RX(0x2, 0x5)
     427            0 : #define EUART0_RX_PC6  SILABS_DBUS_EUART0_RX(0x2, 0x6)
     428            0 : #define EUART0_RX_PC7  SILABS_DBUS_EUART0_RX(0x2, 0x7)
     429            0 : #define EUART0_RX_PD0  SILABS_DBUS_EUART0_RX(0x3, 0x0)
     430            0 : #define EUART0_RX_PD1  SILABS_DBUS_EUART0_RX(0x3, 0x1)
     431            0 : #define EUART0_RX_PD2  SILABS_DBUS_EUART0_RX(0x3, 0x2)
     432            0 : #define EUART0_RX_PD3  SILABS_DBUS_EUART0_RX(0x3, 0x3)
     433              : 
     434            0 : #define MODEM_ANT0_PA0        SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
     435            0 : #define MODEM_ANT0_PA1        SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
     436            0 : #define MODEM_ANT0_PA2        SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
     437            0 : #define MODEM_ANT0_PA3        SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
     438            0 : #define MODEM_ANT0_PA4        SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
     439            0 : #define MODEM_ANT0_PA5        SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
     440            0 : #define MODEM_ANT0_PA6        SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
     441            0 : #define MODEM_ANT0_PA7        SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
     442            0 : #define MODEM_ANT0_PA8        SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
     443            0 : #define MODEM_ANT0_PB0        SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
     444            0 : #define MODEM_ANT0_PB1        SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
     445            0 : #define MODEM_ANT0_PB2        SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
     446            0 : #define MODEM_ANT0_PB3        SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
     447            0 : #define MODEM_ANT0_PB4        SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
     448            0 : #define MODEM_ANT0_PC0        SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
     449            0 : #define MODEM_ANT0_PC1        SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
     450            0 : #define MODEM_ANT0_PC2        SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
     451            0 : #define MODEM_ANT0_PC3        SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
     452            0 : #define MODEM_ANT0_PC4        SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
     453            0 : #define MODEM_ANT0_PC5        SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
     454            0 : #define MODEM_ANT0_PC6        SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
     455            0 : #define MODEM_ANT0_PC7        SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
     456            0 : #define MODEM_ANT0_PD0        SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
     457            0 : #define MODEM_ANT0_PD1        SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
     458            0 : #define MODEM_ANT0_PD2        SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
     459            0 : #define MODEM_ANT0_PD3        SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
     460            0 : #define MODEM_ANT1_PA0        SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
     461            0 : #define MODEM_ANT1_PA1        SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
     462            0 : #define MODEM_ANT1_PA2        SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
     463            0 : #define MODEM_ANT1_PA3        SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
     464            0 : #define MODEM_ANT1_PA4        SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
     465            0 : #define MODEM_ANT1_PA5        SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
     466            0 : #define MODEM_ANT1_PA6        SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
     467            0 : #define MODEM_ANT1_PA7        SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
     468            0 : #define MODEM_ANT1_PA8        SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
     469            0 : #define MODEM_ANT1_PB0        SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
     470            0 : #define MODEM_ANT1_PB1        SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
     471            0 : #define MODEM_ANT1_PB2        SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
     472            0 : #define MODEM_ANT1_PB3        SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
     473            0 : #define MODEM_ANT1_PB4        SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
     474            0 : #define MODEM_ANT1_PC0        SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
     475            0 : #define MODEM_ANT1_PC1        SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
     476            0 : #define MODEM_ANT1_PC2        SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
     477            0 : #define MODEM_ANT1_PC3        SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
     478            0 : #define MODEM_ANT1_PC4        SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
     479            0 : #define MODEM_ANT1_PC5        SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
     480            0 : #define MODEM_ANT1_PC6        SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
     481            0 : #define MODEM_ANT1_PC7        SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
     482            0 : #define MODEM_ANT1_PD0        SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
     483            0 : #define MODEM_ANT1_PD1        SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
     484            0 : #define MODEM_ANT1_PD2        SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
     485            0 : #define MODEM_ANT1_PD3        SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
     486            0 : #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
     487            0 : #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
     488            0 : #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
     489            0 : #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
     490            0 : #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
     491            0 : #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
     492            0 : #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
     493            0 : #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
     494            0 : #define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
     495            0 : #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
     496            0 : #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
     497            0 : #define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
     498            0 : #define MODEM_ANTRR0_PC0      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
     499            0 : #define MODEM_ANTRR0_PC1      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
     500            0 : #define MODEM_ANTRR0_PC2      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
     501            0 : #define MODEM_ANTRR0_PC3      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
     502            0 : #define MODEM_ANTRR0_PC4      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
     503            0 : #define MODEM_ANTRR0_PC5      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
     504            0 : #define MODEM_ANTRR0_PC6      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
     505            0 : #define MODEM_ANTRR0_PC7      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
     506            0 : #define MODEM_ANTRR0_PD0      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
     507            0 : #define MODEM_ANTRR0_PD1      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
     508            0 : #define MODEM_ANTRR0_PD2      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
     509            0 : #define MODEM_ANTRR0_PD3      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
     510            0 : #define MODEM_ANTRR1_PC0      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
     511            0 : #define MODEM_ANTRR1_PC1      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
     512            0 : #define MODEM_ANTRR1_PC2      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
     513            0 : #define MODEM_ANTRR1_PC3      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
     514            0 : #define MODEM_ANTRR1_PC4      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
     515            0 : #define MODEM_ANTRR1_PC5      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
     516            0 : #define MODEM_ANTRR1_PC6      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
     517            0 : #define MODEM_ANTRR1_PC7      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
     518            0 : #define MODEM_ANTRR1_PD0      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
     519            0 : #define MODEM_ANTRR1_PD1      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
     520            0 : #define MODEM_ANTRR1_PD2      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
     521            0 : #define MODEM_ANTRR1_PD3      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
     522            0 : #define MODEM_ANTRR2_PC0      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
     523            0 : #define MODEM_ANTRR2_PC1      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
     524            0 : #define MODEM_ANTRR2_PC2      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
     525            0 : #define MODEM_ANTRR2_PC3      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
     526            0 : #define MODEM_ANTRR2_PC4      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
     527            0 : #define MODEM_ANTRR2_PC5      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
     528            0 : #define MODEM_ANTRR2_PC6      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
     529            0 : #define MODEM_ANTRR2_PC7      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
     530            0 : #define MODEM_ANTRR2_PD0      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
     531            0 : #define MODEM_ANTRR2_PD1      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
     532            0 : #define MODEM_ANTRR2_PD2      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
     533            0 : #define MODEM_ANTRR2_PD3      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
     534            0 : #define MODEM_ANTRR3_PC0      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
     535            0 : #define MODEM_ANTRR3_PC1      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
     536            0 : #define MODEM_ANTRR3_PC2      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
     537            0 : #define MODEM_ANTRR3_PC3      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
     538            0 : #define MODEM_ANTRR3_PC4      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
     539            0 : #define MODEM_ANTRR3_PC5      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
     540            0 : #define MODEM_ANTRR3_PC6      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
     541            0 : #define MODEM_ANTRR3_PC7      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
     542            0 : #define MODEM_ANTRR3_PD0      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
     543            0 : #define MODEM_ANTRR3_PD1      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
     544            0 : #define MODEM_ANTRR3_PD2      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
     545            0 : #define MODEM_ANTRR3_PD3      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
     546            0 : #define MODEM_ANTRR4_PC0      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
     547            0 : #define MODEM_ANTRR4_PC1      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
     548            0 : #define MODEM_ANTRR4_PC2      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
     549            0 : #define MODEM_ANTRR4_PC3      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
     550            0 : #define MODEM_ANTRR4_PC4      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
     551            0 : #define MODEM_ANTRR4_PC5      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
     552            0 : #define MODEM_ANTRR4_PC6      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
     553            0 : #define MODEM_ANTRR4_PC7      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
     554            0 : #define MODEM_ANTRR4_PD0      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
     555            0 : #define MODEM_ANTRR4_PD1      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
     556            0 : #define MODEM_ANTRR4_PD2      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
     557            0 : #define MODEM_ANTRR4_PD3      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
     558            0 : #define MODEM_ANTRR5_PC0      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
     559            0 : #define MODEM_ANTRR5_PC1      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
     560            0 : #define MODEM_ANTRR5_PC2      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
     561            0 : #define MODEM_ANTRR5_PC3      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
     562            0 : #define MODEM_ANTRR5_PC4      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
     563            0 : #define MODEM_ANTRR5_PC5      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
     564            0 : #define MODEM_ANTRR5_PC6      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
     565            0 : #define MODEM_ANTRR5_PC7      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
     566            0 : #define MODEM_ANTRR5_PD0      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
     567            0 : #define MODEM_ANTRR5_PD1      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
     568            0 : #define MODEM_ANTRR5_PD2      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
     569            0 : #define MODEM_ANTRR5_PD3      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
     570            0 : #define MODEM_ANTSWEN_PC0     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
     571            0 : #define MODEM_ANTSWEN_PC1     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
     572            0 : #define MODEM_ANTSWEN_PC2     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
     573            0 : #define MODEM_ANTSWEN_PC3     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
     574            0 : #define MODEM_ANTSWEN_PC4     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
     575            0 : #define MODEM_ANTSWEN_PC5     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
     576            0 : #define MODEM_ANTSWEN_PC6     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
     577            0 : #define MODEM_ANTSWEN_PC7     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
     578            0 : #define MODEM_ANTSWEN_PD0     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
     579            0 : #define MODEM_ANTSWEN_PD1     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
     580            0 : #define MODEM_ANTSWEN_PD2     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
     581            0 : #define MODEM_ANTSWEN_PD3     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
     582            0 : #define MODEM_ANTSWUS_PC0     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
     583            0 : #define MODEM_ANTSWUS_PC1     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
     584            0 : #define MODEM_ANTSWUS_PC2     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
     585            0 : #define MODEM_ANTSWUS_PC3     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
     586            0 : #define MODEM_ANTSWUS_PC4     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
     587            0 : #define MODEM_ANTSWUS_PC5     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
     588            0 : #define MODEM_ANTSWUS_PC6     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
     589            0 : #define MODEM_ANTSWUS_PC7     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
     590            0 : #define MODEM_ANTSWUS_PD0     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
     591            0 : #define MODEM_ANTSWUS_PD1     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
     592            0 : #define MODEM_ANTSWUS_PD2     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
     593            0 : #define MODEM_ANTSWUS_PD3     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
     594            0 : #define MODEM_ANTTRIG_PC0     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
     595            0 : #define MODEM_ANTTRIG_PC1     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
     596            0 : #define MODEM_ANTTRIG_PC2     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
     597            0 : #define MODEM_ANTTRIG_PC3     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
     598            0 : #define MODEM_ANTTRIG_PC4     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
     599            0 : #define MODEM_ANTTRIG_PC5     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
     600            0 : #define MODEM_ANTTRIG_PC6     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
     601            0 : #define MODEM_ANTTRIG_PC7     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
     602            0 : #define MODEM_ANTTRIG_PD0     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
     603            0 : #define MODEM_ANTTRIG_PD1     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
     604            0 : #define MODEM_ANTTRIG_PD2     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
     605            0 : #define MODEM_ANTTRIG_PD3     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
     606            0 : #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
     607            0 : #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
     608            0 : #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
     609            0 : #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
     610            0 : #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
     611            0 : #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
     612            0 : #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
     613            0 : #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
     614            0 : #define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
     615            0 : #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
     616            0 : #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
     617            0 : #define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
     618            0 : #define MODEM_DCLK_PA0        SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
     619            0 : #define MODEM_DCLK_PA1        SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
     620            0 : #define MODEM_DCLK_PA2        SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
     621            0 : #define MODEM_DCLK_PA3        SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
     622            0 : #define MODEM_DCLK_PA4        SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
     623            0 : #define MODEM_DCLK_PA5        SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
     624            0 : #define MODEM_DCLK_PA6        SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
     625            0 : #define MODEM_DCLK_PA7        SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
     626            0 : #define MODEM_DCLK_PA8        SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
     627            0 : #define MODEM_DCLK_PB0        SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
     628            0 : #define MODEM_DCLK_PB1        SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
     629            0 : #define MODEM_DCLK_PB2        SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
     630            0 : #define MODEM_DCLK_PB3        SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
     631            0 : #define MODEM_DCLK_PB4        SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
     632            0 : #define MODEM_DOUT_PA0        SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
     633            0 : #define MODEM_DOUT_PA1        SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
     634            0 : #define MODEM_DOUT_PA2        SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
     635            0 : #define MODEM_DOUT_PA3        SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
     636            0 : #define MODEM_DOUT_PA4        SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
     637            0 : #define MODEM_DOUT_PA5        SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
     638            0 : #define MODEM_DOUT_PA6        SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
     639            0 : #define MODEM_DOUT_PA7        SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
     640            0 : #define MODEM_DOUT_PA8        SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
     641            0 : #define MODEM_DOUT_PB0        SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
     642            0 : #define MODEM_DOUT_PB1        SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
     643            0 : #define MODEM_DOUT_PB2        SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
     644            0 : #define MODEM_DOUT_PB3        SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
     645            0 : #define MODEM_DOUT_PB4        SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
     646            0 : #define MODEM_DIN_PA0         SILABS_DBUS_MODEM_DIN(0x0, 0x0)
     647            0 : #define MODEM_DIN_PA1         SILABS_DBUS_MODEM_DIN(0x0, 0x1)
     648            0 : #define MODEM_DIN_PA2         SILABS_DBUS_MODEM_DIN(0x0, 0x2)
     649            0 : #define MODEM_DIN_PA3         SILABS_DBUS_MODEM_DIN(0x0, 0x3)
     650            0 : #define MODEM_DIN_PA4         SILABS_DBUS_MODEM_DIN(0x0, 0x4)
     651            0 : #define MODEM_DIN_PA5         SILABS_DBUS_MODEM_DIN(0x0, 0x5)
     652            0 : #define MODEM_DIN_PA6         SILABS_DBUS_MODEM_DIN(0x0, 0x6)
     653            0 : #define MODEM_DIN_PA7         SILABS_DBUS_MODEM_DIN(0x0, 0x7)
     654            0 : #define MODEM_DIN_PA8         SILABS_DBUS_MODEM_DIN(0x0, 0x8)
     655            0 : #define MODEM_DIN_PB0         SILABS_DBUS_MODEM_DIN(0x1, 0x0)
     656            0 : #define MODEM_DIN_PB1         SILABS_DBUS_MODEM_DIN(0x1, 0x1)
     657            0 : #define MODEM_DIN_PB2         SILABS_DBUS_MODEM_DIN(0x1, 0x2)
     658            0 : #define MODEM_DIN_PB3         SILABS_DBUS_MODEM_DIN(0x1, 0x3)
     659            0 : #define MODEM_DIN_PB4         SILABS_DBUS_MODEM_DIN(0x1, 0x4)
     660              : 
     661            0 : #define PDM_CLK_PA0  SILABS_DBUS_PDM_CLK(0x0, 0x0)
     662            0 : #define PDM_CLK_PA1  SILABS_DBUS_PDM_CLK(0x0, 0x1)
     663            0 : #define PDM_CLK_PA2  SILABS_DBUS_PDM_CLK(0x0, 0x2)
     664            0 : #define PDM_CLK_PA3  SILABS_DBUS_PDM_CLK(0x0, 0x3)
     665            0 : #define PDM_CLK_PA4  SILABS_DBUS_PDM_CLK(0x0, 0x4)
     666            0 : #define PDM_CLK_PA5  SILABS_DBUS_PDM_CLK(0x0, 0x5)
     667            0 : #define PDM_CLK_PA6  SILABS_DBUS_PDM_CLK(0x0, 0x6)
     668            0 : #define PDM_CLK_PA7  SILABS_DBUS_PDM_CLK(0x0, 0x7)
     669            0 : #define PDM_CLK_PA8  SILABS_DBUS_PDM_CLK(0x0, 0x8)
     670            0 : #define PDM_CLK_PB0  SILABS_DBUS_PDM_CLK(0x1, 0x0)
     671            0 : #define PDM_CLK_PB1  SILABS_DBUS_PDM_CLK(0x1, 0x1)
     672            0 : #define PDM_CLK_PB2  SILABS_DBUS_PDM_CLK(0x1, 0x2)
     673            0 : #define PDM_CLK_PB3  SILABS_DBUS_PDM_CLK(0x1, 0x3)
     674            0 : #define PDM_CLK_PB4  SILABS_DBUS_PDM_CLK(0x1, 0x4)
     675            0 : #define PDM_CLK_PC0  SILABS_DBUS_PDM_CLK(0x2, 0x0)
     676            0 : #define PDM_CLK_PC1  SILABS_DBUS_PDM_CLK(0x2, 0x1)
     677            0 : #define PDM_CLK_PC2  SILABS_DBUS_PDM_CLK(0x2, 0x2)
     678            0 : #define PDM_CLK_PC3  SILABS_DBUS_PDM_CLK(0x2, 0x3)
     679            0 : #define PDM_CLK_PC4  SILABS_DBUS_PDM_CLK(0x2, 0x4)
     680            0 : #define PDM_CLK_PC5  SILABS_DBUS_PDM_CLK(0x2, 0x5)
     681            0 : #define PDM_CLK_PC6  SILABS_DBUS_PDM_CLK(0x2, 0x6)
     682            0 : #define PDM_CLK_PC7  SILABS_DBUS_PDM_CLK(0x2, 0x7)
     683            0 : #define PDM_CLK_PD0  SILABS_DBUS_PDM_CLK(0x3, 0x0)
     684            0 : #define PDM_CLK_PD1  SILABS_DBUS_PDM_CLK(0x3, 0x1)
     685            0 : #define PDM_CLK_PD2  SILABS_DBUS_PDM_CLK(0x3, 0x2)
     686            0 : #define PDM_CLK_PD3  SILABS_DBUS_PDM_CLK(0x3, 0x3)
     687            0 : #define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0)
     688            0 : #define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1)
     689            0 : #define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2)
     690            0 : #define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3)
     691            0 : #define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4)
     692            0 : #define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5)
     693            0 : #define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6)
     694            0 : #define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7)
     695            0 : #define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8)
     696            0 : #define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0)
     697            0 : #define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1)
     698            0 : #define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2)
     699            0 : #define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3)
     700            0 : #define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4)
     701            0 : #define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0)
     702            0 : #define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1)
     703            0 : #define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2)
     704            0 : #define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3)
     705            0 : #define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4)
     706            0 : #define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5)
     707            0 : #define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6)
     708            0 : #define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7)
     709            0 : #define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0)
     710            0 : #define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1)
     711            0 : #define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2)
     712            0 : #define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3)
     713            0 : #define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0)
     714            0 : #define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1)
     715            0 : #define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2)
     716            0 : #define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3)
     717            0 : #define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4)
     718            0 : #define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5)
     719            0 : #define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6)
     720            0 : #define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7)
     721            0 : #define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8)
     722            0 : #define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0)
     723            0 : #define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1)
     724            0 : #define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2)
     725            0 : #define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3)
     726            0 : #define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4)
     727            0 : #define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0)
     728            0 : #define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1)
     729            0 : #define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2)
     730            0 : #define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3)
     731            0 : #define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4)
     732            0 : #define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5)
     733            0 : #define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6)
     734            0 : #define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7)
     735            0 : #define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0)
     736            0 : #define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1)
     737            0 : #define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2)
     738            0 : #define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3)
     739              : 
     740            0 : #define PRS0_ASYNCH0_PA0  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
     741            0 : #define PRS0_ASYNCH0_PA1  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
     742            0 : #define PRS0_ASYNCH0_PA2  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
     743            0 : #define PRS0_ASYNCH0_PA3  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
     744            0 : #define PRS0_ASYNCH0_PA4  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
     745            0 : #define PRS0_ASYNCH0_PA5  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
     746            0 : #define PRS0_ASYNCH0_PA6  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
     747            0 : #define PRS0_ASYNCH0_PA7  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
     748            0 : #define PRS0_ASYNCH0_PA8  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
     749            0 : #define PRS0_ASYNCH0_PB0  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
     750            0 : #define PRS0_ASYNCH0_PB1  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
     751            0 : #define PRS0_ASYNCH0_PB2  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
     752            0 : #define PRS0_ASYNCH0_PB3  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
     753            0 : #define PRS0_ASYNCH0_PB4  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
     754            0 : #define PRS0_ASYNCH1_PA0  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
     755            0 : #define PRS0_ASYNCH1_PA1  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
     756            0 : #define PRS0_ASYNCH1_PA2  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
     757            0 : #define PRS0_ASYNCH1_PA3  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
     758            0 : #define PRS0_ASYNCH1_PA4  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
     759            0 : #define PRS0_ASYNCH1_PA5  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
     760            0 : #define PRS0_ASYNCH1_PA6  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
     761            0 : #define PRS0_ASYNCH1_PA7  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
     762            0 : #define PRS0_ASYNCH1_PA8  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
     763            0 : #define PRS0_ASYNCH1_PB0  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
     764            0 : #define PRS0_ASYNCH1_PB1  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
     765            0 : #define PRS0_ASYNCH1_PB2  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
     766            0 : #define PRS0_ASYNCH1_PB3  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
     767            0 : #define PRS0_ASYNCH1_PB4  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
     768            0 : #define PRS0_ASYNCH2_PA0  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
     769            0 : #define PRS0_ASYNCH2_PA1  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
     770            0 : #define PRS0_ASYNCH2_PA2  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
     771            0 : #define PRS0_ASYNCH2_PA3  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
     772            0 : #define PRS0_ASYNCH2_PA4  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
     773            0 : #define PRS0_ASYNCH2_PA5  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
     774            0 : #define PRS0_ASYNCH2_PA6  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
     775            0 : #define PRS0_ASYNCH2_PA7  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
     776            0 : #define PRS0_ASYNCH2_PA8  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
     777            0 : #define PRS0_ASYNCH2_PB0  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
     778            0 : #define PRS0_ASYNCH2_PB1  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
     779            0 : #define PRS0_ASYNCH2_PB2  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
     780            0 : #define PRS0_ASYNCH2_PB3  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
     781            0 : #define PRS0_ASYNCH2_PB4  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
     782            0 : #define PRS0_ASYNCH3_PA0  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
     783            0 : #define PRS0_ASYNCH3_PA1  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
     784            0 : #define PRS0_ASYNCH3_PA2  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
     785            0 : #define PRS0_ASYNCH3_PA3  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
     786            0 : #define PRS0_ASYNCH3_PA4  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
     787            0 : #define PRS0_ASYNCH3_PA5  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
     788            0 : #define PRS0_ASYNCH3_PA6  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
     789            0 : #define PRS0_ASYNCH3_PA7  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
     790            0 : #define PRS0_ASYNCH3_PA8  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
     791            0 : #define PRS0_ASYNCH3_PB0  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
     792            0 : #define PRS0_ASYNCH3_PB1  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
     793            0 : #define PRS0_ASYNCH3_PB2  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
     794            0 : #define PRS0_ASYNCH3_PB3  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
     795            0 : #define PRS0_ASYNCH3_PB4  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
     796            0 : #define PRS0_ASYNCH4_PA0  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
     797            0 : #define PRS0_ASYNCH4_PA1  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
     798            0 : #define PRS0_ASYNCH4_PA2  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
     799            0 : #define PRS0_ASYNCH4_PA3  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
     800            0 : #define PRS0_ASYNCH4_PA4  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
     801            0 : #define PRS0_ASYNCH4_PA5  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
     802            0 : #define PRS0_ASYNCH4_PA6  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
     803            0 : #define PRS0_ASYNCH4_PA7  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
     804            0 : #define PRS0_ASYNCH4_PA8  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
     805            0 : #define PRS0_ASYNCH4_PB0  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
     806            0 : #define PRS0_ASYNCH4_PB1  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
     807            0 : #define PRS0_ASYNCH4_PB2  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
     808            0 : #define PRS0_ASYNCH4_PB3  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
     809            0 : #define PRS0_ASYNCH4_PB4  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
     810            0 : #define PRS0_ASYNCH5_PA0  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
     811            0 : #define PRS0_ASYNCH5_PA1  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
     812            0 : #define PRS0_ASYNCH5_PA2  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
     813            0 : #define PRS0_ASYNCH5_PA3  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
     814            0 : #define PRS0_ASYNCH5_PA4  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
     815            0 : #define PRS0_ASYNCH5_PA5  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
     816            0 : #define PRS0_ASYNCH5_PA6  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
     817            0 : #define PRS0_ASYNCH5_PA7  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
     818            0 : #define PRS0_ASYNCH5_PA8  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
     819            0 : #define PRS0_ASYNCH5_PB0  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
     820            0 : #define PRS0_ASYNCH5_PB1  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
     821            0 : #define PRS0_ASYNCH5_PB2  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
     822            0 : #define PRS0_ASYNCH5_PB3  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
     823            0 : #define PRS0_ASYNCH5_PB4  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
     824            0 : #define PRS0_ASYNCH6_PC0  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
     825            0 : #define PRS0_ASYNCH6_PC1  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
     826            0 : #define PRS0_ASYNCH6_PC2  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
     827            0 : #define PRS0_ASYNCH6_PC3  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
     828            0 : #define PRS0_ASYNCH6_PC4  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
     829            0 : #define PRS0_ASYNCH6_PC5  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
     830            0 : #define PRS0_ASYNCH6_PC6  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
     831            0 : #define PRS0_ASYNCH6_PC7  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
     832            0 : #define PRS0_ASYNCH6_PD0  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
     833            0 : #define PRS0_ASYNCH6_PD1  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
     834            0 : #define PRS0_ASYNCH6_PD2  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
     835            0 : #define PRS0_ASYNCH6_PD3  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
     836            0 : #define PRS0_ASYNCH7_PC0  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
     837            0 : #define PRS0_ASYNCH7_PC1  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
     838            0 : #define PRS0_ASYNCH7_PC2  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
     839            0 : #define PRS0_ASYNCH7_PC3  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
     840            0 : #define PRS0_ASYNCH7_PC4  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
     841            0 : #define PRS0_ASYNCH7_PC5  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
     842            0 : #define PRS0_ASYNCH7_PC6  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
     843            0 : #define PRS0_ASYNCH7_PC7  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
     844            0 : #define PRS0_ASYNCH7_PD0  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
     845            0 : #define PRS0_ASYNCH7_PD1  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
     846            0 : #define PRS0_ASYNCH7_PD2  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
     847            0 : #define PRS0_ASYNCH7_PD3  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
     848            0 : #define PRS0_ASYNCH8_PC0  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
     849            0 : #define PRS0_ASYNCH8_PC1  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
     850            0 : #define PRS0_ASYNCH8_PC2  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
     851            0 : #define PRS0_ASYNCH8_PC3  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
     852            0 : #define PRS0_ASYNCH8_PC4  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
     853            0 : #define PRS0_ASYNCH8_PC5  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
     854            0 : #define PRS0_ASYNCH8_PC6  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
     855            0 : #define PRS0_ASYNCH8_PC7  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
     856            0 : #define PRS0_ASYNCH8_PD0  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
     857            0 : #define PRS0_ASYNCH8_PD1  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
     858            0 : #define PRS0_ASYNCH8_PD2  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
     859            0 : #define PRS0_ASYNCH8_PD3  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
     860            0 : #define PRS0_ASYNCH9_PC0  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
     861            0 : #define PRS0_ASYNCH9_PC1  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
     862            0 : #define PRS0_ASYNCH9_PC2  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
     863            0 : #define PRS0_ASYNCH9_PC3  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
     864            0 : #define PRS0_ASYNCH9_PC4  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
     865            0 : #define PRS0_ASYNCH9_PC5  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
     866            0 : #define PRS0_ASYNCH9_PC6  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
     867            0 : #define PRS0_ASYNCH9_PC7  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
     868            0 : #define PRS0_ASYNCH9_PD0  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
     869            0 : #define PRS0_ASYNCH9_PD1  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
     870            0 : #define PRS0_ASYNCH9_PD2  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
     871            0 : #define PRS0_ASYNCH9_PD3  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
     872            0 : #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
     873            0 : #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
     874            0 : #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
     875            0 : #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
     876            0 : #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
     877            0 : #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
     878            0 : #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
     879            0 : #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
     880            0 : #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
     881            0 : #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
     882            0 : #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
     883            0 : #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
     884            0 : #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
     885            0 : #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
     886            0 : #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
     887            0 : #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
     888            0 : #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
     889            0 : #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
     890            0 : #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
     891            0 : #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
     892            0 : #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
     893            0 : #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
     894            0 : #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
     895            0 : #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
     896            0 : #define PRS0_SYNCH0_PA0   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
     897            0 : #define PRS0_SYNCH0_PA1   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
     898            0 : #define PRS0_SYNCH0_PA2   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
     899            0 : #define PRS0_SYNCH0_PA3   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
     900            0 : #define PRS0_SYNCH0_PA4   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
     901            0 : #define PRS0_SYNCH0_PA5   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
     902            0 : #define PRS0_SYNCH0_PA6   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
     903            0 : #define PRS0_SYNCH0_PA7   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
     904            0 : #define PRS0_SYNCH0_PA8   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
     905            0 : #define PRS0_SYNCH0_PB0   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
     906            0 : #define PRS0_SYNCH0_PB1   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
     907            0 : #define PRS0_SYNCH0_PB2   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
     908            0 : #define PRS0_SYNCH0_PB3   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
     909            0 : #define PRS0_SYNCH0_PB4   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
     910            0 : #define PRS0_SYNCH0_PC0   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
     911            0 : #define PRS0_SYNCH0_PC1   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
     912            0 : #define PRS0_SYNCH0_PC2   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
     913            0 : #define PRS0_SYNCH0_PC3   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
     914            0 : #define PRS0_SYNCH0_PC4   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
     915            0 : #define PRS0_SYNCH0_PC5   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
     916            0 : #define PRS0_SYNCH0_PC6   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
     917            0 : #define PRS0_SYNCH0_PC7   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
     918            0 : #define PRS0_SYNCH0_PD0   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
     919            0 : #define PRS0_SYNCH0_PD1   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
     920            0 : #define PRS0_SYNCH0_PD2   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
     921            0 : #define PRS0_SYNCH0_PD3   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
     922            0 : #define PRS0_SYNCH1_PA0   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
     923            0 : #define PRS0_SYNCH1_PA1   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
     924            0 : #define PRS0_SYNCH1_PA2   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
     925            0 : #define PRS0_SYNCH1_PA3   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
     926            0 : #define PRS0_SYNCH1_PA4   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
     927            0 : #define PRS0_SYNCH1_PA5   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
     928            0 : #define PRS0_SYNCH1_PA6   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
     929            0 : #define PRS0_SYNCH1_PA7   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
     930            0 : #define PRS0_SYNCH1_PA8   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
     931            0 : #define PRS0_SYNCH1_PB0   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
     932            0 : #define PRS0_SYNCH1_PB1   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
     933            0 : #define PRS0_SYNCH1_PB2   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
     934            0 : #define PRS0_SYNCH1_PB3   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
     935            0 : #define PRS0_SYNCH1_PB4   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
     936            0 : #define PRS0_SYNCH1_PC0   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
     937            0 : #define PRS0_SYNCH1_PC1   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
     938            0 : #define PRS0_SYNCH1_PC2   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
     939            0 : #define PRS0_SYNCH1_PC3   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
     940            0 : #define PRS0_SYNCH1_PC4   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
     941            0 : #define PRS0_SYNCH1_PC5   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
     942            0 : #define PRS0_SYNCH1_PC6   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
     943            0 : #define PRS0_SYNCH1_PC7   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
     944            0 : #define PRS0_SYNCH1_PD0   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
     945            0 : #define PRS0_SYNCH1_PD1   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
     946            0 : #define PRS0_SYNCH1_PD2   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
     947            0 : #define PRS0_SYNCH1_PD3   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
     948            0 : #define PRS0_SYNCH2_PA0   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
     949            0 : #define PRS0_SYNCH2_PA1   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
     950            0 : #define PRS0_SYNCH2_PA2   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
     951            0 : #define PRS0_SYNCH2_PA3   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
     952            0 : #define PRS0_SYNCH2_PA4   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
     953            0 : #define PRS0_SYNCH2_PA5   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
     954            0 : #define PRS0_SYNCH2_PA6   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
     955            0 : #define PRS0_SYNCH2_PA7   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
     956            0 : #define PRS0_SYNCH2_PA8   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
     957            0 : #define PRS0_SYNCH2_PB0   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
     958            0 : #define PRS0_SYNCH2_PB1   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
     959            0 : #define PRS0_SYNCH2_PB2   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
     960            0 : #define PRS0_SYNCH2_PB3   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
     961            0 : #define PRS0_SYNCH2_PB4   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
     962            0 : #define PRS0_SYNCH2_PC0   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
     963            0 : #define PRS0_SYNCH2_PC1   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
     964            0 : #define PRS0_SYNCH2_PC2   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
     965            0 : #define PRS0_SYNCH2_PC3   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
     966            0 : #define PRS0_SYNCH2_PC4   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
     967            0 : #define PRS0_SYNCH2_PC5   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
     968            0 : #define PRS0_SYNCH2_PC6   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
     969            0 : #define PRS0_SYNCH2_PC7   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
     970            0 : #define PRS0_SYNCH2_PD0   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
     971            0 : #define PRS0_SYNCH2_PD1   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
     972            0 : #define PRS0_SYNCH2_PD2   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
     973            0 : #define PRS0_SYNCH2_PD3   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
     974            0 : #define PRS0_SYNCH3_PA0   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
     975            0 : #define PRS0_SYNCH3_PA1   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
     976            0 : #define PRS0_SYNCH3_PA2   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
     977            0 : #define PRS0_SYNCH3_PA3   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
     978            0 : #define PRS0_SYNCH3_PA4   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
     979            0 : #define PRS0_SYNCH3_PA5   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
     980            0 : #define PRS0_SYNCH3_PA6   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
     981            0 : #define PRS0_SYNCH3_PA7   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
     982            0 : #define PRS0_SYNCH3_PA8   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
     983            0 : #define PRS0_SYNCH3_PB0   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
     984            0 : #define PRS0_SYNCH3_PB1   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
     985            0 : #define PRS0_SYNCH3_PB2   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
     986            0 : #define PRS0_SYNCH3_PB3   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
     987            0 : #define PRS0_SYNCH3_PB4   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
     988            0 : #define PRS0_SYNCH3_PC0   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
     989            0 : #define PRS0_SYNCH3_PC1   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
     990            0 : #define PRS0_SYNCH3_PC2   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
     991            0 : #define PRS0_SYNCH3_PC3   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
     992            0 : #define PRS0_SYNCH3_PC4   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
     993            0 : #define PRS0_SYNCH3_PC5   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
     994            0 : #define PRS0_SYNCH3_PC6   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
     995            0 : #define PRS0_SYNCH3_PC7   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
     996            0 : #define PRS0_SYNCH3_PD0   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
     997            0 : #define PRS0_SYNCH3_PD1   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
     998            0 : #define PRS0_SYNCH3_PD2   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
     999            0 : #define PRS0_SYNCH3_PD3   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
    1000              : 
    1001            0 : #define TIMER0_CC0_PA0   SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
    1002            0 : #define TIMER0_CC0_PA1   SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
    1003            0 : #define TIMER0_CC0_PA2   SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
    1004            0 : #define TIMER0_CC0_PA3   SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
    1005            0 : #define TIMER0_CC0_PA4   SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
    1006            0 : #define TIMER0_CC0_PA5   SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
    1007            0 : #define TIMER0_CC0_PA6   SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
    1008            0 : #define TIMER0_CC0_PA7   SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
    1009            0 : #define TIMER0_CC0_PA8   SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
    1010            0 : #define TIMER0_CC0_PB0   SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
    1011            0 : #define TIMER0_CC0_PB1   SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
    1012            0 : #define TIMER0_CC0_PB2   SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
    1013            0 : #define TIMER0_CC0_PB3   SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
    1014            0 : #define TIMER0_CC0_PB4   SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
    1015            0 : #define TIMER0_CC0_PC0   SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
    1016            0 : #define TIMER0_CC0_PC1   SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
    1017            0 : #define TIMER0_CC0_PC2   SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
    1018            0 : #define TIMER0_CC0_PC3   SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
    1019            0 : #define TIMER0_CC0_PC4   SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
    1020            0 : #define TIMER0_CC0_PC5   SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
    1021            0 : #define TIMER0_CC0_PC6   SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
    1022            0 : #define TIMER0_CC0_PC7   SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
    1023            0 : #define TIMER0_CC0_PD0   SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
    1024            0 : #define TIMER0_CC0_PD1   SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
    1025            0 : #define TIMER0_CC0_PD2   SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
    1026            0 : #define TIMER0_CC0_PD3   SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
    1027            0 : #define TIMER0_CC1_PA0   SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
    1028            0 : #define TIMER0_CC1_PA1   SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
    1029            0 : #define TIMER0_CC1_PA2   SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
    1030            0 : #define TIMER0_CC1_PA3   SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
    1031            0 : #define TIMER0_CC1_PA4   SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
    1032            0 : #define TIMER0_CC1_PA5   SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
    1033            0 : #define TIMER0_CC1_PA6   SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
    1034            0 : #define TIMER0_CC1_PA7   SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
    1035            0 : #define TIMER0_CC1_PA8   SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
    1036            0 : #define TIMER0_CC1_PB0   SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
    1037            0 : #define TIMER0_CC1_PB1   SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
    1038            0 : #define TIMER0_CC1_PB2   SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
    1039            0 : #define TIMER0_CC1_PB3   SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
    1040            0 : #define TIMER0_CC1_PB4   SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
    1041            0 : #define TIMER0_CC1_PC0   SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
    1042            0 : #define TIMER0_CC1_PC1   SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
    1043            0 : #define TIMER0_CC1_PC2   SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
    1044            0 : #define TIMER0_CC1_PC3   SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
    1045            0 : #define TIMER0_CC1_PC4   SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
    1046            0 : #define TIMER0_CC1_PC5   SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
    1047            0 : #define TIMER0_CC1_PC6   SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
    1048            0 : #define TIMER0_CC1_PC7   SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
    1049            0 : #define TIMER0_CC1_PD0   SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
    1050            0 : #define TIMER0_CC1_PD1   SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
    1051            0 : #define TIMER0_CC1_PD2   SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
    1052            0 : #define TIMER0_CC1_PD3   SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
    1053            0 : #define TIMER0_CC2_PA0   SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
    1054            0 : #define TIMER0_CC2_PA1   SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
    1055            0 : #define TIMER0_CC2_PA2   SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
    1056            0 : #define TIMER0_CC2_PA3   SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
    1057            0 : #define TIMER0_CC2_PA4   SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
    1058            0 : #define TIMER0_CC2_PA5   SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
    1059            0 : #define TIMER0_CC2_PA6   SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
    1060            0 : #define TIMER0_CC2_PA7   SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
    1061            0 : #define TIMER0_CC2_PA8   SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
    1062            0 : #define TIMER0_CC2_PB0   SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
    1063            0 : #define TIMER0_CC2_PB1   SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
    1064            0 : #define TIMER0_CC2_PB2   SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
    1065            0 : #define TIMER0_CC2_PB3   SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
    1066            0 : #define TIMER0_CC2_PB4   SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
    1067            0 : #define TIMER0_CC2_PC0   SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
    1068            0 : #define TIMER0_CC2_PC1   SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
    1069            0 : #define TIMER0_CC2_PC2   SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
    1070            0 : #define TIMER0_CC2_PC3   SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
    1071            0 : #define TIMER0_CC2_PC4   SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
    1072            0 : #define TIMER0_CC2_PC5   SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
    1073            0 : #define TIMER0_CC2_PC6   SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
    1074            0 : #define TIMER0_CC2_PC7   SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
    1075            0 : #define TIMER0_CC2_PD0   SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
    1076            0 : #define TIMER0_CC2_PD1   SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
    1077            0 : #define TIMER0_CC2_PD2   SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
    1078            0 : #define TIMER0_CC2_PD3   SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
    1079            0 : #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
    1080            0 : #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
    1081            0 : #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
    1082            0 : #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
    1083            0 : #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
    1084            0 : #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
    1085            0 : #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
    1086            0 : #define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
    1087            0 : #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
    1088            0 : #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
    1089            0 : #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
    1090            0 : #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
    1091            0 : #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
    1092            0 : #define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
    1093            0 : #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
    1094            0 : #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
    1095            0 : #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
    1096            0 : #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
    1097            0 : #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
    1098            0 : #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
    1099            0 : #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
    1100            0 : #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
    1101            0 : #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
    1102            0 : #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
    1103            0 : #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
    1104            0 : #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
    1105            0 : #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
    1106            0 : #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
    1107            0 : #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
    1108            0 : #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
    1109            0 : #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
    1110            0 : #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
    1111            0 : #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
    1112            0 : #define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
    1113            0 : #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
    1114            0 : #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
    1115            0 : #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
    1116            0 : #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
    1117            0 : #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
    1118            0 : #define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
    1119            0 : #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
    1120            0 : #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
    1121            0 : #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
    1122            0 : #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
    1123            0 : #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
    1124            0 : #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
    1125            0 : #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
    1126            0 : #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
    1127            0 : #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
    1128            0 : #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
    1129            0 : #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
    1130            0 : #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
    1131            0 : #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
    1132            0 : #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
    1133            0 : #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
    1134            0 : #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
    1135            0 : #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
    1136            0 : #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
    1137            0 : #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
    1138            0 : #define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
    1139            0 : #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
    1140            0 : #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
    1141            0 : #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
    1142            0 : #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
    1143            0 : #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
    1144            0 : #define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
    1145            0 : #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
    1146            0 : #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
    1147            0 : #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
    1148            0 : #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
    1149            0 : #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
    1150            0 : #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
    1151            0 : #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
    1152            0 : #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
    1153            0 : #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
    1154            0 : #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
    1155            0 : #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
    1156            0 : #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
    1157              : 
    1158            0 : #define TIMER1_CC0_PA0   SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
    1159            0 : #define TIMER1_CC0_PA1   SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
    1160            0 : #define TIMER1_CC0_PA2   SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
    1161            0 : #define TIMER1_CC0_PA3   SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
    1162            0 : #define TIMER1_CC0_PA4   SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
    1163            0 : #define TIMER1_CC0_PA5   SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
    1164            0 : #define TIMER1_CC0_PA6   SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
    1165            0 : #define TIMER1_CC0_PA7   SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
    1166            0 : #define TIMER1_CC0_PA8   SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
    1167            0 : #define TIMER1_CC0_PB0   SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
    1168            0 : #define TIMER1_CC0_PB1   SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
    1169            0 : #define TIMER1_CC0_PB2   SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
    1170            0 : #define TIMER1_CC0_PB3   SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
    1171            0 : #define TIMER1_CC0_PB4   SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
    1172            0 : #define TIMER1_CC0_PC0   SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
    1173            0 : #define TIMER1_CC0_PC1   SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
    1174            0 : #define TIMER1_CC0_PC2   SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
    1175            0 : #define TIMER1_CC0_PC3   SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
    1176            0 : #define TIMER1_CC0_PC4   SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
    1177            0 : #define TIMER1_CC0_PC5   SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
    1178            0 : #define TIMER1_CC0_PC6   SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
    1179            0 : #define TIMER1_CC0_PC7   SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
    1180            0 : #define TIMER1_CC0_PD0   SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
    1181            0 : #define TIMER1_CC0_PD1   SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
    1182            0 : #define TIMER1_CC0_PD2   SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
    1183            0 : #define TIMER1_CC0_PD3   SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
    1184            0 : #define TIMER1_CC1_PA0   SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
    1185            0 : #define TIMER1_CC1_PA1   SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
    1186            0 : #define TIMER1_CC1_PA2   SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
    1187            0 : #define TIMER1_CC1_PA3   SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
    1188            0 : #define TIMER1_CC1_PA4   SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
    1189            0 : #define TIMER1_CC1_PA5   SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
    1190            0 : #define TIMER1_CC1_PA6   SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
    1191            0 : #define TIMER1_CC1_PA7   SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
    1192            0 : #define TIMER1_CC1_PA8   SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
    1193            0 : #define TIMER1_CC1_PB0   SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
    1194            0 : #define TIMER1_CC1_PB1   SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
    1195            0 : #define TIMER1_CC1_PB2   SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
    1196            0 : #define TIMER1_CC1_PB3   SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
    1197            0 : #define TIMER1_CC1_PB4   SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
    1198            0 : #define TIMER1_CC1_PC0   SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
    1199            0 : #define TIMER1_CC1_PC1   SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
    1200            0 : #define TIMER1_CC1_PC2   SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
    1201            0 : #define TIMER1_CC1_PC3   SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
    1202            0 : #define TIMER1_CC1_PC4   SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
    1203            0 : #define TIMER1_CC1_PC5   SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
    1204            0 : #define TIMER1_CC1_PC6   SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
    1205            0 : #define TIMER1_CC1_PC7   SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
    1206            0 : #define TIMER1_CC1_PD0   SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
    1207            0 : #define TIMER1_CC1_PD1   SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
    1208            0 : #define TIMER1_CC1_PD2   SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
    1209            0 : #define TIMER1_CC1_PD3   SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
    1210            0 : #define TIMER1_CC2_PA0   SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
    1211            0 : #define TIMER1_CC2_PA1   SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
    1212            0 : #define TIMER1_CC2_PA2   SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
    1213            0 : #define TIMER1_CC2_PA3   SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
    1214            0 : #define TIMER1_CC2_PA4   SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
    1215            0 : #define TIMER1_CC2_PA5   SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
    1216            0 : #define TIMER1_CC2_PA6   SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
    1217            0 : #define TIMER1_CC2_PA7   SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
    1218            0 : #define TIMER1_CC2_PA8   SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
    1219            0 : #define TIMER1_CC2_PB0   SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
    1220            0 : #define TIMER1_CC2_PB1   SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
    1221            0 : #define TIMER1_CC2_PB2   SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
    1222            0 : #define TIMER1_CC2_PB3   SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
    1223            0 : #define TIMER1_CC2_PB4   SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
    1224            0 : #define TIMER1_CC2_PC0   SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
    1225            0 : #define TIMER1_CC2_PC1   SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
    1226            0 : #define TIMER1_CC2_PC2   SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
    1227            0 : #define TIMER1_CC2_PC3   SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
    1228            0 : #define TIMER1_CC2_PC4   SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
    1229            0 : #define TIMER1_CC2_PC5   SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
    1230            0 : #define TIMER1_CC2_PC6   SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
    1231            0 : #define TIMER1_CC2_PC7   SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
    1232            0 : #define TIMER1_CC2_PD0   SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
    1233            0 : #define TIMER1_CC2_PD1   SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
    1234            0 : #define TIMER1_CC2_PD2   SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
    1235            0 : #define TIMER1_CC2_PD3   SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
    1236            0 : #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
    1237            0 : #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
    1238            0 : #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
    1239            0 : #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
    1240            0 : #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
    1241            0 : #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
    1242            0 : #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
    1243            0 : #define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
    1244            0 : #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
    1245            0 : #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
    1246            0 : #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
    1247            0 : #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
    1248            0 : #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
    1249            0 : #define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
    1250            0 : #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
    1251            0 : #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
    1252            0 : #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
    1253            0 : #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
    1254            0 : #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
    1255            0 : #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
    1256            0 : #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
    1257            0 : #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
    1258            0 : #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
    1259            0 : #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
    1260            0 : #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
    1261            0 : #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
    1262            0 : #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
    1263            0 : #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
    1264            0 : #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
    1265            0 : #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
    1266            0 : #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
    1267            0 : #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
    1268            0 : #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
    1269            0 : #define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
    1270            0 : #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
    1271            0 : #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
    1272            0 : #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
    1273            0 : #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
    1274            0 : #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
    1275            0 : #define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
    1276            0 : #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
    1277            0 : #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
    1278            0 : #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
    1279            0 : #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
    1280            0 : #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
    1281            0 : #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
    1282            0 : #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
    1283            0 : #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
    1284            0 : #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
    1285            0 : #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
    1286            0 : #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
    1287            0 : #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
    1288            0 : #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
    1289            0 : #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
    1290            0 : #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
    1291            0 : #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
    1292            0 : #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
    1293            0 : #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
    1294            0 : #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
    1295            0 : #define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
    1296            0 : #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
    1297            0 : #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
    1298            0 : #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
    1299            0 : #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
    1300            0 : #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
    1301            0 : #define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
    1302            0 : #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
    1303            0 : #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
    1304            0 : #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
    1305            0 : #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
    1306            0 : #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
    1307            0 : #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
    1308            0 : #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
    1309            0 : #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
    1310            0 : #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
    1311            0 : #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
    1312            0 : #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
    1313            0 : #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
    1314              : 
    1315            0 : #define TIMER2_CC0_PA0   SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
    1316            0 : #define TIMER2_CC0_PA1   SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
    1317            0 : #define TIMER2_CC0_PA2   SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
    1318            0 : #define TIMER2_CC0_PA3   SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
    1319            0 : #define TIMER2_CC0_PA4   SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
    1320            0 : #define TIMER2_CC0_PA5   SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
    1321            0 : #define TIMER2_CC0_PA6   SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
    1322            0 : #define TIMER2_CC0_PA7   SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
    1323            0 : #define TIMER2_CC0_PA8   SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
    1324            0 : #define TIMER2_CC0_PB0   SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
    1325            0 : #define TIMER2_CC0_PB1   SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
    1326            0 : #define TIMER2_CC0_PB2   SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
    1327            0 : #define TIMER2_CC0_PB3   SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
    1328            0 : #define TIMER2_CC0_PB4   SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
    1329            0 : #define TIMER2_CC1_PA0   SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
    1330            0 : #define TIMER2_CC1_PA1   SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
    1331            0 : #define TIMER2_CC1_PA2   SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
    1332            0 : #define TIMER2_CC1_PA3   SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
    1333            0 : #define TIMER2_CC1_PA4   SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
    1334            0 : #define TIMER2_CC1_PA5   SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
    1335            0 : #define TIMER2_CC1_PA6   SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
    1336            0 : #define TIMER2_CC1_PA7   SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
    1337            0 : #define TIMER2_CC1_PA8   SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
    1338            0 : #define TIMER2_CC1_PB0   SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
    1339            0 : #define TIMER2_CC1_PB1   SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
    1340            0 : #define TIMER2_CC1_PB2   SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
    1341            0 : #define TIMER2_CC1_PB3   SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
    1342            0 : #define TIMER2_CC1_PB4   SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
    1343            0 : #define TIMER2_CC2_PA0   SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
    1344            0 : #define TIMER2_CC2_PA1   SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
    1345            0 : #define TIMER2_CC2_PA2   SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
    1346            0 : #define TIMER2_CC2_PA3   SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
    1347            0 : #define TIMER2_CC2_PA4   SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
    1348            0 : #define TIMER2_CC2_PA5   SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
    1349            0 : #define TIMER2_CC2_PA6   SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
    1350            0 : #define TIMER2_CC2_PA7   SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
    1351            0 : #define TIMER2_CC2_PA8   SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
    1352            0 : #define TIMER2_CC2_PB0   SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
    1353            0 : #define TIMER2_CC2_PB1   SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
    1354            0 : #define TIMER2_CC2_PB2   SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
    1355            0 : #define TIMER2_CC2_PB3   SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
    1356            0 : #define TIMER2_CC2_PB4   SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
    1357            0 : #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
    1358            0 : #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
    1359            0 : #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
    1360            0 : #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
    1361            0 : #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
    1362            0 : #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
    1363            0 : #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
    1364            0 : #define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
    1365            0 : #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
    1366            0 : #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
    1367            0 : #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
    1368            0 : #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
    1369            0 : #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
    1370            0 : #define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
    1371            0 : #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
    1372            0 : #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
    1373            0 : #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
    1374            0 : #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
    1375            0 : #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
    1376            0 : #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
    1377            0 : #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
    1378            0 : #define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
    1379            0 : #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
    1380            0 : #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
    1381            0 : #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
    1382            0 : #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
    1383            0 : #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
    1384            0 : #define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
    1385            0 : #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
    1386            0 : #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
    1387            0 : #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
    1388            0 : #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
    1389            0 : #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
    1390            0 : #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
    1391            0 : #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
    1392            0 : #define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
    1393            0 : #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
    1394            0 : #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
    1395            0 : #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
    1396            0 : #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
    1397            0 : #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
    1398            0 : #define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
    1399              : 
    1400            0 : #define TIMER3_CC0_PC0   SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
    1401            0 : #define TIMER3_CC0_PC1   SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
    1402            0 : #define TIMER3_CC0_PC2   SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
    1403            0 : #define TIMER3_CC0_PC3   SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
    1404            0 : #define TIMER3_CC0_PC4   SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
    1405            0 : #define TIMER3_CC0_PC5   SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
    1406            0 : #define TIMER3_CC0_PC6   SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
    1407            0 : #define TIMER3_CC0_PC7   SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
    1408            0 : #define TIMER3_CC0_PD0   SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
    1409            0 : #define TIMER3_CC0_PD1   SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
    1410            0 : #define TIMER3_CC0_PD2   SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
    1411            0 : #define TIMER3_CC0_PD3   SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
    1412            0 : #define TIMER3_CC1_PC0   SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
    1413            0 : #define TIMER3_CC1_PC1   SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
    1414            0 : #define TIMER3_CC1_PC2   SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
    1415            0 : #define TIMER3_CC1_PC3   SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
    1416            0 : #define TIMER3_CC1_PC4   SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
    1417            0 : #define TIMER3_CC1_PC5   SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
    1418            0 : #define TIMER3_CC1_PC6   SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
    1419            0 : #define TIMER3_CC1_PC7   SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
    1420            0 : #define TIMER3_CC1_PD0   SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
    1421            0 : #define TIMER3_CC1_PD1   SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
    1422            0 : #define TIMER3_CC1_PD2   SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
    1423            0 : #define TIMER3_CC1_PD3   SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
    1424            0 : #define TIMER3_CC2_PC0   SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
    1425            0 : #define TIMER3_CC2_PC1   SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
    1426            0 : #define TIMER3_CC2_PC2   SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
    1427            0 : #define TIMER3_CC2_PC3   SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
    1428            0 : #define TIMER3_CC2_PC4   SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
    1429            0 : #define TIMER3_CC2_PC5   SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
    1430            0 : #define TIMER3_CC2_PC6   SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
    1431            0 : #define TIMER3_CC2_PC7   SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
    1432            0 : #define TIMER3_CC2_PD0   SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
    1433            0 : #define TIMER3_CC2_PD1   SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
    1434            0 : #define TIMER3_CC2_PD2   SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
    1435            0 : #define TIMER3_CC2_PD3   SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
    1436            0 : #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
    1437            0 : #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
    1438            0 : #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
    1439            0 : #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
    1440            0 : #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
    1441            0 : #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
    1442            0 : #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
    1443            0 : #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
    1444            0 : #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
    1445            0 : #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
    1446            0 : #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
    1447            0 : #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
    1448            0 : #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
    1449            0 : #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
    1450            0 : #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
    1451            0 : #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
    1452            0 : #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
    1453            0 : #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
    1454            0 : #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
    1455            0 : #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
    1456            0 : #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
    1457            0 : #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
    1458            0 : #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
    1459            0 : #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
    1460            0 : #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
    1461            0 : #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
    1462            0 : #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
    1463            0 : #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
    1464            0 : #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
    1465            0 : #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
    1466            0 : #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
    1467            0 : #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
    1468            0 : #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
    1469            0 : #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
    1470            0 : #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
    1471            0 : #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
    1472              : 
    1473            0 : #define TIMER4_CC0_PA0   SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
    1474            0 : #define TIMER4_CC0_PA1   SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
    1475            0 : #define TIMER4_CC0_PA2   SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
    1476            0 : #define TIMER4_CC0_PA3   SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
    1477            0 : #define TIMER4_CC0_PA4   SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
    1478            0 : #define TIMER4_CC0_PA5   SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
    1479            0 : #define TIMER4_CC0_PA6   SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
    1480            0 : #define TIMER4_CC0_PA7   SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
    1481            0 : #define TIMER4_CC0_PA8   SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
    1482            0 : #define TIMER4_CC0_PB0   SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
    1483            0 : #define TIMER4_CC0_PB1   SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
    1484            0 : #define TIMER4_CC0_PB2   SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
    1485            0 : #define TIMER4_CC0_PB3   SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
    1486            0 : #define TIMER4_CC0_PB4   SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
    1487            0 : #define TIMER4_CC1_PA0   SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
    1488            0 : #define TIMER4_CC1_PA1   SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
    1489            0 : #define TIMER4_CC1_PA2   SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
    1490            0 : #define TIMER4_CC1_PA3   SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
    1491            0 : #define TIMER4_CC1_PA4   SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
    1492            0 : #define TIMER4_CC1_PA5   SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
    1493            0 : #define TIMER4_CC1_PA6   SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
    1494            0 : #define TIMER4_CC1_PA7   SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
    1495            0 : #define TIMER4_CC1_PA8   SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
    1496            0 : #define TIMER4_CC1_PB0   SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
    1497            0 : #define TIMER4_CC1_PB1   SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
    1498            0 : #define TIMER4_CC1_PB2   SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
    1499            0 : #define TIMER4_CC1_PB3   SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
    1500            0 : #define TIMER4_CC1_PB4   SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
    1501            0 : #define TIMER4_CC2_PA0   SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
    1502            0 : #define TIMER4_CC2_PA1   SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
    1503            0 : #define TIMER4_CC2_PA2   SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
    1504            0 : #define TIMER4_CC2_PA3   SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
    1505            0 : #define TIMER4_CC2_PA4   SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
    1506            0 : #define TIMER4_CC2_PA5   SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
    1507            0 : #define TIMER4_CC2_PA6   SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
    1508            0 : #define TIMER4_CC2_PA7   SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
    1509            0 : #define TIMER4_CC2_PA8   SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
    1510            0 : #define TIMER4_CC2_PB0   SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
    1511            0 : #define TIMER4_CC2_PB1   SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
    1512            0 : #define TIMER4_CC2_PB2   SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
    1513            0 : #define TIMER4_CC2_PB3   SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
    1514            0 : #define TIMER4_CC2_PB4   SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
    1515            0 : #define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
    1516            0 : #define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
    1517            0 : #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
    1518            0 : #define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
    1519            0 : #define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
    1520            0 : #define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
    1521            0 : #define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
    1522            0 : #define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
    1523            0 : #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
    1524            0 : #define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
    1525            0 : #define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
    1526            0 : #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
    1527            0 : #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
    1528            0 : #define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
    1529            0 : #define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
    1530            0 : #define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
    1531            0 : #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
    1532            0 : #define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
    1533            0 : #define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
    1534            0 : #define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
    1535            0 : #define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
    1536            0 : #define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
    1537            0 : #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
    1538            0 : #define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
    1539            0 : #define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
    1540            0 : #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
    1541            0 : #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
    1542            0 : #define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
    1543            0 : #define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
    1544            0 : #define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
    1545            0 : #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
    1546            0 : #define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
    1547            0 : #define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
    1548            0 : #define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
    1549            0 : #define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
    1550            0 : #define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
    1551            0 : #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
    1552            0 : #define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
    1553            0 : #define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
    1554            0 : #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
    1555            0 : #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
    1556            0 : #define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
    1557              : 
    1558            0 : #define USART0_CS_PA0  SILABS_DBUS_USART0_CS(0x0, 0x0)
    1559            0 : #define USART0_CS_PA1  SILABS_DBUS_USART0_CS(0x0, 0x1)
    1560            0 : #define USART0_CS_PA2  SILABS_DBUS_USART0_CS(0x0, 0x2)
    1561            0 : #define USART0_CS_PA3  SILABS_DBUS_USART0_CS(0x0, 0x3)
    1562            0 : #define USART0_CS_PA4  SILABS_DBUS_USART0_CS(0x0, 0x4)
    1563            0 : #define USART0_CS_PA5  SILABS_DBUS_USART0_CS(0x0, 0x5)
    1564            0 : #define USART0_CS_PA6  SILABS_DBUS_USART0_CS(0x0, 0x6)
    1565            0 : #define USART0_CS_PA7  SILABS_DBUS_USART0_CS(0x0, 0x7)
    1566            0 : #define USART0_CS_PA8  SILABS_DBUS_USART0_CS(0x0, 0x8)
    1567            0 : #define USART0_CS_PB0  SILABS_DBUS_USART0_CS(0x1, 0x0)
    1568            0 : #define USART0_CS_PB1  SILABS_DBUS_USART0_CS(0x1, 0x1)
    1569            0 : #define USART0_CS_PB2  SILABS_DBUS_USART0_CS(0x1, 0x2)
    1570            0 : #define USART0_CS_PB3  SILABS_DBUS_USART0_CS(0x1, 0x3)
    1571            0 : #define USART0_CS_PB4  SILABS_DBUS_USART0_CS(0x1, 0x4)
    1572            0 : #define USART0_CS_PC0  SILABS_DBUS_USART0_CS(0x2, 0x0)
    1573            0 : #define USART0_CS_PC1  SILABS_DBUS_USART0_CS(0x2, 0x1)
    1574            0 : #define USART0_CS_PC2  SILABS_DBUS_USART0_CS(0x2, 0x2)
    1575            0 : #define USART0_CS_PC3  SILABS_DBUS_USART0_CS(0x2, 0x3)
    1576            0 : #define USART0_CS_PC4  SILABS_DBUS_USART0_CS(0x2, 0x4)
    1577            0 : #define USART0_CS_PC5  SILABS_DBUS_USART0_CS(0x2, 0x5)
    1578            0 : #define USART0_CS_PC6  SILABS_DBUS_USART0_CS(0x2, 0x6)
    1579            0 : #define USART0_CS_PC7  SILABS_DBUS_USART0_CS(0x2, 0x7)
    1580            0 : #define USART0_CS_PD0  SILABS_DBUS_USART0_CS(0x3, 0x0)
    1581            0 : #define USART0_CS_PD1  SILABS_DBUS_USART0_CS(0x3, 0x1)
    1582            0 : #define USART0_CS_PD2  SILABS_DBUS_USART0_CS(0x3, 0x2)
    1583            0 : #define USART0_CS_PD3  SILABS_DBUS_USART0_CS(0x3, 0x3)
    1584            0 : #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
    1585            0 : #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
    1586            0 : #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
    1587            0 : #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
    1588            0 : #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
    1589            0 : #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
    1590            0 : #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
    1591            0 : #define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
    1592            0 : #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
    1593            0 : #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
    1594            0 : #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
    1595            0 : #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
    1596            0 : #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
    1597            0 : #define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
    1598            0 : #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
    1599            0 : #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
    1600            0 : #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
    1601            0 : #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
    1602            0 : #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
    1603            0 : #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
    1604            0 : #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
    1605            0 : #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
    1606            0 : #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
    1607            0 : #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
    1608            0 : #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
    1609            0 : #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
    1610            0 : #define USART0_RX_PA0  SILABS_DBUS_USART0_RX(0x0, 0x0)
    1611            0 : #define USART0_RX_PA1  SILABS_DBUS_USART0_RX(0x0, 0x1)
    1612            0 : #define USART0_RX_PA2  SILABS_DBUS_USART0_RX(0x0, 0x2)
    1613            0 : #define USART0_RX_PA3  SILABS_DBUS_USART0_RX(0x0, 0x3)
    1614            0 : #define USART0_RX_PA4  SILABS_DBUS_USART0_RX(0x0, 0x4)
    1615            0 : #define USART0_RX_PA5  SILABS_DBUS_USART0_RX(0x0, 0x5)
    1616            0 : #define USART0_RX_PA6  SILABS_DBUS_USART0_RX(0x0, 0x6)
    1617            0 : #define USART0_RX_PA7  SILABS_DBUS_USART0_RX(0x0, 0x7)
    1618            0 : #define USART0_RX_PA8  SILABS_DBUS_USART0_RX(0x0, 0x8)
    1619            0 : #define USART0_RX_PB0  SILABS_DBUS_USART0_RX(0x1, 0x0)
    1620            0 : #define USART0_RX_PB1  SILABS_DBUS_USART0_RX(0x1, 0x1)
    1621            0 : #define USART0_RX_PB2  SILABS_DBUS_USART0_RX(0x1, 0x2)
    1622            0 : #define USART0_RX_PB3  SILABS_DBUS_USART0_RX(0x1, 0x3)
    1623            0 : #define USART0_RX_PB4  SILABS_DBUS_USART0_RX(0x1, 0x4)
    1624            0 : #define USART0_RX_PC0  SILABS_DBUS_USART0_RX(0x2, 0x0)
    1625            0 : #define USART0_RX_PC1  SILABS_DBUS_USART0_RX(0x2, 0x1)
    1626            0 : #define USART0_RX_PC2  SILABS_DBUS_USART0_RX(0x2, 0x2)
    1627            0 : #define USART0_RX_PC3  SILABS_DBUS_USART0_RX(0x2, 0x3)
    1628            0 : #define USART0_RX_PC4  SILABS_DBUS_USART0_RX(0x2, 0x4)
    1629            0 : #define USART0_RX_PC5  SILABS_DBUS_USART0_RX(0x2, 0x5)
    1630            0 : #define USART0_RX_PC6  SILABS_DBUS_USART0_RX(0x2, 0x6)
    1631            0 : #define USART0_RX_PC7  SILABS_DBUS_USART0_RX(0x2, 0x7)
    1632            0 : #define USART0_RX_PD0  SILABS_DBUS_USART0_RX(0x3, 0x0)
    1633            0 : #define USART0_RX_PD1  SILABS_DBUS_USART0_RX(0x3, 0x1)
    1634            0 : #define USART0_RX_PD2  SILABS_DBUS_USART0_RX(0x3, 0x2)
    1635            0 : #define USART0_RX_PD3  SILABS_DBUS_USART0_RX(0x3, 0x3)
    1636            0 : #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
    1637            0 : #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
    1638            0 : #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
    1639            0 : #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
    1640            0 : #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
    1641            0 : #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
    1642            0 : #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
    1643            0 : #define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
    1644            0 : #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
    1645            0 : #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
    1646            0 : #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
    1647            0 : #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
    1648            0 : #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
    1649            0 : #define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
    1650            0 : #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
    1651            0 : #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
    1652            0 : #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
    1653            0 : #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
    1654            0 : #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
    1655            0 : #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
    1656            0 : #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
    1657            0 : #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
    1658            0 : #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
    1659            0 : #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
    1660            0 : #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
    1661            0 : #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
    1662            0 : #define USART0_TX_PA0  SILABS_DBUS_USART0_TX(0x0, 0x0)
    1663            0 : #define USART0_TX_PA1  SILABS_DBUS_USART0_TX(0x0, 0x1)
    1664            0 : #define USART0_TX_PA2  SILABS_DBUS_USART0_TX(0x0, 0x2)
    1665            0 : #define USART0_TX_PA3  SILABS_DBUS_USART0_TX(0x0, 0x3)
    1666            0 : #define USART0_TX_PA4  SILABS_DBUS_USART0_TX(0x0, 0x4)
    1667            0 : #define USART0_TX_PA5  SILABS_DBUS_USART0_TX(0x0, 0x5)
    1668            0 : #define USART0_TX_PA6  SILABS_DBUS_USART0_TX(0x0, 0x6)
    1669            0 : #define USART0_TX_PA7  SILABS_DBUS_USART0_TX(0x0, 0x7)
    1670            0 : #define USART0_TX_PA8  SILABS_DBUS_USART0_TX(0x0, 0x8)
    1671            0 : #define USART0_TX_PB0  SILABS_DBUS_USART0_TX(0x1, 0x0)
    1672            0 : #define USART0_TX_PB1  SILABS_DBUS_USART0_TX(0x1, 0x1)
    1673            0 : #define USART0_TX_PB2  SILABS_DBUS_USART0_TX(0x1, 0x2)
    1674            0 : #define USART0_TX_PB3  SILABS_DBUS_USART0_TX(0x1, 0x3)
    1675            0 : #define USART0_TX_PB4  SILABS_DBUS_USART0_TX(0x1, 0x4)
    1676            0 : #define USART0_TX_PC0  SILABS_DBUS_USART0_TX(0x2, 0x0)
    1677            0 : #define USART0_TX_PC1  SILABS_DBUS_USART0_TX(0x2, 0x1)
    1678            0 : #define USART0_TX_PC2  SILABS_DBUS_USART0_TX(0x2, 0x2)
    1679            0 : #define USART0_TX_PC3  SILABS_DBUS_USART0_TX(0x2, 0x3)
    1680            0 : #define USART0_TX_PC4  SILABS_DBUS_USART0_TX(0x2, 0x4)
    1681            0 : #define USART0_TX_PC5  SILABS_DBUS_USART0_TX(0x2, 0x5)
    1682            0 : #define USART0_TX_PC6  SILABS_DBUS_USART0_TX(0x2, 0x6)
    1683            0 : #define USART0_TX_PC7  SILABS_DBUS_USART0_TX(0x2, 0x7)
    1684            0 : #define USART0_TX_PD0  SILABS_DBUS_USART0_TX(0x3, 0x0)
    1685            0 : #define USART0_TX_PD1  SILABS_DBUS_USART0_TX(0x3, 0x1)
    1686            0 : #define USART0_TX_PD2  SILABS_DBUS_USART0_TX(0x3, 0x2)
    1687            0 : #define USART0_TX_PD3  SILABS_DBUS_USART0_TX(0x3, 0x3)
    1688            0 : #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
    1689            0 : #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
    1690            0 : #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
    1691            0 : #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
    1692            0 : #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
    1693            0 : #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
    1694            0 : #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
    1695            0 : #define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
    1696            0 : #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
    1697            0 : #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
    1698            0 : #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
    1699            0 : #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
    1700            0 : #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
    1701            0 : #define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
    1702            0 : #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
    1703            0 : #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
    1704            0 : #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
    1705            0 : #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
    1706            0 : #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
    1707            0 : #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
    1708            0 : #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
    1709            0 : #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
    1710            0 : #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
    1711            0 : #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
    1712            0 : #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
    1713            0 : #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
    1714              : 
    1715            0 : #define USART1_CS_PA0  SILABS_DBUS_USART1_CS(0x0, 0x0)
    1716            0 : #define USART1_CS_PA1  SILABS_DBUS_USART1_CS(0x0, 0x1)
    1717            0 : #define USART1_CS_PA2  SILABS_DBUS_USART1_CS(0x0, 0x2)
    1718            0 : #define USART1_CS_PA3  SILABS_DBUS_USART1_CS(0x0, 0x3)
    1719            0 : #define USART1_CS_PA4  SILABS_DBUS_USART1_CS(0x0, 0x4)
    1720            0 : #define USART1_CS_PA5  SILABS_DBUS_USART1_CS(0x0, 0x5)
    1721            0 : #define USART1_CS_PA6  SILABS_DBUS_USART1_CS(0x0, 0x6)
    1722            0 : #define USART1_CS_PA7  SILABS_DBUS_USART1_CS(0x0, 0x7)
    1723            0 : #define USART1_CS_PA8  SILABS_DBUS_USART1_CS(0x0, 0x8)
    1724            0 : #define USART1_CS_PB0  SILABS_DBUS_USART1_CS(0x1, 0x0)
    1725            0 : #define USART1_CS_PB1  SILABS_DBUS_USART1_CS(0x1, 0x1)
    1726            0 : #define USART1_CS_PB2  SILABS_DBUS_USART1_CS(0x1, 0x2)
    1727            0 : #define USART1_CS_PB3  SILABS_DBUS_USART1_CS(0x1, 0x3)
    1728            0 : #define USART1_CS_PB4  SILABS_DBUS_USART1_CS(0x1, 0x4)
    1729            0 : #define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0)
    1730            0 : #define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1)
    1731            0 : #define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2)
    1732            0 : #define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3)
    1733            0 : #define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4)
    1734            0 : #define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5)
    1735            0 : #define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
    1736            0 : #define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7)
    1737            0 : #define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8)
    1738            0 : #define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0)
    1739            0 : #define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1)
    1740            0 : #define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2)
    1741            0 : #define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3)
    1742            0 : #define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4)
    1743            0 : #define USART1_RX_PA0  SILABS_DBUS_USART1_RX(0x0, 0x0)
    1744            0 : #define USART1_RX_PA1  SILABS_DBUS_USART1_RX(0x0, 0x1)
    1745            0 : #define USART1_RX_PA2  SILABS_DBUS_USART1_RX(0x0, 0x2)
    1746            0 : #define USART1_RX_PA3  SILABS_DBUS_USART1_RX(0x0, 0x3)
    1747            0 : #define USART1_RX_PA4  SILABS_DBUS_USART1_RX(0x0, 0x4)
    1748            0 : #define USART1_RX_PA5  SILABS_DBUS_USART1_RX(0x0, 0x5)
    1749            0 : #define USART1_RX_PA6  SILABS_DBUS_USART1_RX(0x0, 0x6)
    1750            0 : #define USART1_RX_PA7  SILABS_DBUS_USART1_RX(0x0, 0x7)
    1751            0 : #define USART1_RX_PA8  SILABS_DBUS_USART1_RX(0x0, 0x8)
    1752            0 : #define USART1_RX_PB0  SILABS_DBUS_USART1_RX(0x1, 0x0)
    1753            0 : #define USART1_RX_PB1  SILABS_DBUS_USART1_RX(0x1, 0x1)
    1754            0 : #define USART1_RX_PB2  SILABS_DBUS_USART1_RX(0x1, 0x2)
    1755            0 : #define USART1_RX_PB3  SILABS_DBUS_USART1_RX(0x1, 0x3)
    1756            0 : #define USART1_RX_PB4  SILABS_DBUS_USART1_RX(0x1, 0x4)
    1757            0 : #define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0)
    1758            0 : #define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1)
    1759            0 : #define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2)
    1760            0 : #define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3)
    1761            0 : #define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4)
    1762            0 : #define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5)
    1763            0 : #define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
    1764            0 : #define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7)
    1765            0 : #define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8)
    1766            0 : #define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0)
    1767            0 : #define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1)
    1768            0 : #define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2)
    1769            0 : #define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3)
    1770            0 : #define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4)
    1771            0 : #define USART1_TX_PA0  SILABS_DBUS_USART1_TX(0x0, 0x0)
    1772            0 : #define USART1_TX_PA1  SILABS_DBUS_USART1_TX(0x0, 0x1)
    1773            0 : #define USART1_TX_PA2  SILABS_DBUS_USART1_TX(0x0, 0x2)
    1774            0 : #define USART1_TX_PA3  SILABS_DBUS_USART1_TX(0x0, 0x3)
    1775            0 : #define USART1_TX_PA4  SILABS_DBUS_USART1_TX(0x0, 0x4)
    1776            0 : #define USART1_TX_PA5  SILABS_DBUS_USART1_TX(0x0, 0x5)
    1777            0 : #define USART1_TX_PA6  SILABS_DBUS_USART1_TX(0x0, 0x6)
    1778            0 : #define USART1_TX_PA7  SILABS_DBUS_USART1_TX(0x0, 0x7)
    1779            0 : #define USART1_TX_PA8  SILABS_DBUS_USART1_TX(0x0, 0x8)
    1780            0 : #define USART1_TX_PB0  SILABS_DBUS_USART1_TX(0x1, 0x0)
    1781            0 : #define USART1_TX_PB1  SILABS_DBUS_USART1_TX(0x1, 0x1)
    1782            0 : #define USART1_TX_PB2  SILABS_DBUS_USART1_TX(0x1, 0x2)
    1783            0 : #define USART1_TX_PB3  SILABS_DBUS_USART1_TX(0x1, 0x3)
    1784            0 : #define USART1_TX_PB4  SILABS_DBUS_USART1_TX(0x1, 0x4)
    1785            0 : #define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0)
    1786            0 : #define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1)
    1787            0 : #define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2)
    1788            0 : #define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3)
    1789            0 : #define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4)
    1790            0 : #define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5)
    1791            0 : #define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)
    1792            0 : #define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7)
    1793            0 : #define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8)
    1794            0 : #define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0)
    1795            0 : #define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1)
    1796            0 : #define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2)
    1797            0 : #define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
    1798            0 : #define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)
    1799              : 
    1800            0 : #define ABUS_AEVEN0_IADC0  SILABS_ABUS(0x0, 0x0, 0x1)
    1801            0 : #define ABUS_AEVEN1_IADC0  SILABS_ABUS(0x0, 0x1, 0x1)
    1802            0 : #define ABUS_AODD0_IADC0   SILABS_ABUS(0x0, 0x2, 0x1)
    1803            0 : #define ABUS_AODD1_IADC0   SILABS_ABUS(0x0, 0x3, 0x1)
    1804            0 : #define ABUS_BEVEN0_IADC0  SILABS_ABUS(0x1, 0x0, 0x1)
    1805            0 : #define ABUS_BEVEN1_IADC0  SILABS_ABUS(0x1, 0x1, 0x1)
    1806            0 : #define ABUS_BODD0_IADC0   SILABS_ABUS(0x1, 0x2, 0x1)
    1807            0 : #define ABUS_BODD1_IADC0   SILABS_ABUS(0x1, 0x3, 0x1)
    1808            0 : #define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1)
    1809            0 : #define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1)
    1810            0 : #define ABUS_CDODD0_IADC0  SILABS_ABUS(0x2, 0x2, 0x1)
    1811            0 : #define ABUS_CDODD1_IADC0  SILABS_ABUS(0x2, 0x3, 0x1)
    1812              : 
    1813              : #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_ */
        

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