Line data Source code
1 0 : /*
2 : * Copyright (c) 2024 Silicon Laboratories Inc.
3 : * SPDX-License-Identifier: Apache-2.0
4 : *
5 : * Pin Control for Silicon Labs XG23 devices
6 : *
7 : * This file was generated by the script gen_pinctrl.py in the hal_silabs module.
8 : * Do not manually edit.
9 : */
10 :
11 : #ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG23_PINCTRL_H_
12 : #define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG23_PINCTRL_H_
13 :
14 : #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
15 :
16 0 : #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1)
17 :
18 0 : #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
19 :
20 0 : #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 2)
21 0 : #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 22, 1, 1, 3)
22 0 : #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 22, 1, 2, 4)
23 0 : #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1)
24 :
25 0 : #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 33, 1, 0, 1)
26 0 : #define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 33, 1, 1, 3)
27 0 : #define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 33, 1, 2, 4)
28 0 : #define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 33, 1, 3, 5)
29 0 : #define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 33, 1, 4, 6)
30 0 : #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 33, 0, 0, 2)
31 :
32 0 : #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1)
33 0 : #define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 41, 1, 1, 3)
34 0 : #define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 41, 1, 2, 4)
35 0 : #define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 41, 1, 3, 5)
36 0 : #define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 41, 1, 4, 6)
37 0 : #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 41, 0, 0, 2)
38 :
39 0 : #define SILABS_DBUS_EUSART2_CS(port, pin) SILABS_DBUS(port, pin, 49, 1, 0, 1)
40 0 : #define SILABS_DBUS_EUSART2_RTS(port, pin) SILABS_DBUS(port, pin, 49, 1, 1, 3)
41 0 : #define SILABS_DBUS_EUSART2_RX(port, pin) SILABS_DBUS(port, pin, 49, 1, 2, 4)
42 0 : #define SILABS_DBUS_EUSART2_SCLK(port, pin) SILABS_DBUS(port, pin, 49, 1, 3, 5)
43 0 : #define SILABS_DBUS_EUSART2_TX(port, pin) SILABS_DBUS(port, pin, 49, 1, 4, 6)
44 0 : #define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 49, 0, 0, 2)
45 :
46 0 : #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 57, 1, 0, 1)
47 0 : #define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 57, 1, 1, 2)
48 0 : #define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 57, 1, 2, 3)
49 :
50 0 : #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 62, 1, 0, 1)
51 0 : #define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 62, 1, 1, 2)
52 :
53 0 : #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 66, 1, 0, 1)
54 0 : #define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 66, 1, 1, 2)
55 :
56 0 : #define SILABS_DBUS_KEYSCAN_COLOUT0(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1)
57 0 : #define SILABS_DBUS_KEYSCAN_COLOUT1(port, pin) SILABS_DBUS(port, pin, 70, 1, 1, 2)
58 0 : #define SILABS_DBUS_KEYSCAN_COLOUT2(port, pin) SILABS_DBUS(port, pin, 70, 1, 2, 3)
59 0 : #define SILABS_DBUS_KEYSCAN_COLOUT3(port, pin) SILABS_DBUS(port, pin, 70, 1, 3, 4)
60 0 : #define SILABS_DBUS_KEYSCAN_COLOUT4(port, pin) SILABS_DBUS(port, pin, 70, 1, 4, 5)
61 0 : #define SILABS_DBUS_KEYSCAN_COLOUT5(port, pin) SILABS_DBUS(port, pin, 70, 1, 5, 6)
62 0 : #define SILABS_DBUS_KEYSCAN_COLOUT6(port, pin) SILABS_DBUS(port, pin, 70, 1, 6, 7)
63 0 : #define SILABS_DBUS_KEYSCAN_COLOUT7(port, pin) SILABS_DBUS(port, pin, 70, 1, 7, 8)
64 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE0(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 9)
65 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE1(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 10)
66 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE2(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 11)
67 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE3(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 12)
68 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE4(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 13)
69 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE5(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 14)
70 :
71 0 : #define SILABS_DBUS_LESENSE_CH0OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 0, 1)
72 0 : #define SILABS_DBUS_LESENSE_CH1OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 1, 2)
73 0 : #define SILABS_DBUS_LESENSE_CH2OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 2, 3)
74 0 : #define SILABS_DBUS_LESENSE_CH3OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 3, 4)
75 0 : #define SILABS_DBUS_LESENSE_CH4OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 4, 5)
76 0 : #define SILABS_DBUS_LESENSE_CH5OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 5, 6)
77 0 : #define SILABS_DBUS_LESENSE_CH6OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 6, 7)
78 0 : #define SILABS_DBUS_LESENSE_CH7OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 7, 8)
79 0 : #define SILABS_DBUS_LESENSE_CH8OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 8, 9)
80 0 : #define SILABS_DBUS_LESENSE_CH9OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 9, 10)
81 0 : #define SILABS_DBUS_LESENSE_CH10OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 10, 11)
82 0 : #define SILABS_DBUS_LESENSE_CH11OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 11, 12)
83 0 : #define SILABS_DBUS_LESENSE_CH12OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 12, 13)
84 0 : #define SILABS_DBUS_LESENSE_CH13OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 13, 14)
85 0 : #define SILABS_DBUS_LESENSE_CH14OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 14, 15)
86 0 : #define SILABS_DBUS_LESENSE_CH15OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 15, 16)
87 :
88 0 : #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 104, 1, 0, 1)
89 0 : #define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 104, 1, 1, 2)
90 :
91 0 : #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 108, 1, 0, 1)
92 0 : #define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 108, 1, 1, 2)
93 0 : #define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 108, 1, 2, 3)
94 0 : #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 108, 1, 3, 4)
95 0 : #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 108, 1, 4, 5)
96 0 : #define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 108, 1, 5, 6)
97 0 : #define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 108, 1, 6, 7)
98 0 : #define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 108, 1, 7, 8)
99 0 : #define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 108, 1, 8, 9)
100 0 : #define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 108, 1, 9, 10)
101 0 : #define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 108, 1, 10, 11)
102 0 : #define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 108, 1, 11, 12)
103 0 : #define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 108, 1, 12, 13)
104 0 : #define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 108, 1, 13, 14)
105 0 : #define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 108, 1, 14, 16)
106 0 : #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 108, 0, 0, 15)
107 :
108 0 : #define SILABS_DBUS_PCNT0_S0IN(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 0)
109 0 : #define SILABS_DBUS_PCNT0_S1IN(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 1)
110 :
111 0 : #define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 130, 1, 0, 1)
112 0 : #define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 130, 1, 1, 2)
113 0 : #define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 130, 1, 2, 3)
114 0 : #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 130, 1, 3, 4)
115 0 : #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 130, 1, 4, 5)
116 0 : #define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 130, 1, 5, 6)
117 0 : #define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 130, 1, 6, 7)
118 0 : #define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 130, 1, 7, 8)
119 0 : #define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 130, 1, 8, 9)
120 0 : #define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 130, 1, 9, 10)
121 0 : #define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 130, 1, 10, 11)
122 0 : #define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 130, 1, 11, 12)
123 0 : #define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 130, 1, 12, 13)
124 0 : #define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 130, 1, 13, 14)
125 0 : #define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 130, 1, 14, 15)
126 0 : #define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 130, 1, 15, 16)
127 :
128 0 : #define SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(port, pin) SILABS_DBUS(port, pin, 172, 0, 0, 0)
129 :
130 0 : #define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 174, 1, 0, 1)
131 0 : #define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 174, 1, 1, 2)
132 0 : #define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 174, 1, 2, 3)
133 0 : #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 174, 1, 3, 4)
134 0 : #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 174, 1, 4, 5)
135 0 : #define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 174, 1, 5, 6)
136 :
137 0 : #define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 182, 1, 0, 1)
138 0 : #define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 182, 1, 1, 2)
139 0 : #define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 182, 1, 2, 3)
140 0 : #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 182, 1, 3, 4)
141 0 : #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 182, 1, 4, 5)
142 0 : #define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 182, 1, 5, 6)
143 :
144 0 : #define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 190, 1, 0, 1)
145 0 : #define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 190, 1, 1, 2)
146 0 : #define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 190, 1, 2, 3)
147 0 : #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 190, 1, 3, 4)
148 0 : #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 190, 1, 4, 5)
149 0 : #define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 190, 1, 5, 6)
150 :
151 0 : #define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 198, 1, 0, 1)
152 0 : #define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 198, 1, 1, 2)
153 0 : #define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 198, 1, 2, 3)
154 0 : #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 198, 1, 3, 4)
155 0 : #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 198, 1, 4, 5)
156 0 : #define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 198, 1, 5, 6)
157 :
158 0 : #define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 206, 1, 0, 1)
159 0 : #define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 206, 1, 1, 2)
160 0 : #define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 206, 1, 2, 3)
161 0 : #define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 206, 1, 3, 4)
162 0 : #define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 206, 1, 4, 5)
163 0 : #define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 206, 1, 5, 6)
164 :
165 0 : #define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 214, 1, 0, 1)
166 0 : #define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 214, 1, 1, 3)
167 0 : #define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 214, 1, 2, 4)
168 0 : #define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 214, 1, 3, 5)
169 0 : #define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 214, 1, 4, 6)
170 0 : #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 214, 0, 0, 2)
171 :
172 0 : #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
173 0 : #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
174 0 : #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
175 0 : #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
176 0 : #define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4)
177 0 : #define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
178 0 : #define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
179 0 : #define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7)
180 0 : #define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8)
181 0 : #define ACMP0_ACMPOUT_PA9 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x9)
182 0 : #define ACMP0_ACMPOUT_PA10 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xa)
183 0 : #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
184 0 : #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
185 0 : #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
186 0 : #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
187 0 : #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
188 0 : #define ACMP0_ACMPOUT_PB5 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x5)
189 0 : #define ACMP0_ACMPOUT_PB6 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x6)
190 0 : #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
191 0 : #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
192 0 : #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
193 0 : #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
194 0 : #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
195 0 : #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
196 0 : #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
197 0 : #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
198 0 : #define ACMP0_ACMPOUT_PC8 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x8)
199 0 : #define ACMP0_ACMPOUT_PC9 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x9)
200 0 : #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
201 0 : #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
202 0 : #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
203 0 : #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
204 0 : #define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4)
205 0 : #define ACMP0_ACMPOUT_PD5 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x5)
206 :
207 0 : #define ACMP1_ACMPOUT_PA0 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x0)
208 0 : #define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1)
209 0 : #define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2)
210 0 : #define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3)
211 0 : #define ACMP1_ACMPOUT_PA4 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x4)
212 0 : #define ACMP1_ACMPOUT_PA5 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x5)
213 0 : #define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6)
214 0 : #define ACMP1_ACMPOUT_PA7 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x7)
215 0 : #define ACMP1_ACMPOUT_PA8 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x8)
216 0 : #define ACMP1_ACMPOUT_PA9 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x9)
217 0 : #define ACMP1_ACMPOUT_PA10 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xa)
218 0 : #define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0)
219 0 : #define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1)
220 0 : #define ACMP1_ACMPOUT_PB2 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x2)
221 0 : #define ACMP1_ACMPOUT_PB3 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x3)
222 0 : #define ACMP1_ACMPOUT_PB4 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x4)
223 0 : #define ACMP1_ACMPOUT_PB5 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x5)
224 0 : #define ACMP1_ACMPOUT_PB6 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x6)
225 0 : #define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0)
226 0 : #define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1)
227 0 : #define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2)
228 0 : #define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3)
229 0 : #define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4)
230 0 : #define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5)
231 0 : #define ACMP1_ACMPOUT_PC6 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x6)
232 0 : #define ACMP1_ACMPOUT_PC7 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x7)
233 0 : #define ACMP1_ACMPOUT_PC8 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x8)
234 0 : #define ACMP1_ACMPOUT_PC9 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x9)
235 0 : #define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0)
236 0 : #define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1)
237 0 : #define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2)
238 0 : #define ACMP1_ACMPOUT_PD3 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x3)
239 0 : #define ACMP1_ACMPOUT_PD4 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x4)
240 0 : #define ACMP1_ACMPOUT_PD5 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x5)
241 :
242 0 : #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
243 0 : #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
244 0 : #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
245 0 : #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
246 0 : #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
247 0 : #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
248 0 : #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
249 0 : #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
250 0 : #define CMU_CLKOUT0_PC8 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x8)
251 0 : #define CMU_CLKOUT0_PC9 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x9)
252 0 : #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
253 0 : #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
254 0 : #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
255 0 : #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
256 0 : #define CMU_CLKOUT0_PD4 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x4)
257 0 : #define CMU_CLKOUT0_PD5 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x5)
258 0 : #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
259 0 : #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
260 0 : #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
261 0 : #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
262 0 : #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
263 0 : #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
264 0 : #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
265 0 : #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
266 0 : #define CMU_CLKOUT1_PC8 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x8)
267 0 : #define CMU_CLKOUT1_PC9 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x9)
268 0 : #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
269 0 : #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
270 0 : #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
271 0 : #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
272 0 : #define CMU_CLKOUT1_PD4 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x4)
273 0 : #define CMU_CLKOUT1_PD5 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x5)
274 0 : #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
275 0 : #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
276 0 : #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
277 0 : #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
278 0 : #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
279 0 : #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
280 0 : #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
281 0 : #define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
282 0 : #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
283 0 : #define CMU_CLKOUT2_PA9 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x9)
284 0 : #define CMU_CLKOUT2_PA10 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xa)
285 0 : #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
286 0 : #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
287 0 : #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
288 0 : #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
289 0 : #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
290 0 : #define CMU_CLKOUT2_PB5 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x5)
291 0 : #define CMU_CLKOUT2_PB6 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x6)
292 0 : #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
293 0 : #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
294 0 : #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
295 0 : #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
296 0 : #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
297 0 : #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
298 0 : #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
299 0 : #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
300 0 : #define CMU_CLKIN0_PC8 SILABS_DBUS_CMU_CLKIN0(0x2, 0x8)
301 0 : #define CMU_CLKIN0_PC9 SILABS_DBUS_CMU_CLKIN0(0x2, 0x9)
302 0 : #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
303 0 : #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
304 0 : #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
305 0 : #define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
306 0 : #define CMU_CLKIN0_PD4 SILABS_DBUS_CMU_CLKIN0(0x3, 0x4)
307 0 : #define CMU_CLKIN0_PD5 SILABS_DBUS_CMU_CLKIN0(0x3, 0x5)
308 :
309 0 : #define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0)
310 0 : #define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1)
311 0 : #define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2)
312 0 : #define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3)
313 0 : #define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4)
314 0 : #define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5)
315 0 : #define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6)
316 0 : #define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7)
317 0 : #define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8)
318 0 : #define EUSART0_CS_PA9 SILABS_DBUS_EUSART0_CS(0x0, 0x9)
319 0 : #define EUSART0_CS_PA10 SILABS_DBUS_EUSART0_CS(0x0, 0xa)
320 0 : #define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0)
321 0 : #define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1)
322 0 : #define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2)
323 0 : #define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3)
324 0 : #define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4)
325 0 : #define EUSART0_CS_PB5 SILABS_DBUS_EUSART0_CS(0x1, 0x5)
326 0 : #define EUSART0_CS_PB6 SILABS_DBUS_EUSART0_CS(0x1, 0x6)
327 0 : #define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0)
328 0 : #define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1)
329 0 : #define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2)
330 0 : #define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3)
331 0 : #define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4)
332 0 : #define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5)
333 0 : #define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6)
334 0 : #define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7)
335 0 : #define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8)
336 0 : #define EUSART0_RTS_PA9 SILABS_DBUS_EUSART0_RTS(0x0, 0x9)
337 0 : #define EUSART0_RTS_PA10 SILABS_DBUS_EUSART0_RTS(0x0, 0xa)
338 0 : #define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0)
339 0 : #define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1)
340 0 : #define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
341 0 : #define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
342 0 : #define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4)
343 0 : #define EUSART0_RTS_PB5 SILABS_DBUS_EUSART0_RTS(0x1, 0x5)
344 0 : #define EUSART0_RTS_PB6 SILABS_DBUS_EUSART0_RTS(0x1, 0x6)
345 0 : #define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0)
346 0 : #define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1)
347 0 : #define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2)
348 0 : #define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3)
349 0 : #define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4)
350 0 : #define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5)
351 0 : #define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6)
352 0 : #define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7)
353 0 : #define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8)
354 0 : #define EUSART0_RX_PA9 SILABS_DBUS_EUSART0_RX(0x0, 0x9)
355 0 : #define EUSART0_RX_PA10 SILABS_DBUS_EUSART0_RX(0x0, 0xa)
356 0 : #define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0)
357 0 : #define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1)
358 0 : #define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2)
359 0 : #define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3)
360 0 : #define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4)
361 0 : #define EUSART0_RX_PB5 SILABS_DBUS_EUSART0_RX(0x1, 0x5)
362 0 : #define EUSART0_RX_PB6 SILABS_DBUS_EUSART0_RX(0x1, 0x6)
363 0 : #define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0)
364 0 : #define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1)
365 0 : #define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2)
366 0 : #define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3)
367 0 : #define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4)
368 0 : #define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5)
369 0 : #define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6)
370 0 : #define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7)
371 0 : #define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8)
372 0 : #define EUSART0_SCLK_PA9 SILABS_DBUS_EUSART0_SCLK(0x0, 0x9)
373 0 : #define EUSART0_SCLK_PA10 SILABS_DBUS_EUSART0_SCLK(0x0, 0xa)
374 0 : #define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0)
375 0 : #define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1)
376 0 : #define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
377 0 : #define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
378 0 : #define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4)
379 0 : #define EUSART0_SCLK_PB5 SILABS_DBUS_EUSART0_SCLK(0x1, 0x5)
380 0 : #define EUSART0_SCLK_PB6 SILABS_DBUS_EUSART0_SCLK(0x1, 0x6)
381 0 : #define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0)
382 0 : #define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1)
383 0 : #define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2)
384 0 : #define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3)
385 0 : #define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4)
386 0 : #define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5)
387 0 : #define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6)
388 0 : #define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7)
389 0 : #define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8)
390 0 : #define EUSART0_TX_PA9 SILABS_DBUS_EUSART0_TX(0x0, 0x9)
391 0 : #define EUSART0_TX_PA10 SILABS_DBUS_EUSART0_TX(0x0, 0xa)
392 0 : #define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0)
393 0 : #define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1)
394 0 : #define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2)
395 0 : #define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3)
396 0 : #define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4)
397 0 : #define EUSART0_TX_PB5 SILABS_DBUS_EUSART0_TX(0x1, 0x5)
398 0 : #define EUSART0_TX_PB6 SILABS_DBUS_EUSART0_TX(0x1, 0x6)
399 0 : #define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0)
400 0 : #define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1)
401 0 : #define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2)
402 0 : #define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3)
403 0 : #define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4)
404 0 : #define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5)
405 0 : #define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6)
406 0 : #define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7)
407 0 : #define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8)
408 0 : #define EUSART0_CTS_PA9 SILABS_DBUS_EUSART0_CTS(0x0, 0x9)
409 0 : #define EUSART0_CTS_PA10 SILABS_DBUS_EUSART0_CTS(0x0, 0xa)
410 0 : #define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0)
411 0 : #define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1)
412 0 : #define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
413 0 : #define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
414 0 : #define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4)
415 0 : #define EUSART0_CTS_PB5 SILABS_DBUS_EUSART0_CTS(0x1, 0x5)
416 0 : #define EUSART0_CTS_PB6 SILABS_DBUS_EUSART0_CTS(0x1, 0x6)
417 :
418 0 : #define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0)
419 0 : #define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1)
420 0 : #define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2)
421 0 : #define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3)
422 0 : #define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4)
423 0 : #define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5)
424 0 : #define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6)
425 0 : #define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7)
426 0 : #define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8)
427 0 : #define EUSART1_CS_PA9 SILABS_DBUS_EUSART1_CS(0x0, 0x9)
428 0 : #define EUSART1_CS_PA10 SILABS_DBUS_EUSART1_CS(0x0, 0xa)
429 0 : #define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0)
430 0 : #define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1)
431 0 : #define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2)
432 0 : #define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3)
433 0 : #define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4)
434 0 : #define EUSART1_CS_PB5 SILABS_DBUS_EUSART1_CS(0x1, 0x5)
435 0 : #define EUSART1_CS_PB6 SILABS_DBUS_EUSART1_CS(0x1, 0x6)
436 0 : #define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0)
437 0 : #define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1)
438 0 : #define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2)
439 0 : #define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3)
440 0 : #define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4)
441 0 : #define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5)
442 0 : #define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6)
443 0 : #define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7)
444 0 : #define EUSART1_CS_PC8 SILABS_DBUS_EUSART1_CS(0x2, 0x8)
445 0 : #define EUSART1_CS_PC9 SILABS_DBUS_EUSART1_CS(0x2, 0x9)
446 0 : #define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0)
447 0 : #define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1)
448 0 : #define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2)
449 0 : #define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3)
450 0 : #define EUSART1_CS_PD4 SILABS_DBUS_EUSART1_CS(0x3, 0x4)
451 0 : #define EUSART1_CS_PD5 SILABS_DBUS_EUSART1_CS(0x3, 0x5)
452 0 : #define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0)
453 0 : #define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1)
454 0 : #define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2)
455 0 : #define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3)
456 0 : #define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4)
457 0 : #define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5)
458 0 : #define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6)
459 0 : #define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7)
460 0 : #define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8)
461 0 : #define EUSART1_RTS_PA9 SILABS_DBUS_EUSART1_RTS(0x0, 0x9)
462 0 : #define EUSART1_RTS_PA10 SILABS_DBUS_EUSART1_RTS(0x0, 0xa)
463 0 : #define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0)
464 0 : #define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1)
465 0 : #define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2)
466 0 : #define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3)
467 0 : #define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4)
468 0 : #define EUSART1_RTS_PB5 SILABS_DBUS_EUSART1_RTS(0x1, 0x5)
469 0 : #define EUSART1_RTS_PB6 SILABS_DBUS_EUSART1_RTS(0x1, 0x6)
470 0 : #define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0)
471 0 : #define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1)
472 0 : #define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2)
473 0 : #define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3)
474 0 : #define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4)
475 0 : #define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5)
476 0 : #define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6)
477 0 : #define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7)
478 0 : #define EUSART1_RTS_PC8 SILABS_DBUS_EUSART1_RTS(0x2, 0x8)
479 0 : #define EUSART1_RTS_PC9 SILABS_DBUS_EUSART1_RTS(0x2, 0x9)
480 0 : #define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0)
481 0 : #define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1)
482 0 : #define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2)
483 0 : #define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3)
484 0 : #define EUSART1_RTS_PD4 SILABS_DBUS_EUSART1_RTS(0x3, 0x4)
485 0 : #define EUSART1_RTS_PD5 SILABS_DBUS_EUSART1_RTS(0x3, 0x5)
486 0 : #define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0)
487 0 : #define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1)
488 0 : #define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2)
489 0 : #define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3)
490 0 : #define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4)
491 0 : #define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5)
492 0 : #define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6)
493 0 : #define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7)
494 0 : #define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8)
495 0 : #define EUSART1_RX_PA9 SILABS_DBUS_EUSART1_RX(0x0, 0x9)
496 0 : #define EUSART1_RX_PA10 SILABS_DBUS_EUSART1_RX(0x0, 0xa)
497 0 : #define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0)
498 0 : #define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1)
499 0 : #define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2)
500 0 : #define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3)
501 0 : #define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4)
502 0 : #define EUSART1_RX_PB5 SILABS_DBUS_EUSART1_RX(0x1, 0x5)
503 0 : #define EUSART1_RX_PB6 SILABS_DBUS_EUSART1_RX(0x1, 0x6)
504 0 : #define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0)
505 0 : #define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1)
506 0 : #define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2)
507 0 : #define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3)
508 0 : #define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4)
509 0 : #define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5)
510 0 : #define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6)
511 0 : #define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7)
512 0 : #define EUSART1_RX_PC8 SILABS_DBUS_EUSART1_RX(0x2, 0x8)
513 0 : #define EUSART1_RX_PC9 SILABS_DBUS_EUSART1_RX(0x2, 0x9)
514 0 : #define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0)
515 0 : #define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1)
516 0 : #define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2)
517 0 : #define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3)
518 0 : #define EUSART1_RX_PD4 SILABS_DBUS_EUSART1_RX(0x3, 0x4)
519 0 : #define EUSART1_RX_PD5 SILABS_DBUS_EUSART1_RX(0x3, 0x5)
520 0 : #define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0)
521 0 : #define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1)
522 0 : #define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2)
523 0 : #define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3)
524 0 : #define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4)
525 0 : #define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5)
526 0 : #define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6)
527 0 : #define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7)
528 0 : #define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8)
529 0 : #define EUSART1_SCLK_PA9 SILABS_DBUS_EUSART1_SCLK(0x0, 0x9)
530 0 : #define EUSART1_SCLK_PA10 SILABS_DBUS_EUSART1_SCLK(0x0, 0xa)
531 0 : #define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0)
532 0 : #define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1)
533 0 : #define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2)
534 0 : #define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3)
535 0 : #define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4)
536 0 : #define EUSART1_SCLK_PB5 SILABS_DBUS_EUSART1_SCLK(0x1, 0x5)
537 0 : #define EUSART1_SCLK_PB6 SILABS_DBUS_EUSART1_SCLK(0x1, 0x6)
538 0 : #define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0)
539 0 : #define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1)
540 0 : #define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2)
541 0 : #define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3)
542 0 : #define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4)
543 0 : #define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5)
544 0 : #define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6)
545 0 : #define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7)
546 0 : #define EUSART1_SCLK_PC8 SILABS_DBUS_EUSART1_SCLK(0x2, 0x8)
547 0 : #define EUSART1_SCLK_PC9 SILABS_DBUS_EUSART1_SCLK(0x2, 0x9)
548 0 : #define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0)
549 0 : #define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1)
550 0 : #define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2)
551 0 : #define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3)
552 0 : #define EUSART1_SCLK_PD4 SILABS_DBUS_EUSART1_SCLK(0x3, 0x4)
553 0 : #define EUSART1_SCLK_PD5 SILABS_DBUS_EUSART1_SCLK(0x3, 0x5)
554 0 : #define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0)
555 0 : #define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1)
556 0 : #define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2)
557 0 : #define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3)
558 0 : #define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4)
559 0 : #define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5)
560 0 : #define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6)
561 0 : #define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7)
562 0 : #define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8)
563 0 : #define EUSART1_TX_PA9 SILABS_DBUS_EUSART1_TX(0x0, 0x9)
564 0 : #define EUSART1_TX_PA10 SILABS_DBUS_EUSART1_TX(0x0, 0xa)
565 0 : #define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0)
566 0 : #define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1)
567 0 : #define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2)
568 0 : #define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3)
569 0 : #define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4)
570 0 : #define EUSART1_TX_PB5 SILABS_DBUS_EUSART1_TX(0x1, 0x5)
571 0 : #define EUSART1_TX_PB6 SILABS_DBUS_EUSART1_TX(0x1, 0x6)
572 0 : #define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0)
573 0 : #define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1)
574 0 : #define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2)
575 0 : #define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3)
576 0 : #define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4)
577 0 : #define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5)
578 0 : #define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6)
579 0 : #define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7)
580 0 : #define EUSART1_TX_PC8 SILABS_DBUS_EUSART1_TX(0x2, 0x8)
581 0 : #define EUSART1_TX_PC9 SILABS_DBUS_EUSART1_TX(0x2, 0x9)
582 0 : #define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0)
583 0 : #define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1)
584 0 : #define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2)
585 0 : #define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3)
586 0 : #define EUSART1_TX_PD4 SILABS_DBUS_EUSART1_TX(0x3, 0x4)
587 0 : #define EUSART1_TX_PD5 SILABS_DBUS_EUSART1_TX(0x3, 0x5)
588 0 : #define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0)
589 0 : #define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1)
590 0 : #define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2)
591 0 : #define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3)
592 0 : #define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4)
593 0 : #define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5)
594 0 : #define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6)
595 0 : #define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7)
596 0 : #define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8)
597 0 : #define EUSART1_CTS_PA9 SILABS_DBUS_EUSART1_CTS(0x0, 0x9)
598 0 : #define EUSART1_CTS_PA10 SILABS_DBUS_EUSART1_CTS(0x0, 0xa)
599 0 : #define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0)
600 0 : #define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1)
601 0 : #define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2)
602 0 : #define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3)
603 0 : #define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4)
604 0 : #define EUSART1_CTS_PB5 SILABS_DBUS_EUSART1_CTS(0x1, 0x5)
605 0 : #define EUSART1_CTS_PB6 SILABS_DBUS_EUSART1_CTS(0x1, 0x6)
606 0 : #define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0)
607 0 : #define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1)
608 0 : #define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2)
609 0 : #define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3)
610 0 : #define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4)
611 0 : #define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5)
612 0 : #define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6)
613 0 : #define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7)
614 0 : #define EUSART1_CTS_PC8 SILABS_DBUS_EUSART1_CTS(0x2, 0x8)
615 0 : #define EUSART1_CTS_PC9 SILABS_DBUS_EUSART1_CTS(0x2, 0x9)
616 0 : #define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0)
617 0 : #define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1)
618 0 : #define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2)
619 0 : #define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3)
620 0 : #define EUSART1_CTS_PD4 SILABS_DBUS_EUSART1_CTS(0x3, 0x4)
621 0 : #define EUSART1_CTS_PD5 SILABS_DBUS_EUSART1_CTS(0x3, 0x5)
622 :
623 0 : #define EUSART2_CS_PC0 SILABS_DBUS_EUSART2_CS(0x2, 0x0)
624 0 : #define EUSART2_CS_PC1 SILABS_DBUS_EUSART2_CS(0x2, 0x1)
625 0 : #define EUSART2_CS_PC2 SILABS_DBUS_EUSART2_CS(0x2, 0x2)
626 0 : #define EUSART2_CS_PC3 SILABS_DBUS_EUSART2_CS(0x2, 0x3)
627 0 : #define EUSART2_CS_PC4 SILABS_DBUS_EUSART2_CS(0x2, 0x4)
628 0 : #define EUSART2_CS_PC5 SILABS_DBUS_EUSART2_CS(0x2, 0x5)
629 0 : #define EUSART2_CS_PC6 SILABS_DBUS_EUSART2_CS(0x2, 0x6)
630 0 : #define EUSART2_CS_PC7 SILABS_DBUS_EUSART2_CS(0x2, 0x7)
631 0 : #define EUSART2_CS_PC8 SILABS_DBUS_EUSART2_CS(0x2, 0x8)
632 0 : #define EUSART2_CS_PC9 SILABS_DBUS_EUSART2_CS(0x2, 0x9)
633 0 : #define EUSART2_CS_PD0 SILABS_DBUS_EUSART2_CS(0x3, 0x0)
634 0 : #define EUSART2_CS_PD1 SILABS_DBUS_EUSART2_CS(0x3, 0x1)
635 0 : #define EUSART2_CS_PD2 SILABS_DBUS_EUSART2_CS(0x3, 0x2)
636 0 : #define EUSART2_CS_PD3 SILABS_DBUS_EUSART2_CS(0x3, 0x3)
637 0 : #define EUSART2_CS_PD4 SILABS_DBUS_EUSART2_CS(0x3, 0x4)
638 0 : #define EUSART2_CS_PD5 SILABS_DBUS_EUSART2_CS(0x3, 0x5)
639 0 : #define EUSART2_RTS_PC0 SILABS_DBUS_EUSART2_RTS(0x2, 0x0)
640 0 : #define EUSART2_RTS_PC1 SILABS_DBUS_EUSART2_RTS(0x2, 0x1)
641 0 : #define EUSART2_RTS_PC2 SILABS_DBUS_EUSART2_RTS(0x2, 0x2)
642 0 : #define EUSART2_RTS_PC3 SILABS_DBUS_EUSART2_RTS(0x2, 0x3)
643 0 : #define EUSART2_RTS_PC4 SILABS_DBUS_EUSART2_RTS(0x2, 0x4)
644 0 : #define EUSART2_RTS_PC5 SILABS_DBUS_EUSART2_RTS(0x2, 0x5)
645 0 : #define EUSART2_RTS_PC6 SILABS_DBUS_EUSART2_RTS(0x2, 0x6)
646 0 : #define EUSART2_RTS_PC7 SILABS_DBUS_EUSART2_RTS(0x2, 0x7)
647 0 : #define EUSART2_RTS_PC8 SILABS_DBUS_EUSART2_RTS(0x2, 0x8)
648 0 : #define EUSART2_RTS_PC9 SILABS_DBUS_EUSART2_RTS(0x2, 0x9)
649 0 : #define EUSART2_RTS_PD0 SILABS_DBUS_EUSART2_RTS(0x3, 0x0)
650 0 : #define EUSART2_RTS_PD1 SILABS_DBUS_EUSART2_RTS(0x3, 0x1)
651 0 : #define EUSART2_RTS_PD2 SILABS_DBUS_EUSART2_RTS(0x3, 0x2)
652 0 : #define EUSART2_RTS_PD3 SILABS_DBUS_EUSART2_RTS(0x3, 0x3)
653 0 : #define EUSART2_RTS_PD4 SILABS_DBUS_EUSART2_RTS(0x3, 0x4)
654 0 : #define EUSART2_RTS_PD5 SILABS_DBUS_EUSART2_RTS(0x3, 0x5)
655 0 : #define EUSART2_RX_PC0 SILABS_DBUS_EUSART2_RX(0x2, 0x0)
656 0 : #define EUSART2_RX_PC1 SILABS_DBUS_EUSART2_RX(0x2, 0x1)
657 0 : #define EUSART2_RX_PC2 SILABS_DBUS_EUSART2_RX(0x2, 0x2)
658 0 : #define EUSART2_RX_PC3 SILABS_DBUS_EUSART2_RX(0x2, 0x3)
659 0 : #define EUSART2_RX_PC4 SILABS_DBUS_EUSART2_RX(0x2, 0x4)
660 0 : #define EUSART2_RX_PC5 SILABS_DBUS_EUSART2_RX(0x2, 0x5)
661 0 : #define EUSART2_RX_PC6 SILABS_DBUS_EUSART2_RX(0x2, 0x6)
662 0 : #define EUSART2_RX_PC7 SILABS_DBUS_EUSART2_RX(0x2, 0x7)
663 0 : #define EUSART2_RX_PC8 SILABS_DBUS_EUSART2_RX(0x2, 0x8)
664 0 : #define EUSART2_RX_PC9 SILABS_DBUS_EUSART2_RX(0x2, 0x9)
665 0 : #define EUSART2_RX_PD0 SILABS_DBUS_EUSART2_RX(0x3, 0x0)
666 0 : #define EUSART2_RX_PD1 SILABS_DBUS_EUSART2_RX(0x3, 0x1)
667 0 : #define EUSART2_RX_PD2 SILABS_DBUS_EUSART2_RX(0x3, 0x2)
668 0 : #define EUSART2_RX_PD3 SILABS_DBUS_EUSART2_RX(0x3, 0x3)
669 0 : #define EUSART2_RX_PD4 SILABS_DBUS_EUSART2_RX(0x3, 0x4)
670 0 : #define EUSART2_RX_PD5 SILABS_DBUS_EUSART2_RX(0x3, 0x5)
671 0 : #define EUSART2_SCLK_PC0 SILABS_DBUS_EUSART2_SCLK(0x2, 0x0)
672 0 : #define EUSART2_SCLK_PC1 SILABS_DBUS_EUSART2_SCLK(0x2, 0x1)
673 0 : #define EUSART2_SCLK_PC2 SILABS_DBUS_EUSART2_SCLK(0x2, 0x2)
674 0 : #define EUSART2_SCLK_PC3 SILABS_DBUS_EUSART2_SCLK(0x2, 0x3)
675 0 : #define EUSART2_SCLK_PC4 SILABS_DBUS_EUSART2_SCLK(0x2, 0x4)
676 0 : #define EUSART2_SCLK_PC5 SILABS_DBUS_EUSART2_SCLK(0x2, 0x5)
677 0 : #define EUSART2_SCLK_PC6 SILABS_DBUS_EUSART2_SCLK(0x2, 0x6)
678 0 : #define EUSART2_SCLK_PC7 SILABS_DBUS_EUSART2_SCLK(0x2, 0x7)
679 0 : #define EUSART2_SCLK_PC8 SILABS_DBUS_EUSART2_SCLK(0x2, 0x8)
680 0 : #define EUSART2_SCLK_PC9 SILABS_DBUS_EUSART2_SCLK(0x2, 0x9)
681 0 : #define EUSART2_SCLK_PD0 SILABS_DBUS_EUSART2_SCLK(0x3, 0x0)
682 0 : #define EUSART2_SCLK_PD1 SILABS_DBUS_EUSART2_SCLK(0x3, 0x1)
683 0 : #define EUSART2_SCLK_PD2 SILABS_DBUS_EUSART2_SCLK(0x3, 0x2)
684 0 : #define EUSART2_SCLK_PD3 SILABS_DBUS_EUSART2_SCLK(0x3, 0x3)
685 0 : #define EUSART2_SCLK_PD4 SILABS_DBUS_EUSART2_SCLK(0x3, 0x4)
686 0 : #define EUSART2_SCLK_PD5 SILABS_DBUS_EUSART2_SCLK(0x3, 0x5)
687 0 : #define EUSART2_TX_PC0 SILABS_DBUS_EUSART2_TX(0x2, 0x0)
688 0 : #define EUSART2_TX_PC1 SILABS_DBUS_EUSART2_TX(0x2, 0x1)
689 0 : #define EUSART2_TX_PC2 SILABS_DBUS_EUSART2_TX(0x2, 0x2)
690 0 : #define EUSART2_TX_PC3 SILABS_DBUS_EUSART2_TX(0x2, 0x3)
691 0 : #define EUSART2_TX_PC4 SILABS_DBUS_EUSART2_TX(0x2, 0x4)
692 0 : #define EUSART2_TX_PC5 SILABS_DBUS_EUSART2_TX(0x2, 0x5)
693 0 : #define EUSART2_TX_PC6 SILABS_DBUS_EUSART2_TX(0x2, 0x6)
694 0 : #define EUSART2_TX_PC7 SILABS_DBUS_EUSART2_TX(0x2, 0x7)
695 0 : #define EUSART2_TX_PC8 SILABS_DBUS_EUSART2_TX(0x2, 0x8)
696 0 : #define EUSART2_TX_PC9 SILABS_DBUS_EUSART2_TX(0x2, 0x9)
697 0 : #define EUSART2_TX_PD0 SILABS_DBUS_EUSART2_TX(0x3, 0x0)
698 0 : #define EUSART2_TX_PD1 SILABS_DBUS_EUSART2_TX(0x3, 0x1)
699 0 : #define EUSART2_TX_PD2 SILABS_DBUS_EUSART2_TX(0x3, 0x2)
700 0 : #define EUSART2_TX_PD3 SILABS_DBUS_EUSART2_TX(0x3, 0x3)
701 0 : #define EUSART2_TX_PD4 SILABS_DBUS_EUSART2_TX(0x3, 0x4)
702 0 : #define EUSART2_TX_PD5 SILABS_DBUS_EUSART2_TX(0x3, 0x5)
703 0 : #define EUSART2_CTS_PC0 SILABS_DBUS_EUSART2_CTS(0x2, 0x0)
704 0 : #define EUSART2_CTS_PC1 SILABS_DBUS_EUSART2_CTS(0x2, 0x1)
705 0 : #define EUSART2_CTS_PC2 SILABS_DBUS_EUSART2_CTS(0x2, 0x2)
706 0 : #define EUSART2_CTS_PC3 SILABS_DBUS_EUSART2_CTS(0x2, 0x3)
707 0 : #define EUSART2_CTS_PC4 SILABS_DBUS_EUSART2_CTS(0x2, 0x4)
708 0 : #define EUSART2_CTS_PC5 SILABS_DBUS_EUSART2_CTS(0x2, 0x5)
709 0 : #define EUSART2_CTS_PC6 SILABS_DBUS_EUSART2_CTS(0x2, 0x6)
710 0 : #define EUSART2_CTS_PC7 SILABS_DBUS_EUSART2_CTS(0x2, 0x7)
711 0 : #define EUSART2_CTS_PC8 SILABS_DBUS_EUSART2_CTS(0x2, 0x8)
712 0 : #define EUSART2_CTS_PC9 SILABS_DBUS_EUSART2_CTS(0x2, 0x9)
713 0 : #define EUSART2_CTS_PD0 SILABS_DBUS_EUSART2_CTS(0x3, 0x0)
714 0 : #define EUSART2_CTS_PD1 SILABS_DBUS_EUSART2_CTS(0x3, 0x1)
715 0 : #define EUSART2_CTS_PD2 SILABS_DBUS_EUSART2_CTS(0x3, 0x2)
716 0 : #define EUSART2_CTS_PD3 SILABS_DBUS_EUSART2_CTS(0x3, 0x3)
717 0 : #define EUSART2_CTS_PD4 SILABS_DBUS_EUSART2_CTS(0x3, 0x4)
718 0 : #define EUSART2_CTS_PD5 SILABS_DBUS_EUSART2_CTS(0x3, 0x5)
719 :
720 0 : #define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0)
721 0 : #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
722 0 : #define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2)
723 0 : #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
724 0 : #define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4)
725 0 : #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
726 0 : #define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6)
727 0 : #define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7)
728 0 : #define PTI_DCLK_PC8 SILABS_DBUS_PTI_DCLK(0x2, 0x8)
729 0 : #define PTI_DCLK_PC9 SILABS_DBUS_PTI_DCLK(0x2, 0x9)
730 0 : #define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0)
731 0 : #define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1)
732 0 : #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
733 0 : #define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3)
734 0 : #define PTI_DCLK_PD4 SILABS_DBUS_PTI_DCLK(0x3, 0x4)
735 0 : #define PTI_DCLK_PD5 SILABS_DBUS_PTI_DCLK(0x3, 0x5)
736 0 : #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
737 0 : #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
738 0 : #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
739 0 : #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
740 0 : #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
741 0 : #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
742 0 : #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
743 0 : #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
744 0 : #define PTI_DFRAME_PC8 SILABS_DBUS_PTI_DFRAME(0x2, 0x8)
745 0 : #define PTI_DFRAME_PC9 SILABS_DBUS_PTI_DFRAME(0x2, 0x9)
746 0 : #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
747 0 : #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
748 0 : #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
749 0 : #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
750 0 : #define PTI_DFRAME_PD4 SILABS_DBUS_PTI_DFRAME(0x3, 0x4)
751 0 : #define PTI_DFRAME_PD5 SILABS_DBUS_PTI_DFRAME(0x3, 0x5)
752 0 : #define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0)
753 0 : #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
754 0 : #define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2)
755 0 : #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
756 0 : #define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4)
757 0 : #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
758 0 : #define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6)
759 0 : #define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7)
760 0 : #define PTI_DOUT_PC8 SILABS_DBUS_PTI_DOUT(0x2, 0x8)
761 0 : #define PTI_DOUT_PC9 SILABS_DBUS_PTI_DOUT(0x2, 0x9)
762 0 : #define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0)
763 0 : #define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1)
764 0 : #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
765 0 : #define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3)
766 0 : #define PTI_DOUT_PD4 SILABS_DBUS_PTI_DOUT(0x3, 0x4)
767 0 : #define PTI_DOUT_PD5 SILABS_DBUS_PTI_DOUT(0x3, 0x5)
768 :
769 0 : #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
770 0 : #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
771 0 : #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
772 0 : #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
773 0 : #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
774 0 : #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
775 0 : #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
776 0 : #define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
777 0 : #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
778 0 : #define I2C0_SCL_PA9 SILABS_DBUS_I2C0_SCL(0x0, 0x9)
779 0 : #define I2C0_SCL_PA10 SILABS_DBUS_I2C0_SCL(0x0, 0xa)
780 0 : #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
781 0 : #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
782 0 : #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
783 0 : #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
784 0 : #define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
785 0 : #define I2C0_SCL_PB5 SILABS_DBUS_I2C0_SCL(0x1, 0x5)
786 0 : #define I2C0_SCL_PB6 SILABS_DBUS_I2C0_SCL(0x1, 0x6)
787 0 : #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
788 0 : #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
789 0 : #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
790 0 : #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
791 0 : #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
792 0 : #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
793 0 : #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
794 0 : #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
795 0 : #define I2C0_SCL_PC8 SILABS_DBUS_I2C0_SCL(0x2, 0x8)
796 0 : #define I2C0_SCL_PC9 SILABS_DBUS_I2C0_SCL(0x2, 0x9)
797 0 : #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
798 0 : #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
799 0 : #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
800 0 : #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
801 0 : #define I2C0_SCL_PD4 SILABS_DBUS_I2C0_SCL(0x3, 0x4)
802 0 : #define I2C0_SCL_PD5 SILABS_DBUS_I2C0_SCL(0x3, 0x5)
803 0 : #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
804 0 : #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
805 0 : #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
806 0 : #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
807 0 : #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
808 0 : #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
809 0 : #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
810 0 : #define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
811 0 : #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
812 0 : #define I2C0_SDA_PA9 SILABS_DBUS_I2C0_SDA(0x0, 0x9)
813 0 : #define I2C0_SDA_PA10 SILABS_DBUS_I2C0_SDA(0x0, 0xa)
814 0 : #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
815 0 : #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
816 0 : #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
817 0 : #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
818 0 : #define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
819 0 : #define I2C0_SDA_PB5 SILABS_DBUS_I2C0_SDA(0x1, 0x5)
820 0 : #define I2C0_SDA_PB6 SILABS_DBUS_I2C0_SDA(0x1, 0x6)
821 0 : #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
822 0 : #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
823 0 : #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
824 0 : #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
825 0 : #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
826 0 : #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
827 0 : #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
828 0 : #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
829 0 : #define I2C0_SDA_PC8 SILABS_DBUS_I2C0_SDA(0x2, 0x8)
830 0 : #define I2C0_SDA_PC9 SILABS_DBUS_I2C0_SDA(0x2, 0x9)
831 0 : #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
832 0 : #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
833 0 : #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
834 0 : #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
835 0 : #define I2C0_SDA_PD4 SILABS_DBUS_I2C0_SDA(0x3, 0x4)
836 0 : #define I2C0_SDA_PD5 SILABS_DBUS_I2C0_SDA(0x3, 0x5)
837 :
838 0 : #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
839 0 : #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
840 0 : #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
841 0 : #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
842 0 : #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
843 0 : #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
844 0 : #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
845 0 : #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
846 0 : #define I2C1_SCL_PC8 SILABS_DBUS_I2C1_SCL(0x2, 0x8)
847 0 : #define I2C1_SCL_PC9 SILABS_DBUS_I2C1_SCL(0x2, 0x9)
848 0 : #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
849 0 : #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
850 0 : #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
851 0 : #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
852 0 : #define I2C1_SCL_PD4 SILABS_DBUS_I2C1_SCL(0x3, 0x4)
853 0 : #define I2C1_SCL_PD5 SILABS_DBUS_I2C1_SCL(0x3, 0x5)
854 0 : #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
855 0 : #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
856 0 : #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
857 0 : #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
858 0 : #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
859 0 : #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
860 0 : #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
861 0 : #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
862 0 : #define I2C1_SDA_PC8 SILABS_DBUS_I2C1_SDA(0x2, 0x8)
863 0 : #define I2C1_SDA_PC9 SILABS_DBUS_I2C1_SDA(0x2, 0x9)
864 0 : #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
865 0 : #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
866 0 : #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
867 0 : #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
868 0 : #define I2C1_SDA_PD4 SILABS_DBUS_I2C1_SDA(0x3, 0x4)
869 0 : #define I2C1_SDA_PD5 SILABS_DBUS_I2C1_SDA(0x3, 0x5)
870 :
871 0 : #define KEYSCAN_COLOUT0_PA0 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x0)
872 0 : #define KEYSCAN_COLOUT0_PA1 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x1)
873 0 : #define KEYSCAN_COLOUT0_PA2 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x2)
874 0 : #define KEYSCAN_COLOUT0_PA3 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x3)
875 0 : #define KEYSCAN_COLOUT0_PA4 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x4)
876 0 : #define KEYSCAN_COLOUT0_PA5 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x5)
877 0 : #define KEYSCAN_COLOUT0_PA6 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x6)
878 0 : #define KEYSCAN_COLOUT0_PA7 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x7)
879 0 : #define KEYSCAN_COLOUT0_PA8 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x8)
880 0 : #define KEYSCAN_COLOUT0_PA9 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x9)
881 0 : #define KEYSCAN_COLOUT0_PA10 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xa)
882 0 : #define KEYSCAN_COLOUT0_PB0 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x0)
883 0 : #define KEYSCAN_COLOUT0_PB1 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x1)
884 0 : #define KEYSCAN_COLOUT0_PB2 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x2)
885 0 : #define KEYSCAN_COLOUT0_PB3 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x3)
886 0 : #define KEYSCAN_COLOUT0_PB4 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x4)
887 0 : #define KEYSCAN_COLOUT0_PB5 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x5)
888 0 : #define KEYSCAN_COLOUT0_PB6 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x6)
889 0 : #define KEYSCAN_COLOUT0_PC0 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x0)
890 0 : #define KEYSCAN_COLOUT0_PC1 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x1)
891 0 : #define KEYSCAN_COLOUT0_PC2 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x2)
892 0 : #define KEYSCAN_COLOUT0_PC3 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x3)
893 0 : #define KEYSCAN_COLOUT0_PC4 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x4)
894 0 : #define KEYSCAN_COLOUT0_PC5 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x5)
895 0 : #define KEYSCAN_COLOUT0_PC6 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x6)
896 0 : #define KEYSCAN_COLOUT0_PC7 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x7)
897 0 : #define KEYSCAN_COLOUT0_PC8 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x8)
898 0 : #define KEYSCAN_COLOUT0_PC9 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x9)
899 0 : #define KEYSCAN_COLOUT0_PD0 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x0)
900 0 : #define KEYSCAN_COLOUT0_PD1 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x1)
901 0 : #define KEYSCAN_COLOUT0_PD2 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x2)
902 0 : #define KEYSCAN_COLOUT0_PD3 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x3)
903 0 : #define KEYSCAN_COLOUT0_PD4 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x4)
904 0 : #define KEYSCAN_COLOUT0_PD5 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x5)
905 0 : #define KEYSCAN_COLOUT1_PA0 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x0)
906 0 : #define KEYSCAN_COLOUT1_PA1 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x1)
907 0 : #define KEYSCAN_COLOUT1_PA2 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x2)
908 0 : #define KEYSCAN_COLOUT1_PA3 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x3)
909 0 : #define KEYSCAN_COLOUT1_PA4 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x4)
910 0 : #define KEYSCAN_COLOUT1_PA5 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x5)
911 0 : #define KEYSCAN_COLOUT1_PA6 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x6)
912 0 : #define KEYSCAN_COLOUT1_PA7 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x7)
913 0 : #define KEYSCAN_COLOUT1_PA8 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x8)
914 0 : #define KEYSCAN_COLOUT1_PA9 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x9)
915 0 : #define KEYSCAN_COLOUT1_PA10 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xa)
916 0 : #define KEYSCAN_COLOUT1_PB0 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x0)
917 0 : #define KEYSCAN_COLOUT1_PB1 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x1)
918 0 : #define KEYSCAN_COLOUT1_PB2 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x2)
919 0 : #define KEYSCAN_COLOUT1_PB3 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x3)
920 0 : #define KEYSCAN_COLOUT1_PB4 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x4)
921 0 : #define KEYSCAN_COLOUT1_PB5 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x5)
922 0 : #define KEYSCAN_COLOUT1_PB6 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x6)
923 0 : #define KEYSCAN_COLOUT1_PC0 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x0)
924 0 : #define KEYSCAN_COLOUT1_PC1 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x1)
925 0 : #define KEYSCAN_COLOUT1_PC2 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x2)
926 0 : #define KEYSCAN_COLOUT1_PC3 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x3)
927 0 : #define KEYSCAN_COLOUT1_PC4 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x4)
928 0 : #define KEYSCAN_COLOUT1_PC5 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x5)
929 0 : #define KEYSCAN_COLOUT1_PC6 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x6)
930 0 : #define KEYSCAN_COLOUT1_PC7 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x7)
931 0 : #define KEYSCAN_COLOUT1_PC8 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x8)
932 0 : #define KEYSCAN_COLOUT1_PC9 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x9)
933 0 : #define KEYSCAN_COLOUT1_PD0 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x0)
934 0 : #define KEYSCAN_COLOUT1_PD1 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x1)
935 0 : #define KEYSCAN_COLOUT1_PD2 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x2)
936 0 : #define KEYSCAN_COLOUT1_PD3 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x3)
937 0 : #define KEYSCAN_COLOUT1_PD4 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x4)
938 0 : #define KEYSCAN_COLOUT1_PD5 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x5)
939 0 : #define KEYSCAN_COLOUT2_PA0 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x0)
940 0 : #define KEYSCAN_COLOUT2_PA1 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x1)
941 0 : #define KEYSCAN_COLOUT2_PA2 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x2)
942 0 : #define KEYSCAN_COLOUT2_PA3 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x3)
943 0 : #define KEYSCAN_COLOUT2_PA4 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x4)
944 0 : #define KEYSCAN_COLOUT2_PA5 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x5)
945 0 : #define KEYSCAN_COLOUT2_PA6 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x6)
946 0 : #define KEYSCAN_COLOUT2_PA7 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x7)
947 0 : #define KEYSCAN_COLOUT2_PA8 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x8)
948 0 : #define KEYSCAN_COLOUT2_PA9 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x9)
949 0 : #define KEYSCAN_COLOUT2_PA10 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xa)
950 0 : #define KEYSCAN_COLOUT2_PB0 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x0)
951 0 : #define KEYSCAN_COLOUT2_PB1 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x1)
952 0 : #define KEYSCAN_COLOUT2_PB2 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x2)
953 0 : #define KEYSCAN_COLOUT2_PB3 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x3)
954 0 : #define KEYSCAN_COLOUT2_PB4 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x4)
955 0 : #define KEYSCAN_COLOUT2_PB5 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x5)
956 0 : #define KEYSCAN_COLOUT2_PB6 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x6)
957 0 : #define KEYSCAN_COLOUT2_PC0 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x0)
958 0 : #define KEYSCAN_COLOUT2_PC1 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x1)
959 0 : #define KEYSCAN_COLOUT2_PC2 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x2)
960 0 : #define KEYSCAN_COLOUT2_PC3 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x3)
961 0 : #define KEYSCAN_COLOUT2_PC4 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x4)
962 0 : #define KEYSCAN_COLOUT2_PC5 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x5)
963 0 : #define KEYSCAN_COLOUT2_PC6 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x6)
964 0 : #define KEYSCAN_COLOUT2_PC7 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x7)
965 0 : #define KEYSCAN_COLOUT2_PC8 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x8)
966 0 : #define KEYSCAN_COLOUT2_PC9 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x9)
967 0 : #define KEYSCAN_COLOUT2_PD0 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x0)
968 0 : #define KEYSCAN_COLOUT2_PD1 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x1)
969 0 : #define KEYSCAN_COLOUT2_PD2 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x2)
970 0 : #define KEYSCAN_COLOUT2_PD3 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x3)
971 0 : #define KEYSCAN_COLOUT2_PD4 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x4)
972 0 : #define KEYSCAN_COLOUT2_PD5 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x5)
973 0 : #define KEYSCAN_COLOUT3_PA0 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x0)
974 0 : #define KEYSCAN_COLOUT3_PA1 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x1)
975 0 : #define KEYSCAN_COLOUT3_PA2 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x2)
976 0 : #define KEYSCAN_COLOUT3_PA3 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x3)
977 0 : #define KEYSCAN_COLOUT3_PA4 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x4)
978 0 : #define KEYSCAN_COLOUT3_PA5 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x5)
979 0 : #define KEYSCAN_COLOUT3_PA6 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x6)
980 0 : #define KEYSCAN_COLOUT3_PA7 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x7)
981 0 : #define KEYSCAN_COLOUT3_PA8 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x8)
982 0 : #define KEYSCAN_COLOUT3_PA9 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x9)
983 0 : #define KEYSCAN_COLOUT3_PA10 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xa)
984 0 : #define KEYSCAN_COLOUT3_PB0 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x0)
985 0 : #define KEYSCAN_COLOUT3_PB1 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x1)
986 0 : #define KEYSCAN_COLOUT3_PB2 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x2)
987 0 : #define KEYSCAN_COLOUT3_PB3 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x3)
988 0 : #define KEYSCAN_COLOUT3_PB4 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x4)
989 0 : #define KEYSCAN_COLOUT3_PB5 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x5)
990 0 : #define KEYSCAN_COLOUT3_PB6 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x6)
991 0 : #define KEYSCAN_COLOUT3_PC0 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x0)
992 0 : #define KEYSCAN_COLOUT3_PC1 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x1)
993 0 : #define KEYSCAN_COLOUT3_PC2 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x2)
994 0 : #define KEYSCAN_COLOUT3_PC3 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x3)
995 0 : #define KEYSCAN_COLOUT3_PC4 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x4)
996 0 : #define KEYSCAN_COLOUT3_PC5 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x5)
997 0 : #define KEYSCAN_COLOUT3_PC6 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x6)
998 0 : #define KEYSCAN_COLOUT3_PC7 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x7)
999 0 : #define KEYSCAN_COLOUT3_PC8 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x8)
1000 0 : #define KEYSCAN_COLOUT3_PC9 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x9)
1001 0 : #define KEYSCAN_COLOUT3_PD0 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x0)
1002 0 : #define KEYSCAN_COLOUT3_PD1 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x1)
1003 0 : #define KEYSCAN_COLOUT3_PD2 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x2)
1004 0 : #define KEYSCAN_COLOUT3_PD3 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x3)
1005 0 : #define KEYSCAN_COLOUT3_PD4 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x4)
1006 0 : #define KEYSCAN_COLOUT3_PD5 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x5)
1007 0 : #define KEYSCAN_COLOUT4_PA0 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x0)
1008 0 : #define KEYSCAN_COLOUT4_PA1 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x1)
1009 0 : #define KEYSCAN_COLOUT4_PA2 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x2)
1010 0 : #define KEYSCAN_COLOUT4_PA3 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x3)
1011 0 : #define KEYSCAN_COLOUT4_PA4 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x4)
1012 0 : #define KEYSCAN_COLOUT4_PA5 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x5)
1013 0 : #define KEYSCAN_COLOUT4_PA6 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x6)
1014 0 : #define KEYSCAN_COLOUT4_PA7 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x7)
1015 0 : #define KEYSCAN_COLOUT4_PA8 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x8)
1016 0 : #define KEYSCAN_COLOUT4_PA9 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x9)
1017 0 : #define KEYSCAN_COLOUT4_PA10 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xa)
1018 0 : #define KEYSCAN_COLOUT4_PB0 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x0)
1019 0 : #define KEYSCAN_COLOUT4_PB1 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x1)
1020 0 : #define KEYSCAN_COLOUT4_PB2 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x2)
1021 0 : #define KEYSCAN_COLOUT4_PB3 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x3)
1022 0 : #define KEYSCAN_COLOUT4_PB4 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x4)
1023 0 : #define KEYSCAN_COLOUT4_PB5 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x5)
1024 0 : #define KEYSCAN_COLOUT4_PB6 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x6)
1025 0 : #define KEYSCAN_COLOUT4_PC0 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x0)
1026 0 : #define KEYSCAN_COLOUT4_PC1 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x1)
1027 0 : #define KEYSCAN_COLOUT4_PC2 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x2)
1028 0 : #define KEYSCAN_COLOUT4_PC3 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x3)
1029 0 : #define KEYSCAN_COLOUT4_PC4 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x4)
1030 0 : #define KEYSCAN_COLOUT4_PC5 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x5)
1031 0 : #define KEYSCAN_COLOUT4_PC6 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x6)
1032 0 : #define KEYSCAN_COLOUT4_PC7 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x7)
1033 0 : #define KEYSCAN_COLOUT4_PC8 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x8)
1034 0 : #define KEYSCAN_COLOUT4_PC9 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x9)
1035 0 : #define KEYSCAN_COLOUT4_PD0 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x0)
1036 0 : #define KEYSCAN_COLOUT4_PD1 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x1)
1037 0 : #define KEYSCAN_COLOUT4_PD2 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x2)
1038 0 : #define KEYSCAN_COLOUT4_PD3 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x3)
1039 0 : #define KEYSCAN_COLOUT4_PD4 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x4)
1040 0 : #define KEYSCAN_COLOUT4_PD5 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x5)
1041 0 : #define KEYSCAN_COLOUT5_PA0 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x0)
1042 0 : #define KEYSCAN_COLOUT5_PA1 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x1)
1043 0 : #define KEYSCAN_COLOUT5_PA2 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x2)
1044 0 : #define KEYSCAN_COLOUT5_PA3 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x3)
1045 0 : #define KEYSCAN_COLOUT5_PA4 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x4)
1046 0 : #define KEYSCAN_COLOUT5_PA5 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x5)
1047 0 : #define KEYSCAN_COLOUT5_PA6 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x6)
1048 0 : #define KEYSCAN_COLOUT5_PA7 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x7)
1049 0 : #define KEYSCAN_COLOUT5_PA8 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x8)
1050 0 : #define KEYSCAN_COLOUT5_PA9 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x9)
1051 0 : #define KEYSCAN_COLOUT5_PA10 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xa)
1052 0 : #define KEYSCAN_COLOUT5_PB0 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x0)
1053 0 : #define KEYSCAN_COLOUT5_PB1 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x1)
1054 0 : #define KEYSCAN_COLOUT5_PB2 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x2)
1055 0 : #define KEYSCAN_COLOUT5_PB3 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x3)
1056 0 : #define KEYSCAN_COLOUT5_PB4 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x4)
1057 0 : #define KEYSCAN_COLOUT5_PB5 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x5)
1058 0 : #define KEYSCAN_COLOUT5_PB6 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x6)
1059 0 : #define KEYSCAN_COLOUT5_PC0 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x0)
1060 0 : #define KEYSCAN_COLOUT5_PC1 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x1)
1061 0 : #define KEYSCAN_COLOUT5_PC2 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x2)
1062 0 : #define KEYSCAN_COLOUT5_PC3 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x3)
1063 0 : #define KEYSCAN_COLOUT5_PC4 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x4)
1064 0 : #define KEYSCAN_COLOUT5_PC5 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x5)
1065 0 : #define KEYSCAN_COLOUT5_PC6 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x6)
1066 0 : #define KEYSCAN_COLOUT5_PC7 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x7)
1067 0 : #define KEYSCAN_COLOUT5_PC8 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x8)
1068 0 : #define KEYSCAN_COLOUT5_PC9 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x9)
1069 0 : #define KEYSCAN_COLOUT5_PD0 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x0)
1070 0 : #define KEYSCAN_COLOUT5_PD1 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x1)
1071 0 : #define KEYSCAN_COLOUT5_PD2 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x2)
1072 0 : #define KEYSCAN_COLOUT5_PD3 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x3)
1073 0 : #define KEYSCAN_COLOUT5_PD4 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x4)
1074 0 : #define KEYSCAN_COLOUT5_PD5 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x5)
1075 0 : #define KEYSCAN_COLOUT6_PA0 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x0)
1076 0 : #define KEYSCAN_COLOUT6_PA1 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x1)
1077 0 : #define KEYSCAN_COLOUT6_PA2 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x2)
1078 0 : #define KEYSCAN_COLOUT6_PA3 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x3)
1079 0 : #define KEYSCAN_COLOUT6_PA4 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x4)
1080 0 : #define KEYSCAN_COLOUT6_PA5 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x5)
1081 0 : #define KEYSCAN_COLOUT6_PA6 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x6)
1082 0 : #define KEYSCAN_COLOUT6_PA7 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x7)
1083 0 : #define KEYSCAN_COLOUT6_PA8 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x8)
1084 0 : #define KEYSCAN_COLOUT6_PA9 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x9)
1085 0 : #define KEYSCAN_COLOUT6_PA10 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xa)
1086 0 : #define KEYSCAN_COLOUT6_PB0 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x0)
1087 0 : #define KEYSCAN_COLOUT6_PB1 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x1)
1088 0 : #define KEYSCAN_COLOUT6_PB2 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x2)
1089 0 : #define KEYSCAN_COLOUT6_PB3 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x3)
1090 0 : #define KEYSCAN_COLOUT6_PB4 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x4)
1091 0 : #define KEYSCAN_COLOUT6_PB5 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x5)
1092 0 : #define KEYSCAN_COLOUT6_PB6 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x6)
1093 0 : #define KEYSCAN_COLOUT6_PC0 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x0)
1094 0 : #define KEYSCAN_COLOUT6_PC1 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x1)
1095 0 : #define KEYSCAN_COLOUT6_PC2 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x2)
1096 0 : #define KEYSCAN_COLOUT6_PC3 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x3)
1097 0 : #define KEYSCAN_COLOUT6_PC4 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x4)
1098 0 : #define KEYSCAN_COLOUT6_PC5 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x5)
1099 0 : #define KEYSCAN_COLOUT6_PC6 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x6)
1100 0 : #define KEYSCAN_COLOUT6_PC7 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x7)
1101 0 : #define KEYSCAN_COLOUT6_PC8 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x8)
1102 0 : #define KEYSCAN_COLOUT6_PC9 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x9)
1103 0 : #define KEYSCAN_COLOUT6_PD0 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x0)
1104 0 : #define KEYSCAN_COLOUT6_PD1 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x1)
1105 0 : #define KEYSCAN_COLOUT6_PD2 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x2)
1106 0 : #define KEYSCAN_COLOUT6_PD3 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x3)
1107 0 : #define KEYSCAN_COLOUT6_PD4 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x4)
1108 0 : #define KEYSCAN_COLOUT6_PD5 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x5)
1109 0 : #define KEYSCAN_COLOUT7_PA0 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x0)
1110 0 : #define KEYSCAN_COLOUT7_PA1 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x1)
1111 0 : #define KEYSCAN_COLOUT7_PA2 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x2)
1112 0 : #define KEYSCAN_COLOUT7_PA3 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x3)
1113 0 : #define KEYSCAN_COLOUT7_PA4 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x4)
1114 0 : #define KEYSCAN_COLOUT7_PA5 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x5)
1115 0 : #define KEYSCAN_COLOUT7_PA6 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x6)
1116 0 : #define KEYSCAN_COLOUT7_PA7 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x7)
1117 0 : #define KEYSCAN_COLOUT7_PA8 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x8)
1118 0 : #define KEYSCAN_COLOUT7_PA9 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x9)
1119 0 : #define KEYSCAN_COLOUT7_PA10 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xa)
1120 0 : #define KEYSCAN_COLOUT7_PB0 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x0)
1121 0 : #define KEYSCAN_COLOUT7_PB1 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x1)
1122 0 : #define KEYSCAN_COLOUT7_PB2 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x2)
1123 0 : #define KEYSCAN_COLOUT7_PB3 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x3)
1124 0 : #define KEYSCAN_COLOUT7_PB4 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x4)
1125 0 : #define KEYSCAN_COLOUT7_PB5 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x5)
1126 0 : #define KEYSCAN_COLOUT7_PB6 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x6)
1127 0 : #define KEYSCAN_COLOUT7_PC0 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x0)
1128 0 : #define KEYSCAN_COLOUT7_PC1 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x1)
1129 0 : #define KEYSCAN_COLOUT7_PC2 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x2)
1130 0 : #define KEYSCAN_COLOUT7_PC3 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x3)
1131 0 : #define KEYSCAN_COLOUT7_PC4 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x4)
1132 0 : #define KEYSCAN_COLOUT7_PC5 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x5)
1133 0 : #define KEYSCAN_COLOUT7_PC6 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x6)
1134 0 : #define KEYSCAN_COLOUT7_PC7 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x7)
1135 0 : #define KEYSCAN_COLOUT7_PC8 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x8)
1136 0 : #define KEYSCAN_COLOUT7_PC9 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x9)
1137 0 : #define KEYSCAN_COLOUT7_PD0 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x0)
1138 0 : #define KEYSCAN_COLOUT7_PD1 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x1)
1139 0 : #define KEYSCAN_COLOUT7_PD2 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x2)
1140 0 : #define KEYSCAN_COLOUT7_PD3 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x3)
1141 0 : #define KEYSCAN_COLOUT7_PD4 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x4)
1142 0 : #define KEYSCAN_COLOUT7_PD5 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x5)
1143 0 : #define KEYSCAN_ROWSENSE0_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x0)
1144 0 : #define KEYSCAN_ROWSENSE0_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x1)
1145 0 : #define KEYSCAN_ROWSENSE0_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x2)
1146 0 : #define KEYSCAN_ROWSENSE0_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x3)
1147 0 : #define KEYSCAN_ROWSENSE0_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x4)
1148 0 : #define KEYSCAN_ROWSENSE0_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x5)
1149 0 : #define KEYSCAN_ROWSENSE0_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x6)
1150 0 : #define KEYSCAN_ROWSENSE0_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x7)
1151 0 : #define KEYSCAN_ROWSENSE0_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x8)
1152 0 : #define KEYSCAN_ROWSENSE0_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x9)
1153 0 : #define KEYSCAN_ROWSENSE0_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xa)
1154 0 : #define KEYSCAN_ROWSENSE0_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x0)
1155 0 : #define KEYSCAN_ROWSENSE0_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x1)
1156 0 : #define KEYSCAN_ROWSENSE0_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x2)
1157 0 : #define KEYSCAN_ROWSENSE0_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x3)
1158 0 : #define KEYSCAN_ROWSENSE0_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x4)
1159 0 : #define KEYSCAN_ROWSENSE0_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x5)
1160 0 : #define KEYSCAN_ROWSENSE0_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x6)
1161 0 : #define KEYSCAN_ROWSENSE1_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x0)
1162 0 : #define KEYSCAN_ROWSENSE1_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x1)
1163 0 : #define KEYSCAN_ROWSENSE1_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x2)
1164 0 : #define KEYSCAN_ROWSENSE1_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x3)
1165 0 : #define KEYSCAN_ROWSENSE1_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x4)
1166 0 : #define KEYSCAN_ROWSENSE1_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x5)
1167 0 : #define KEYSCAN_ROWSENSE1_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x6)
1168 0 : #define KEYSCAN_ROWSENSE1_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x7)
1169 0 : #define KEYSCAN_ROWSENSE1_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x8)
1170 0 : #define KEYSCAN_ROWSENSE1_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x9)
1171 0 : #define KEYSCAN_ROWSENSE1_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xa)
1172 0 : #define KEYSCAN_ROWSENSE1_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x0)
1173 0 : #define KEYSCAN_ROWSENSE1_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x1)
1174 0 : #define KEYSCAN_ROWSENSE1_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x2)
1175 0 : #define KEYSCAN_ROWSENSE1_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x3)
1176 0 : #define KEYSCAN_ROWSENSE1_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x4)
1177 0 : #define KEYSCAN_ROWSENSE1_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x5)
1178 0 : #define KEYSCAN_ROWSENSE1_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x6)
1179 0 : #define KEYSCAN_ROWSENSE2_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x0)
1180 0 : #define KEYSCAN_ROWSENSE2_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x1)
1181 0 : #define KEYSCAN_ROWSENSE2_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x2)
1182 0 : #define KEYSCAN_ROWSENSE2_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x3)
1183 0 : #define KEYSCAN_ROWSENSE2_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x4)
1184 0 : #define KEYSCAN_ROWSENSE2_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x5)
1185 0 : #define KEYSCAN_ROWSENSE2_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x6)
1186 0 : #define KEYSCAN_ROWSENSE2_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x7)
1187 0 : #define KEYSCAN_ROWSENSE2_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x8)
1188 0 : #define KEYSCAN_ROWSENSE2_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x9)
1189 0 : #define KEYSCAN_ROWSENSE2_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xa)
1190 0 : #define KEYSCAN_ROWSENSE2_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x0)
1191 0 : #define KEYSCAN_ROWSENSE2_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x1)
1192 0 : #define KEYSCAN_ROWSENSE2_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x2)
1193 0 : #define KEYSCAN_ROWSENSE2_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x3)
1194 0 : #define KEYSCAN_ROWSENSE2_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x4)
1195 0 : #define KEYSCAN_ROWSENSE2_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x5)
1196 0 : #define KEYSCAN_ROWSENSE2_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x6)
1197 0 : #define KEYSCAN_ROWSENSE3_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x0)
1198 0 : #define KEYSCAN_ROWSENSE3_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x1)
1199 0 : #define KEYSCAN_ROWSENSE3_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x2)
1200 0 : #define KEYSCAN_ROWSENSE3_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x3)
1201 0 : #define KEYSCAN_ROWSENSE3_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x4)
1202 0 : #define KEYSCAN_ROWSENSE3_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x5)
1203 0 : #define KEYSCAN_ROWSENSE3_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x6)
1204 0 : #define KEYSCAN_ROWSENSE3_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x7)
1205 0 : #define KEYSCAN_ROWSENSE3_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x8)
1206 0 : #define KEYSCAN_ROWSENSE3_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x9)
1207 0 : #define KEYSCAN_ROWSENSE3_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xa)
1208 0 : #define KEYSCAN_ROWSENSE3_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x0)
1209 0 : #define KEYSCAN_ROWSENSE3_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x1)
1210 0 : #define KEYSCAN_ROWSENSE3_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x2)
1211 0 : #define KEYSCAN_ROWSENSE3_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x3)
1212 0 : #define KEYSCAN_ROWSENSE3_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x4)
1213 0 : #define KEYSCAN_ROWSENSE3_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x5)
1214 0 : #define KEYSCAN_ROWSENSE3_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x6)
1215 0 : #define KEYSCAN_ROWSENSE4_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x0)
1216 0 : #define KEYSCAN_ROWSENSE4_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x1)
1217 0 : #define KEYSCAN_ROWSENSE4_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x2)
1218 0 : #define KEYSCAN_ROWSENSE4_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x3)
1219 0 : #define KEYSCAN_ROWSENSE4_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x4)
1220 0 : #define KEYSCAN_ROWSENSE4_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x5)
1221 0 : #define KEYSCAN_ROWSENSE4_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x6)
1222 0 : #define KEYSCAN_ROWSENSE4_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x7)
1223 0 : #define KEYSCAN_ROWSENSE4_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x8)
1224 0 : #define KEYSCAN_ROWSENSE4_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x9)
1225 0 : #define KEYSCAN_ROWSENSE4_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xa)
1226 0 : #define KEYSCAN_ROWSENSE4_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x0)
1227 0 : #define KEYSCAN_ROWSENSE4_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x1)
1228 0 : #define KEYSCAN_ROWSENSE4_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x2)
1229 0 : #define KEYSCAN_ROWSENSE4_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x3)
1230 0 : #define KEYSCAN_ROWSENSE4_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x4)
1231 0 : #define KEYSCAN_ROWSENSE4_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x5)
1232 0 : #define KEYSCAN_ROWSENSE4_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x6)
1233 0 : #define KEYSCAN_ROWSENSE5_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x0)
1234 0 : #define KEYSCAN_ROWSENSE5_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x1)
1235 0 : #define KEYSCAN_ROWSENSE5_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x2)
1236 0 : #define KEYSCAN_ROWSENSE5_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x3)
1237 0 : #define KEYSCAN_ROWSENSE5_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x4)
1238 0 : #define KEYSCAN_ROWSENSE5_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x5)
1239 0 : #define KEYSCAN_ROWSENSE5_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x6)
1240 0 : #define KEYSCAN_ROWSENSE5_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x7)
1241 0 : #define KEYSCAN_ROWSENSE5_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x8)
1242 0 : #define KEYSCAN_ROWSENSE5_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x9)
1243 0 : #define KEYSCAN_ROWSENSE5_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xa)
1244 0 : #define KEYSCAN_ROWSENSE5_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x0)
1245 0 : #define KEYSCAN_ROWSENSE5_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x1)
1246 0 : #define KEYSCAN_ROWSENSE5_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x2)
1247 0 : #define KEYSCAN_ROWSENSE5_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x3)
1248 0 : #define KEYSCAN_ROWSENSE5_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x4)
1249 0 : #define KEYSCAN_ROWSENSE5_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x5)
1250 0 : #define KEYSCAN_ROWSENSE5_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x6)
1251 :
1252 0 : #define LESENSE_CH0OUT_PA0 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x0)
1253 0 : #define LESENSE_CH0OUT_PA1 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x1)
1254 0 : #define LESENSE_CH0OUT_PA2 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x2)
1255 0 : #define LESENSE_CH0OUT_PA3 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x3)
1256 0 : #define LESENSE_CH0OUT_PA4 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x4)
1257 0 : #define LESENSE_CH0OUT_PA5 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x5)
1258 0 : #define LESENSE_CH0OUT_PA6 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x6)
1259 0 : #define LESENSE_CH0OUT_PA7 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x7)
1260 0 : #define LESENSE_CH0OUT_PA8 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x8)
1261 0 : #define LESENSE_CH0OUT_PA9 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x9)
1262 0 : #define LESENSE_CH0OUT_PA10 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xa)
1263 0 : #define LESENSE_CH0OUT_PB0 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x0)
1264 0 : #define LESENSE_CH0OUT_PB1 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x1)
1265 0 : #define LESENSE_CH0OUT_PB2 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x2)
1266 0 : #define LESENSE_CH0OUT_PB3 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x3)
1267 0 : #define LESENSE_CH0OUT_PB4 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x4)
1268 0 : #define LESENSE_CH0OUT_PB5 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x5)
1269 0 : #define LESENSE_CH0OUT_PB6 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x6)
1270 0 : #define LESENSE_CH1OUT_PA0 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x0)
1271 0 : #define LESENSE_CH1OUT_PA1 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x1)
1272 0 : #define LESENSE_CH1OUT_PA2 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x2)
1273 0 : #define LESENSE_CH1OUT_PA3 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x3)
1274 0 : #define LESENSE_CH1OUT_PA4 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x4)
1275 0 : #define LESENSE_CH1OUT_PA5 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x5)
1276 0 : #define LESENSE_CH1OUT_PA6 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x6)
1277 0 : #define LESENSE_CH1OUT_PA7 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x7)
1278 0 : #define LESENSE_CH1OUT_PA8 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x8)
1279 0 : #define LESENSE_CH1OUT_PA9 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x9)
1280 0 : #define LESENSE_CH1OUT_PA10 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xa)
1281 0 : #define LESENSE_CH1OUT_PB0 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x0)
1282 0 : #define LESENSE_CH1OUT_PB1 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x1)
1283 0 : #define LESENSE_CH1OUT_PB2 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x2)
1284 0 : #define LESENSE_CH1OUT_PB3 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x3)
1285 0 : #define LESENSE_CH1OUT_PB4 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x4)
1286 0 : #define LESENSE_CH1OUT_PB5 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x5)
1287 0 : #define LESENSE_CH1OUT_PB6 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x6)
1288 0 : #define LESENSE_CH2OUT_PA0 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x0)
1289 0 : #define LESENSE_CH2OUT_PA1 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x1)
1290 0 : #define LESENSE_CH2OUT_PA2 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x2)
1291 0 : #define LESENSE_CH2OUT_PA3 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x3)
1292 0 : #define LESENSE_CH2OUT_PA4 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x4)
1293 0 : #define LESENSE_CH2OUT_PA5 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x5)
1294 0 : #define LESENSE_CH2OUT_PA6 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x6)
1295 0 : #define LESENSE_CH2OUT_PA7 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x7)
1296 0 : #define LESENSE_CH2OUT_PA8 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x8)
1297 0 : #define LESENSE_CH2OUT_PA9 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x9)
1298 0 : #define LESENSE_CH2OUT_PA10 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xa)
1299 0 : #define LESENSE_CH2OUT_PB0 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x0)
1300 0 : #define LESENSE_CH2OUT_PB1 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x1)
1301 0 : #define LESENSE_CH2OUT_PB2 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x2)
1302 0 : #define LESENSE_CH2OUT_PB3 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x3)
1303 0 : #define LESENSE_CH2OUT_PB4 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x4)
1304 0 : #define LESENSE_CH2OUT_PB5 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x5)
1305 0 : #define LESENSE_CH2OUT_PB6 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x6)
1306 0 : #define LESENSE_CH3OUT_PA0 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x0)
1307 0 : #define LESENSE_CH3OUT_PA1 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x1)
1308 0 : #define LESENSE_CH3OUT_PA2 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x2)
1309 0 : #define LESENSE_CH3OUT_PA3 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x3)
1310 0 : #define LESENSE_CH3OUT_PA4 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x4)
1311 0 : #define LESENSE_CH3OUT_PA5 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x5)
1312 0 : #define LESENSE_CH3OUT_PA6 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x6)
1313 0 : #define LESENSE_CH3OUT_PA7 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x7)
1314 0 : #define LESENSE_CH3OUT_PA8 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x8)
1315 0 : #define LESENSE_CH3OUT_PA9 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x9)
1316 0 : #define LESENSE_CH3OUT_PA10 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xa)
1317 0 : #define LESENSE_CH3OUT_PB0 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x0)
1318 0 : #define LESENSE_CH3OUT_PB1 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x1)
1319 0 : #define LESENSE_CH3OUT_PB2 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x2)
1320 0 : #define LESENSE_CH3OUT_PB3 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x3)
1321 0 : #define LESENSE_CH3OUT_PB4 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x4)
1322 0 : #define LESENSE_CH3OUT_PB5 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x5)
1323 0 : #define LESENSE_CH3OUT_PB6 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x6)
1324 0 : #define LESENSE_CH4OUT_PA0 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x0)
1325 0 : #define LESENSE_CH4OUT_PA1 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x1)
1326 0 : #define LESENSE_CH4OUT_PA2 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x2)
1327 0 : #define LESENSE_CH4OUT_PA3 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x3)
1328 0 : #define LESENSE_CH4OUT_PA4 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x4)
1329 0 : #define LESENSE_CH4OUT_PA5 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x5)
1330 0 : #define LESENSE_CH4OUT_PA6 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x6)
1331 0 : #define LESENSE_CH4OUT_PA7 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x7)
1332 0 : #define LESENSE_CH4OUT_PA8 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x8)
1333 0 : #define LESENSE_CH4OUT_PA9 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x9)
1334 0 : #define LESENSE_CH4OUT_PA10 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xa)
1335 0 : #define LESENSE_CH4OUT_PB0 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x0)
1336 0 : #define LESENSE_CH4OUT_PB1 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x1)
1337 0 : #define LESENSE_CH4OUT_PB2 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x2)
1338 0 : #define LESENSE_CH4OUT_PB3 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x3)
1339 0 : #define LESENSE_CH4OUT_PB4 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x4)
1340 0 : #define LESENSE_CH4OUT_PB5 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x5)
1341 0 : #define LESENSE_CH4OUT_PB6 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x6)
1342 0 : #define LESENSE_CH5OUT_PA0 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x0)
1343 0 : #define LESENSE_CH5OUT_PA1 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x1)
1344 0 : #define LESENSE_CH5OUT_PA2 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x2)
1345 0 : #define LESENSE_CH5OUT_PA3 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x3)
1346 0 : #define LESENSE_CH5OUT_PA4 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x4)
1347 0 : #define LESENSE_CH5OUT_PA5 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x5)
1348 0 : #define LESENSE_CH5OUT_PA6 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x6)
1349 0 : #define LESENSE_CH5OUT_PA7 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x7)
1350 0 : #define LESENSE_CH5OUT_PA8 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x8)
1351 0 : #define LESENSE_CH5OUT_PA9 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x9)
1352 0 : #define LESENSE_CH5OUT_PA10 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xa)
1353 0 : #define LESENSE_CH5OUT_PB0 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x0)
1354 0 : #define LESENSE_CH5OUT_PB1 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x1)
1355 0 : #define LESENSE_CH5OUT_PB2 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x2)
1356 0 : #define LESENSE_CH5OUT_PB3 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x3)
1357 0 : #define LESENSE_CH5OUT_PB4 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x4)
1358 0 : #define LESENSE_CH5OUT_PB5 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x5)
1359 0 : #define LESENSE_CH5OUT_PB6 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x6)
1360 0 : #define LESENSE_CH6OUT_PA0 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x0)
1361 0 : #define LESENSE_CH6OUT_PA1 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x1)
1362 0 : #define LESENSE_CH6OUT_PA2 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x2)
1363 0 : #define LESENSE_CH6OUT_PA3 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x3)
1364 0 : #define LESENSE_CH6OUT_PA4 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x4)
1365 0 : #define LESENSE_CH6OUT_PA5 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x5)
1366 0 : #define LESENSE_CH6OUT_PA6 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x6)
1367 0 : #define LESENSE_CH6OUT_PA7 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x7)
1368 0 : #define LESENSE_CH6OUT_PA8 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x8)
1369 0 : #define LESENSE_CH6OUT_PA9 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x9)
1370 0 : #define LESENSE_CH6OUT_PA10 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xa)
1371 0 : #define LESENSE_CH6OUT_PB0 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x0)
1372 0 : #define LESENSE_CH6OUT_PB1 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x1)
1373 0 : #define LESENSE_CH6OUT_PB2 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x2)
1374 0 : #define LESENSE_CH6OUT_PB3 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x3)
1375 0 : #define LESENSE_CH6OUT_PB4 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x4)
1376 0 : #define LESENSE_CH6OUT_PB5 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x5)
1377 0 : #define LESENSE_CH6OUT_PB6 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x6)
1378 0 : #define LESENSE_CH7OUT_PA0 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x0)
1379 0 : #define LESENSE_CH7OUT_PA1 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x1)
1380 0 : #define LESENSE_CH7OUT_PA2 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x2)
1381 0 : #define LESENSE_CH7OUT_PA3 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x3)
1382 0 : #define LESENSE_CH7OUT_PA4 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x4)
1383 0 : #define LESENSE_CH7OUT_PA5 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x5)
1384 0 : #define LESENSE_CH7OUT_PA6 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x6)
1385 0 : #define LESENSE_CH7OUT_PA7 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x7)
1386 0 : #define LESENSE_CH7OUT_PA8 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x8)
1387 0 : #define LESENSE_CH7OUT_PA9 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x9)
1388 0 : #define LESENSE_CH7OUT_PA10 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xa)
1389 0 : #define LESENSE_CH7OUT_PB0 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x0)
1390 0 : #define LESENSE_CH7OUT_PB1 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x1)
1391 0 : #define LESENSE_CH7OUT_PB2 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x2)
1392 0 : #define LESENSE_CH7OUT_PB3 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x3)
1393 0 : #define LESENSE_CH7OUT_PB4 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x4)
1394 0 : #define LESENSE_CH7OUT_PB5 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x5)
1395 0 : #define LESENSE_CH7OUT_PB6 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x6)
1396 0 : #define LESENSE_CH8OUT_PA0 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x0)
1397 0 : #define LESENSE_CH8OUT_PA1 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x1)
1398 0 : #define LESENSE_CH8OUT_PA2 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x2)
1399 0 : #define LESENSE_CH8OUT_PA3 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x3)
1400 0 : #define LESENSE_CH8OUT_PA4 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x4)
1401 0 : #define LESENSE_CH8OUT_PA5 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x5)
1402 0 : #define LESENSE_CH8OUT_PA6 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x6)
1403 0 : #define LESENSE_CH8OUT_PA7 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x7)
1404 0 : #define LESENSE_CH8OUT_PA8 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x8)
1405 0 : #define LESENSE_CH8OUT_PA9 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x9)
1406 0 : #define LESENSE_CH8OUT_PA10 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xa)
1407 0 : #define LESENSE_CH8OUT_PB0 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x0)
1408 0 : #define LESENSE_CH8OUT_PB1 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x1)
1409 0 : #define LESENSE_CH8OUT_PB2 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x2)
1410 0 : #define LESENSE_CH8OUT_PB3 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x3)
1411 0 : #define LESENSE_CH8OUT_PB4 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x4)
1412 0 : #define LESENSE_CH8OUT_PB5 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x5)
1413 0 : #define LESENSE_CH8OUT_PB6 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x6)
1414 0 : #define LESENSE_CH9OUT_PA0 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x0)
1415 0 : #define LESENSE_CH9OUT_PA1 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x1)
1416 0 : #define LESENSE_CH9OUT_PA2 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x2)
1417 0 : #define LESENSE_CH9OUT_PA3 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x3)
1418 0 : #define LESENSE_CH9OUT_PA4 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x4)
1419 0 : #define LESENSE_CH9OUT_PA5 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x5)
1420 0 : #define LESENSE_CH9OUT_PA6 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x6)
1421 0 : #define LESENSE_CH9OUT_PA7 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x7)
1422 0 : #define LESENSE_CH9OUT_PA8 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x8)
1423 0 : #define LESENSE_CH9OUT_PA9 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x9)
1424 0 : #define LESENSE_CH9OUT_PA10 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xa)
1425 0 : #define LESENSE_CH9OUT_PB0 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x0)
1426 0 : #define LESENSE_CH9OUT_PB1 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x1)
1427 0 : #define LESENSE_CH9OUT_PB2 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x2)
1428 0 : #define LESENSE_CH9OUT_PB3 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x3)
1429 0 : #define LESENSE_CH9OUT_PB4 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x4)
1430 0 : #define LESENSE_CH9OUT_PB5 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x5)
1431 0 : #define LESENSE_CH9OUT_PB6 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x6)
1432 0 : #define LESENSE_CH10OUT_PA0 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x0)
1433 0 : #define LESENSE_CH10OUT_PA1 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x1)
1434 0 : #define LESENSE_CH10OUT_PA2 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x2)
1435 0 : #define LESENSE_CH10OUT_PA3 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x3)
1436 0 : #define LESENSE_CH10OUT_PA4 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x4)
1437 0 : #define LESENSE_CH10OUT_PA5 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x5)
1438 0 : #define LESENSE_CH10OUT_PA6 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x6)
1439 0 : #define LESENSE_CH10OUT_PA7 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x7)
1440 0 : #define LESENSE_CH10OUT_PA8 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x8)
1441 0 : #define LESENSE_CH10OUT_PA9 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x9)
1442 0 : #define LESENSE_CH10OUT_PA10 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xa)
1443 0 : #define LESENSE_CH10OUT_PB0 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x0)
1444 0 : #define LESENSE_CH10OUT_PB1 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x1)
1445 0 : #define LESENSE_CH10OUT_PB2 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x2)
1446 0 : #define LESENSE_CH10OUT_PB3 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x3)
1447 0 : #define LESENSE_CH10OUT_PB4 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x4)
1448 0 : #define LESENSE_CH10OUT_PB5 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x5)
1449 0 : #define LESENSE_CH10OUT_PB6 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x6)
1450 0 : #define LESENSE_CH11OUT_PA0 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x0)
1451 0 : #define LESENSE_CH11OUT_PA1 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x1)
1452 0 : #define LESENSE_CH11OUT_PA2 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x2)
1453 0 : #define LESENSE_CH11OUT_PA3 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x3)
1454 0 : #define LESENSE_CH11OUT_PA4 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x4)
1455 0 : #define LESENSE_CH11OUT_PA5 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x5)
1456 0 : #define LESENSE_CH11OUT_PA6 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x6)
1457 0 : #define LESENSE_CH11OUT_PA7 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x7)
1458 0 : #define LESENSE_CH11OUT_PA8 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x8)
1459 0 : #define LESENSE_CH11OUT_PA9 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x9)
1460 0 : #define LESENSE_CH11OUT_PA10 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xa)
1461 0 : #define LESENSE_CH11OUT_PB0 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x0)
1462 0 : #define LESENSE_CH11OUT_PB1 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x1)
1463 0 : #define LESENSE_CH11OUT_PB2 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x2)
1464 0 : #define LESENSE_CH11OUT_PB3 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x3)
1465 0 : #define LESENSE_CH11OUT_PB4 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x4)
1466 0 : #define LESENSE_CH11OUT_PB5 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x5)
1467 0 : #define LESENSE_CH11OUT_PB6 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x6)
1468 0 : #define LESENSE_CH12OUT_PA0 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x0)
1469 0 : #define LESENSE_CH12OUT_PA1 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x1)
1470 0 : #define LESENSE_CH12OUT_PA2 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x2)
1471 0 : #define LESENSE_CH12OUT_PA3 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x3)
1472 0 : #define LESENSE_CH12OUT_PA4 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x4)
1473 0 : #define LESENSE_CH12OUT_PA5 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x5)
1474 0 : #define LESENSE_CH12OUT_PA6 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x6)
1475 0 : #define LESENSE_CH12OUT_PA7 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x7)
1476 0 : #define LESENSE_CH12OUT_PA8 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x8)
1477 0 : #define LESENSE_CH12OUT_PA9 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x9)
1478 0 : #define LESENSE_CH12OUT_PA10 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xa)
1479 0 : #define LESENSE_CH12OUT_PB0 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x0)
1480 0 : #define LESENSE_CH12OUT_PB1 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x1)
1481 0 : #define LESENSE_CH12OUT_PB2 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x2)
1482 0 : #define LESENSE_CH12OUT_PB3 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x3)
1483 0 : #define LESENSE_CH12OUT_PB4 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x4)
1484 0 : #define LESENSE_CH12OUT_PB5 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x5)
1485 0 : #define LESENSE_CH12OUT_PB6 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x6)
1486 0 : #define LESENSE_CH13OUT_PA0 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x0)
1487 0 : #define LESENSE_CH13OUT_PA1 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x1)
1488 0 : #define LESENSE_CH13OUT_PA2 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x2)
1489 0 : #define LESENSE_CH13OUT_PA3 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x3)
1490 0 : #define LESENSE_CH13OUT_PA4 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x4)
1491 0 : #define LESENSE_CH13OUT_PA5 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x5)
1492 0 : #define LESENSE_CH13OUT_PA6 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x6)
1493 0 : #define LESENSE_CH13OUT_PA7 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x7)
1494 0 : #define LESENSE_CH13OUT_PA8 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x8)
1495 0 : #define LESENSE_CH13OUT_PA9 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x9)
1496 0 : #define LESENSE_CH13OUT_PA10 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xa)
1497 0 : #define LESENSE_CH13OUT_PB0 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x0)
1498 0 : #define LESENSE_CH13OUT_PB1 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x1)
1499 0 : #define LESENSE_CH13OUT_PB2 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x2)
1500 0 : #define LESENSE_CH13OUT_PB3 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x3)
1501 0 : #define LESENSE_CH13OUT_PB4 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x4)
1502 0 : #define LESENSE_CH13OUT_PB5 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x5)
1503 0 : #define LESENSE_CH13OUT_PB6 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x6)
1504 0 : #define LESENSE_CH14OUT_PA0 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x0)
1505 0 : #define LESENSE_CH14OUT_PA1 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x1)
1506 0 : #define LESENSE_CH14OUT_PA2 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x2)
1507 0 : #define LESENSE_CH14OUT_PA3 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x3)
1508 0 : #define LESENSE_CH14OUT_PA4 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x4)
1509 0 : #define LESENSE_CH14OUT_PA5 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x5)
1510 0 : #define LESENSE_CH14OUT_PA6 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x6)
1511 0 : #define LESENSE_CH14OUT_PA7 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x7)
1512 0 : #define LESENSE_CH14OUT_PA8 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x8)
1513 0 : #define LESENSE_CH14OUT_PA9 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x9)
1514 0 : #define LESENSE_CH14OUT_PA10 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xa)
1515 0 : #define LESENSE_CH14OUT_PB0 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x0)
1516 0 : #define LESENSE_CH14OUT_PB1 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x1)
1517 0 : #define LESENSE_CH14OUT_PB2 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x2)
1518 0 : #define LESENSE_CH14OUT_PB3 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x3)
1519 0 : #define LESENSE_CH14OUT_PB4 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x4)
1520 0 : #define LESENSE_CH14OUT_PB5 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x5)
1521 0 : #define LESENSE_CH14OUT_PB6 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x6)
1522 0 : #define LESENSE_CH15OUT_PA0 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x0)
1523 0 : #define LESENSE_CH15OUT_PA1 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x1)
1524 0 : #define LESENSE_CH15OUT_PA2 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x2)
1525 0 : #define LESENSE_CH15OUT_PA3 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x3)
1526 0 : #define LESENSE_CH15OUT_PA4 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x4)
1527 0 : #define LESENSE_CH15OUT_PA5 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x5)
1528 0 : #define LESENSE_CH15OUT_PA6 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x6)
1529 0 : #define LESENSE_CH15OUT_PA7 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x7)
1530 0 : #define LESENSE_CH15OUT_PA8 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x8)
1531 0 : #define LESENSE_CH15OUT_PA9 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x9)
1532 0 : #define LESENSE_CH15OUT_PA10 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xa)
1533 0 : #define LESENSE_CH15OUT_PB0 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x0)
1534 0 : #define LESENSE_CH15OUT_PB1 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x1)
1535 0 : #define LESENSE_CH15OUT_PB2 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x2)
1536 0 : #define LESENSE_CH15OUT_PB3 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x3)
1537 0 : #define LESENSE_CH15OUT_PB4 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x4)
1538 0 : #define LESENSE_CH15OUT_PB5 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x5)
1539 0 : #define LESENSE_CH15OUT_PB6 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x6)
1540 :
1541 0 : #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
1542 0 : #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
1543 0 : #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
1544 0 : #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
1545 0 : #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
1546 0 : #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
1547 0 : #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
1548 0 : #define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
1549 0 : #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
1550 0 : #define LETIMER0_OUT0_PA9 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x9)
1551 0 : #define LETIMER0_OUT0_PA10 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xa)
1552 0 : #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
1553 0 : #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
1554 0 : #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
1555 0 : #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
1556 0 : #define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
1557 0 : #define LETIMER0_OUT0_PB5 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x5)
1558 0 : #define LETIMER0_OUT0_PB6 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x6)
1559 0 : #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
1560 0 : #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
1561 0 : #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
1562 0 : #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
1563 0 : #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
1564 0 : #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
1565 0 : #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
1566 0 : #define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
1567 0 : #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
1568 0 : #define LETIMER0_OUT1_PA9 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x9)
1569 0 : #define LETIMER0_OUT1_PA10 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xa)
1570 0 : #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
1571 0 : #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
1572 0 : #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
1573 0 : #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
1574 0 : #define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
1575 0 : #define LETIMER0_OUT1_PB5 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x5)
1576 0 : #define LETIMER0_OUT1_PB6 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x6)
1577 :
1578 0 : #define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
1579 0 : #define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
1580 0 : #define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
1581 0 : #define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
1582 0 : #define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
1583 0 : #define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
1584 0 : #define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
1585 0 : #define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
1586 0 : #define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
1587 0 : #define MODEM_ANT0_PA9 SILABS_DBUS_MODEM_ANT0(0x0, 0x9)
1588 0 : #define MODEM_ANT0_PA10 SILABS_DBUS_MODEM_ANT0(0x0, 0xa)
1589 0 : #define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
1590 0 : #define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
1591 0 : #define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
1592 0 : #define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
1593 0 : #define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
1594 0 : #define MODEM_ANT0_PB5 SILABS_DBUS_MODEM_ANT0(0x1, 0x5)
1595 0 : #define MODEM_ANT0_PB6 SILABS_DBUS_MODEM_ANT0(0x1, 0x6)
1596 0 : #define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
1597 0 : #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
1598 0 : #define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
1599 0 : #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
1600 0 : #define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
1601 0 : #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
1602 0 : #define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
1603 0 : #define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
1604 0 : #define MODEM_ANT0_PC8 SILABS_DBUS_MODEM_ANT0(0x2, 0x8)
1605 0 : #define MODEM_ANT0_PC9 SILABS_DBUS_MODEM_ANT0(0x2, 0x9)
1606 0 : #define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
1607 0 : #define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
1608 0 : #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
1609 0 : #define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
1610 0 : #define MODEM_ANT0_PD4 SILABS_DBUS_MODEM_ANT0(0x3, 0x4)
1611 0 : #define MODEM_ANT0_PD5 SILABS_DBUS_MODEM_ANT0(0x3, 0x5)
1612 0 : #define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
1613 0 : #define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
1614 0 : #define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
1615 0 : #define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
1616 0 : #define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
1617 0 : #define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
1618 0 : #define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
1619 0 : #define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
1620 0 : #define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
1621 0 : #define MODEM_ANT1_PA9 SILABS_DBUS_MODEM_ANT1(0x0, 0x9)
1622 0 : #define MODEM_ANT1_PA10 SILABS_DBUS_MODEM_ANT1(0x0, 0xa)
1623 0 : #define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
1624 0 : #define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
1625 0 : #define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
1626 0 : #define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
1627 0 : #define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
1628 0 : #define MODEM_ANT1_PB5 SILABS_DBUS_MODEM_ANT1(0x1, 0x5)
1629 0 : #define MODEM_ANT1_PB6 SILABS_DBUS_MODEM_ANT1(0x1, 0x6)
1630 0 : #define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
1631 0 : #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
1632 0 : #define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
1633 0 : #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
1634 0 : #define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
1635 0 : #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
1636 0 : #define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
1637 0 : #define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
1638 0 : #define MODEM_ANT1_PC8 SILABS_DBUS_MODEM_ANT1(0x2, 0x8)
1639 0 : #define MODEM_ANT1_PC9 SILABS_DBUS_MODEM_ANT1(0x2, 0x9)
1640 0 : #define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
1641 0 : #define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
1642 0 : #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
1643 0 : #define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
1644 0 : #define MODEM_ANT1_PD4 SILABS_DBUS_MODEM_ANT1(0x3, 0x4)
1645 0 : #define MODEM_ANT1_PD5 SILABS_DBUS_MODEM_ANT1(0x3, 0x5)
1646 0 : #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
1647 0 : #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
1648 0 : #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
1649 0 : #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
1650 0 : #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
1651 0 : #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
1652 0 : #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
1653 0 : #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
1654 0 : #define MODEM_ANTROLLOVER_PC8 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x8)
1655 0 : #define MODEM_ANTROLLOVER_PC9 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x9)
1656 0 : #define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
1657 0 : #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
1658 0 : #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
1659 0 : #define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
1660 0 : #define MODEM_ANTROLLOVER_PD4 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x4)
1661 0 : #define MODEM_ANTROLLOVER_PD5 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x5)
1662 0 : #define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
1663 0 : #define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
1664 0 : #define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
1665 0 : #define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
1666 0 : #define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
1667 0 : #define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
1668 0 : #define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
1669 0 : #define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
1670 0 : #define MODEM_ANTRR0_PC8 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x8)
1671 0 : #define MODEM_ANTRR0_PC9 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x9)
1672 0 : #define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
1673 0 : #define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
1674 0 : #define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
1675 0 : #define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
1676 0 : #define MODEM_ANTRR0_PD4 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x4)
1677 0 : #define MODEM_ANTRR0_PD5 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x5)
1678 0 : #define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
1679 0 : #define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
1680 0 : #define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
1681 0 : #define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
1682 0 : #define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
1683 0 : #define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
1684 0 : #define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
1685 0 : #define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
1686 0 : #define MODEM_ANTRR1_PC8 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x8)
1687 0 : #define MODEM_ANTRR1_PC9 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x9)
1688 0 : #define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
1689 0 : #define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
1690 0 : #define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
1691 0 : #define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
1692 0 : #define MODEM_ANTRR1_PD4 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x4)
1693 0 : #define MODEM_ANTRR1_PD5 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x5)
1694 0 : #define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
1695 0 : #define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
1696 0 : #define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
1697 0 : #define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
1698 0 : #define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
1699 0 : #define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
1700 0 : #define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
1701 0 : #define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
1702 0 : #define MODEM_ANTRR2_PC8 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x8)
1703 0 : #define MODEM_ANTRR2_PC9 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x9)
1704 0 : #define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
1705 0 : #define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
1706 0 : #define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
1707 0 : #define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
1708 0 : #define MODEM_ANTRR2_PD4 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x4)
1709 0 : #define MODEM_ANTRR2_PD5 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x5)
1710 0 : #define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
1711 0 : #define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
1712 0 : #define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
1713 0 : #define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
1714 0 : #define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
1715 0 : #define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
1716 0 : #define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
1717 0 : #define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
1718 0 : #define MODEM_ANTRR3_PC8 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x8)
1719 0 : #define MODEM_ANTRR3_PC9 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x9)
1720 0 : #define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
1721 0 : #define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
1722 0 : #define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
1723 0 : #define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
1724 0 : #define MODEM_ANTRR3_PD4 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x4)
1725 0 : #define MODEM_ANTRR3_PD5 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x5)
1726 0 : #define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
1727 0 : #define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
1728 0 : #define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
1729 0 : #define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
1730 0 : #define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
1731 0 : #define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
1732 0 : #define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
1733 0 : #define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
1734 0 : #define MODEM_ANTRR4_PC8 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x8)
1735 0 : #define MODEM_ANTRR4_PC9 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x9)
1736 0 : #define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
1737 0 : #define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
1738 0 : #define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
1739 0 : #define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
1740 0 : #define MODEM_ANTRR4_PD4 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x4)
1741 0 : #define MODEM_ANTRR4_PD5 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x5)
1742 0 : #define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
1743 0 : #define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
1744 0 : #define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
1745 0 : #define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
1746 0 : #define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
1747 0 : #define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
1748 0 : #define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
1749 0 : #define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
1750 0 : #define MODEM_ANTRR5_PC8 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x8)
1751 0 : #define MODEM_ANTRR5_PC9 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x9)
1752 0 : #define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
1753 0 : #define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
1754 0 : #define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
1755 0 : #define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
1756 0 : #define MODEM_ANTRR5_PD4 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x4)
1757 0 : #define MODEM_ANTRR5_PD5 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x5)
1758 0 : #define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
1759 0 : #define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
1760 0 : #define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
1761 0 : #define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
1762 0 : #define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
1763 0 : #define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
1764 0 : #define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
1765 0 : #define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
1766 0 : #define MODEM_ANTSWEN_PC8 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x8)
1767 0 : #define MODEM_ANTSWEN_PC9 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x9)
1768 0 : #define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
1769 0 : #define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
1770 0 : #define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
1771 0 : #define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
1772 0 : #define MODEM_ANTSWEN_PD4 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x4)
1773 0 : #define MODEM_ANTSWEN_PD5 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x5)
1774 0 : #define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
1775 0 : #define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
1776 0 : #define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
1777 0 : #define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
1778 0 : #define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
1779 0 : #define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
1780 0 : #define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
1781 0 : #define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
1782 0 : #define MODEM_ANTSWUS_PC8 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x8)
1783 0 : #define MODEM_ANTSWUS_PC9 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x9)
1784 0 : #define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
1785 0 : #define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
1786 0 : #define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
1787 0 : #define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
1788 0 : #define MODEM_ANTSWUS_PD4 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x4)
1789 0 : #define MODEM_ANTSWUS_PD5 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x5)
1790 0 : #define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
1791 0 : #define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
1792 0 : #define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
1793 0 : #define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
1794 0 : #define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
1795 0 : #define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
1796 0 : #define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
1797 0 : #define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
1798 0 : #define MODEM_ANTTRIG_PC8 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x8)
1799 0 : #define MODEM_ANTTRIG_PC9 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x9)
1800 0 : #define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
1801 0 : #define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
1802 0 : #define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
1803 0 : #define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
1804 0 : #define MODEM_ANTTRIG_PD4 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x4)
1805 0 : #define MODEM_ANTTRIG_PD5 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x5)
1806 0 : #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
1807 0 : #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
1808 0 : #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
1809 0 : #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
1810 0 : #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
1811 0 : #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
1812 0 : #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
1813 0 : #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
1814 0 : #define MODEM_ANTTRIGSTOP_PC8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x8)
1815 0 : #define MODEM_ANTTRIGSTOP_PC9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x9)
1816 0 : #define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
1817 0 : #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
1818 0 : #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
1819 0 : #define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
1820 0 : #define MODEM_ANTTRIGSTOP_PD4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x4)
1821 0 : #define MODEM_ANTTRIGSTOP_PD5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x5)
1822 0 : #define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
1823 0 : #define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
1824 0 : #define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
1825 0 : #define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
1826 0 : #define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
1827 0 : #define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
1828 0 : #define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
1829 0 : #define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
1830 0 : #define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
1831 0 : #define MODEM_DCLK_PA9 SILABS_DBUS_MODEM_DCLK(0x0, 0x9)
1832 0 : #define MODEM_DCLK_PA10 SILABS_DBUS_MODEM_DCLK(0x0, 0xa)
1833 0 : #define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
1834 0 : #define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
1835 0 : #define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
1836 0 : #define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
1837 0 : #define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
1838 0 : #define MODEM_DCLK_PB5 SILABS_DBUS_MODEM_DCLK(0x1, 0x5)
1839 0 : #define MODEM_DCLK_PB6 SILABS_DBUS_MODEM_DCLK(0x1, 0x6)
1840 0 : #define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
1841 0 : #define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
1842 0 : #define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
1843 0 : #define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
1844 0 : #define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
1845 0 : #define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
1846 0 : #define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
1847 0 : #define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
1848 0 : #define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
1849 0 : #define MODEM_DOUT_PA9 SILABS_DBUS_MODEM_DOUT(0x0, 0x9)
1850 0 : #define MODEM_DOUT_PA10 SILABS_DBUS_MODEM_DOUT(0x0, 0xa)
1851 0 : #define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
1852 0 : #define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
1853 0 : #define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
1854 0 : #define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
1855 0 : #define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
1856 0 : #define MODEM_DOUT_PB5 SILABS_DBUS_MODEM_DOUT(0x1, 0x5)
1857 0 : #define MODEM_DOUT_PB6 SILABS_DBUS_MODEM_DOUT(0x1, 0x6)
1858 0 : #define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0)
1859 0 : #define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1)
1860 0 : #define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2)
1861 0 : #define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3)
1862 0 : #define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4)
1863 0 : #define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5)
1864 0 : #define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6)
1865 0 : #define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7)
1866 0 : #define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8)
1867 0 : #define MODEM_DIN_PA9 SILABS_DBUS_MODEM_DIN(0x0, 0x9)
1868 0 : #define MODEM_DIN_PA10 SILABS_DBUS_MODEM_DIN(0x0, 0xa)
1869 0 : #define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0)
1870 0 : #define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1)
1871 0 : #define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2)
1872 0 : #define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3)
1873 0 : #define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4)
1874 0 : #define MODEM_DIN_PB5 SILABS_DBUS_MODEM_DIN(0x1, 0x5)
1875 0 : #define MODEM_DIN_PB6 SILABS_DBUS_MODEM_DIN(0x1, 0x6)
1876 :
1877 0 : #define PCNT0_S0IN_PA0 SILABS_DBUS_PCNT0_S0IN(0x0, 0x0)
1878 0 : #define PCNT0_S0IN_PA1 SILABS_DBUS_PCNT0_S0IN(0x0, 0x1)
1879 0 : #define PCNT0_S0IN_PA2 SILABS_DBUS_PCNT0_S0IN(0x0, 0x2)
1880 0 : #define PCNT0_S0IN_PA3 SILABS_DBUS_PCNT0_S0IN(0x0, 0x3)
1881 0 : #define PCNT0_S0IN_PA4 SILABS_DBUS_PCNT0_S0IN(0x0, 0x4)
1882 0 : #define PCNT0_S0IN_PA5 SILABS_DBUS_PCNT0_S0IN(0x0, 0x5)
1883 0 : #define PCNT0_S0IN_PA6 SILABS_DBUS_PCNT0_S0IN(0x0, 0x6)
1884 0 : #define PCNT0_S0IN_PA7 SILABS_DBUS_PCNT0_S0IN(0x0, 0x7)
1885 0 : #define PCNT0_S0IN_PA8 SILABS_DBUS_PCNT0_S0IN(0x0, 0x8)
1886 0 : #define PCNT0_S0IN_PA9 SILABS_DBUS_PCNT0_S0IN(0x0, 0x9)
1887 0 : #define PCNT0_S0IN_PA10 SILABS_DBUS_PCNT0_S0IN(0x0, 0xa)
1888 0 : #define PCNT0_S0IN_PB0 SILABS_DBUS_PCNT0_S0IN(0x1, 0x0)
1889 0 : #define PCNT0_S0IN_PB1 SILABS_DBUS_PCNT0_S0IN(0x1, 0x1)
1890 0 : #define PCNT0_S0IN_PB2 SILABS_DBUS_PCNT0_S0IN(0x1, 0x2)
1891 0 : #define PCNT0_S0IN_PB3 SILABS_DBUS_PCNT0_S0IN(0x1, 0x3)
1892 0 : #define PCNT0_S0IN_PB4 SILABS_DBUS_PCNT0_S0IN(0x1, 0x4)
1893 0 : #define PCNT0_S0IN_PB5 SILABS_DBUS_PCNT0_S0IN(0x1, 0x5)
1894 0 : #define PCNT0_S0IN_PB6 SILABS_DBUS_PCNT0_S0IN(0x1, 0x6)
1895 0 : #define PCNT0_S1IN_PA0 SILABS_DBUS_PCNT0_S1IN(0x0, 0x0)
1896 0 : #define PCNT0_S1IN_PA1 SILABS_DBUS_PCNT0_S1IN(0x0, 0x1)
1897 0 : #define PCNT0_S1IN_PA2 SILABS_DBUS_PCNT0_S1IN(0x0, 0x2)
1898 0 : #define PCNT0_S1IN_PA3 SILABS_DBUS_PCNT0_S1IN(0x0, 0x3)
1899 0 : #define PCNT0_S1IN_PA4 SILABS_DBUS_PCNT0_S1IN(0x0, 0x4)
1900 0 : #define PCNT0_S1IN_PA5 SILABS_DBUS_PCNT0_S1IN(0x0, 0x5)
1901 0 : #define PCNT0_S1IN_PA6 SILABS_DBUS_PCNT0_S1IN(0x0, 0x6)
1902 0 : #define PCNT0_S1IN_PA7 SILABS_DBUS_PCNT0_S1IN(0x0, 0x7)
1903 0 : #define PCNT0_S1IN_PA8 SILABS_DBUS_PCNT0_S1IN(0x0, 0x8)
1904 0 : #define PCNT0_S1IN_PA9 SILABS_DBUS_PCNT0_S1IN(0x0, 0x9)
1905 0 : #define PCNT0_S1IN_PA10 SILABS_DBUS_PCNT0_S1IN(0x0, 0xa)
1906 0 : #define PCNT0_S1IN_PB0 SILABS_DBUS_PCNT0_S1IN(0x1, 0x0)
1907 0 : #define PCNT0_S1IN_PB1 SILABS_DBUS_PCNT0_S1IN(0x1, 0x1)
1908 0 : #define PCNT0_S1IN_PB2 SILABS_DBUS_PCNT0_S1IN(0x1, 0x2)
1909 0 : #define PCNT0_S1IN_PB3 SILABS_DBUS_PCNT0_S1IN(0x1, 0x3)
1910 0 : #define PCNT0_S1IN_PB4 SILABS_DBUS_PCNT0_S1IN(0x1, 0x4)
1911 0 : #define PCNT0_S1IN_PB5 SILABS_DBUS_PCNT0_S1IN(0x1, 0x5)
1912 0 : #define PCNT0_S1IN_PB6 SILABS_DBUS_PCNT0_S1IN(0x1, 0x6)
1913 :
1914 0 : #define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
1915 0 : #define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
1916 0 : #define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
1917 0 : #define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
1918 0 : #define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
1919 0 : #define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
1920 0 : #define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
1921 0 : #define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
1922 0 : #define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
1923 0 : #define PRS0_ASYNCH0_PA9 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x9)
1924 0 : #define PRS0_ASYNCH0_PA10 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xa)
1925 0 : #define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
1926 0 : #define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
1927 0 : #define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
1928 0 : #define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
1929 0 : #define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
1930 0 : #define PRS0_ASYNCH0_PB5 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x5)
1931 0 : #define PRS0_ASYNCH0_PB6 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x6)
1932 0 : #define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
1933 0 : #define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
1934 0 : #define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
1935 0 : #define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
1936 0 : #define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
1937 0 : #define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
1938 0 : #define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
1939 0 : #define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
1940 0 : #define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
1941 0 : #define PRS0_ASYNCH1_PA9 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x9)
1942 0 : #define PRS0_ASYNCH1_PA10 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xa)
1943 0 : #define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
1944 0 : #define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
1945 0 : #define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
1946 0 : #define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
1947 0 : #define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
1948 0 : #define PRS0_ASYNCH1_PB5 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x5)
1949 0 : #define PRS0_ASYNCH1_PB6 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x6)
1950 0 : #define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
1951 0 : #define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
1952 0 : #define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
1953 0 : #define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
1954 0 : #define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
1955 0 : #define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
1956 0 : #define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
1957 0 : #define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
1958 0 : #define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
1959 0 : #define PRS0_ASYNCH2_PA9 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x9)
1960 0 : #define PRS0_ASYNCH2_PA10 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xa)
1961 0 : #define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
1962 0 : #define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
1963 0 : #define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
1964 0 : #define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
1965 0 : #define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
1966 0 : #define PRS0_ASYNCH2_PB5 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x5)
1967 0 : #define PRS0_ASYNCH2_PB6 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x6)
1968 0 : #define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
1969 0 : #define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
1970 0 : #define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
1971 0 : #define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
1972 0 : #define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
1973 0 : #define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
1974 0 : #define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
1975 0 : #define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
1976 0 : #define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
1977 0 : #define PRS0_ASYNCH3_PA9 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x9)
1978 0 : #define PRS0_ASYNCH3_PA10 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xa)
1979 0 : #define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
1980 0 : #define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
1981 0 : #define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
1982 0 : #define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
1983 0 : #define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
1984 0 : #define PRS0_ASYNCH3_PB5 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x5)
1985 0 : #define PRS0_ASYNCH3_PB6 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x6)
1986 0 : #define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
1987 0 : #define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
1988 0 : #define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
1989 0 : #define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
1990 0 : #define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
1991 0 : #define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
1992 0 : #define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
1993 0 : #define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
1994 0 : #define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
1995 0 : #define PRS0_ASYNCH4_PA9 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x9)
1996 0 : #define PRS0_ASYNCH4_PA10 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xa)
1997 0 : #define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
1998 0 : #define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
1999 0 : #define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
2000 0 : #define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
2001 0 : #define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
2002 0 : #define PRS0_ASYNCH4_PB5 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x5)
2003 0 : #define PRS0_ASYNCH4_PB6 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x6)
2004 0 : #define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
2005 0 : #define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
2006 0 : #define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
2007 0 : #define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
2008 0 : #define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
2009 0 : #define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
2010 0 : #define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
2011 0 : #define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
2012 0 : #define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
2013 0 : #define PRS0_ASYNCH5_PA9 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x9)
2014 0 : #define PRS0_ASYNCH5_PA10 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xa)
2015 0 : #define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
2016 0 : #define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
2017 0 : #define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
2018 0 : #define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
2019 0 : #define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
2020 0 : #define PRS0_ASYNCH5_PB5 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x5)
2021 0 : #define PRS0_ASYNCH5_PB6 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x6)
2022 0 : #define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
2023 0 : #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
2024 0 : #define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
2025 0 : #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
2026 0 : #define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
2027 0 : #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
2028 0 : #define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
2029 0 : #define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
2030 0 : #define PRS0_ASYNCH6_PC8 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x8)
2031 0 : #define PRS0_ASYNCH6_PC9 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x9)
2032 0 : #define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
2033 0 : #define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
2034 0 : #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
2035 0 : #define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
2036 0 : #define PRS0_ASYNCH6_PD4 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x4)
2037 0 : #define PRS0_ASYNCH6_PD5 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x5)
2038 0 : #define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
2039 0 : #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
2040 0 : #define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
2041 0 : #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
2042 0 : #define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
2043 0 : #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
2044 0 : #define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
2045 0 : #define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
2046 0 : #define PRS0_ASYNCH7_PC8 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x8)
2047 0 : #define PRS0_ASYNCH7_PC9 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x9)
2048 0 : #define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
2049 0 : #define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
2050 0 : #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
2051 0 : #define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
2052 0 : #define PRS0_ASYNCH7_PD4 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x4)
2053 0 : #define PRS0_ASYNCH7_PD5 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x5)
2054 0 : #define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
2055 0 : #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
2056 0 : #define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
2057 0 : #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
2058 0 : #define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
2059 0 : #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
2060 0 : #define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
2061 0 : #define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
2062 0 : #define PRS0_ASYNCH8_PC8 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x8)
2063 0 : #define PRS0_ASYNCH8_PC9 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x9)
2064 0 : #define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
2065 0 : #define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
2066 0 : #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
2067 0 : #define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
2068 0 : #define PRS0_ASYNCH8_PD4 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x4)
2069 0 : #define PRS0_ASYNCH8_PD5 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x5)
2070 0 : #define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
2071 0 : #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
2072 0 : #define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
2073 0 : #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
2074 0 : #define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
2075 0 : #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
2076 0 : #define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
2077 0 : #define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
2078 0 : #define PRS0_ASYNCH9_PC8 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x8)
2079 0 : #define PRS0_ASYNCH9_PC9 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x9)
2080 0 : #define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
2081 0 : #define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
2082 0 : #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
2083 0 : #define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
2084 0 : #define PRS0_ASYNCH9_PD4 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x4)
2085 0 : #define PRS0_ASYNCH9_PD5 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x5)
2086 0 : #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
2087 0 : #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
2088 0 : #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
2089 0 : #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
2090 0 : #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
2091 0 : #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
2092 0 : #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
2093 0 : #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
2094 0 : #define PRS0_ASYNCH10_PC8 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x8)
2095 0 : #define PRS0_ASYNCH10_PC9 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x9)
2096 0 : #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
2097 0 : #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
2098 0 : #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
2099 0 : #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
2100 0 : #define PRS0_ASYNCH10_PD4 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x4)
2101 0 : #define PRS0_ASYNCH10_PD5 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x5)
2102 0 : #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
2103 0 : #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
2104 0 : #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
2105 0 : #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
2106 0 : #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
2107 0 : #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
2108 0 : #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
2109 0 : #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
2110 0 : #define PRS0_ASYNCH11_PC8 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x8)
2111 0 : #define PRS0_ASYNCH11_PC9 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x9)
2112 0 : #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
2113 0 : #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
2114 0 : #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
2115 0 : #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
2116 0 : #define PRS0_ASYNCH11_PD4 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x4)
2117 0 : #define PRS0_ASYNCH11_PD5 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x5)
2118 0 : #define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
2119 0 : #define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
2120 0 : #define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
2121 0 : #define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
2122 0 : #define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
2123 0 : #define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
2124 0 : #define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
2125 0 : #define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
2126 0 : #define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
2127 0 : #define PRS0_SYNCH0_PA9 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x9)
2128 0 : #define PRS0_SYNCH0_PA10 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xa)
2129 0 : #define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
2130 0 : #define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
2131 0 : #define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
2132 0 : #define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
2133 0 : #define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
2134 0 : #define PRS0_SYNCH0_PB5 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x5)
2135 0 : #define PRS0_SYNCH0_PB6 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x6)
2136 0 : #define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
2137 0 : #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
2138 0 : #define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
2139 0 : #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
2140 0 : #define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
2141 0 : #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
2142 0 : #define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
2143 0 : #define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
2144 0 : #define PRS0_SYNCH0_PC8 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x8)
2145 0 : #define PRS0_SYNCH0_PC9 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x9)
2146 0 : #define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
2147 0 : #define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
2148 0 : #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
2149 0 : #define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
2150 0 : #define PRS0_SYNCH0_PD4 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x4)
2151 0 : #define PRS0_SYNCH0_PD5 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x5)
2152 0 : #define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
2153 0 : #define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
2154 0 : #define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
2155 0 : #define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
2156 0 : #define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
2157 0 : #define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
2158 0 : #define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
2159 0 : #define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
2160 0 : #define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
2161 0 : #define PRS0_SYNCH1_PA9 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x9)
2162 0 : #define PRS0_SYNCH1_PA10 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xa)
2163 0 : #define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
2164 0 : #define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
2165 0 : #define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
2166 0 : #define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
2167 0 : #define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
2168 0 : #define PRS0_SYNCH1_PB5 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x5)
2169 0 : #define PRS0_SYNCH1_PB6 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x6)
2170 0 : #define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
2171 0 : #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
2172 0 : #define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
2173 0 : #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
2174 0 : #define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
2175 0 : #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
2176 0 : #define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
2177 0 : #define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
2178 0 : #define PRS0_SYNCH1_PC8 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x8)
2179 0 : #define PRS0_SYNCH1_PC9 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x9)
2180 0 : #define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
2181 0 : #define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
2182 0 : #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
2183 0 : #define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
2184 0 : #define PRS0_SYNCH1_PD4 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x4)
2185 0 : #define PRS0_SYNCH1_PD5 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x5)
2186 0 : #define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
2187 0 : #define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
2188 0 : #define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
2189 0 : #define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
2190 0 : #define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
2191 0 : #define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
2192 0 : #define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
2193 0 : #define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
2194 0 : #define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
2195 0 : #define PRS0_SYNCH2_PA9 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x9)
2196 0 : #define PRS0_SYNCH2_PA10 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xa)
2197 0 : #define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
2198 0 : #define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
2199 0 : #define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
2200 0 : #define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
2201 0 : #define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
2202 0 : #define PRS0_SYNCH2_PB5 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x5)
2203 0 : #define PRS0_SYNCH2_PB6 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x6)
2204 0 : #define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
2205 0 : #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
2206 0 : #define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
2207 0 : #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
2208 0 : #define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
2209 0 : #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
2210 0 : #define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
2211 0 : #define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
2212 0 : #define PRS0_SYNCH2_PC8 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x8)
2213 0 : #define PRS0_SYNCH2_PC9 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x9)
2214 0 : #define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
2215 0 : #define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
2216 0 : #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
2217 0 : #define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
2218 0 : #define PRS0_SYNCH2_PD4 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x4)
2219 0 : #define PRS0_SYNCH2_PD5 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x5)
2220 0 : #define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
2221 0 : #define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
2222 0 : #define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
2223 0 : #define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
2224 0 : #define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
2225 0 : #define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
2226 0 : #define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
2227 0 : #define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
2228 0 : #define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
2229 0 : #define PRS0_SYNCH3_PA9 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x9)
2230 0 : #define PRS0_SYNCH3_PA10 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xa)
2231 0 : #define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
2232 0 : #define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
2233 0 : #define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
2234 0 : #define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
2235 0 : #define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
2236 0 : #define PRS0_SYNCH3_PB5 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x5)
2237 0 : #define PRS0_SYNCH3_PB6 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x6)
2238 0 : #define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
2239 0 : #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
2240 0 : #define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
2241 0 : #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
2242 0 : #define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
2243 0 : #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
2244 0 : #define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
2245 0 : #define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
2246 0 : #define PRS0_SYNCH3_PC8 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x8)
2247 0 : #define PRS0_SYNCH3_PC9 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x9)
2248 0 : #define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
2249 0 : #define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
2250 0 : #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
2251 0 : #define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
2252 0 : #define PRS0_SYNCH3_PD4 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x4)
2253 0 : #define PRS0_SYNCH3_PD5 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x5)
2254 :
2255 0 : #define HFXO0_BUFOUTREQINASYNC_PA0 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x0)
2256 0 : #define HFXO0_BUFOUTREQINASYNC_PA1 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x1)
2257 0 : #define HFXO0_BUFOUTREQINASYNC_PA2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x2)
2258 0 : #define HFXO0_BUFOUTREQINASYNC_PA3 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x3)
2259 0 : #define HFXO0_BUFOUTREQINASYNC_PA4 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x4)
2260 0 : #define HFXO0_BUFOUTREQINASYNC_PA5 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x5)
2261 0 : #define HFXO0_BUFOUTREQINASYNC_PA6 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x6)
2262 0 : #define HFXO0_BUFOUTREQINASYNC_PA7 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x7)
2263 0 : #define HFXO0_BUFOUTREQINASYNC_PA8 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x8)
2264 0 : #define HFXO0_BUFOUTREQINASYNC_PA9 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x9)
2265 0 : #define HFXO0_BUFOUTREQINASYNC_PA10 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0xa)
2266 0 : #define HFXO0_BUFOUTREQINASYNC_PB0 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x0)
2267 0 : #define HFXO0_BUFOUTREQINASYNC_PB1 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x1)
2268 0 : #define HFXO0_BUFOUTREQINASYNC_PB2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x2)
2269 0 : #define HFXO0_BUFOUTREQINASYNC_PB3 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x3)
2270 0 : #define HFXO0_BUFOUTREQINASYNC_PB4 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x4)
2271 0 : #define HFXO0_BUFOUTREQINASYNC_PB5 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x5)
2272 0 : #define HFXO0_BUFOUTREQINASYNC_PB6 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x6)
2273 :
2274 0 : #define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
2275 0 : #define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
2276 0 : #define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
2277 0 : #define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
2278 0 : #define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
2279 0 : #define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
2280 0 : #define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
2281 0 : #define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
2282 0 : #define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
2283 0 : #define TIMER0_CC0_PA9 SILABS_DBUS_TIMER0_CC0(0x0, 0x9)
2284 0 : #define TIMER0_CC0_PA10 SILABS_DBUS_TIMER0_CC0(0x0, 0xa)
2285 0 : #define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
2286 0 : #define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
2287 0 : #define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
2288 0 : #define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
2289 0 : #define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
2290 0 : #define TIMER0_CC0_PB5 SILABS_DBUS_TIMER0_CC0(0x1, 0x5)
2291 0 : #define TIMER0_CC0_PB6 SILABS_DBUS_TIMER0_CC0(0x1, 0x6)
2292 0 : #define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
2293 0 : #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
2294 0 : #define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
2295 0 : #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
2296 0 : #define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
2297 0 : #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
2298 0 : #define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
2299 0 : #define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
2300 0 : #define TIMER0_CC0_PC8 SILABS_DBUS_TIMER0_CC0(0x2, 0x8)
2301 0 : #define TIMER0_CC0_PC9 SILABS_DBUS_TIMER0_CC0(0x2, 0x9)
2302 0 : #define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
2303 0 : #define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
2304 0 : #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
2305 0 : #define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
2306 0 : #define TIMER0_CC0_PD4 SILABS_DBUS_TIMER0_CC0(0x3, 0x4)
2307 0 : #define TIMER0_CC0_PD5 SILABS_DBUS_TIMER0_CC0(0x3, 0x5)
2308 0 : #define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
2309 0 : #define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
2310 0 : #define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
2311 0 : #define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
2312 0 : #define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
2313 0 : #define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
2314 0 : #define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
2315 0 : #define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
2316 0 : #define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
2317 0 : #define TIMER0_CC1_PA9 SILABS_DBUS_TIMER0_CC1(0x0, 0x9)
2318 0 : #define TIMER0_CC1_PA10 SILABS_DBUS_TIMER0_CC1(0x0, 0xa)
2319 0 : #define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
2320 0 : #define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
2321 0 : #define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
2322 0 : #define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
2323 0 : #define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
2324 0 : #define TIMER0_CC1_PB5 SILABS_DBUS_TIMER0_CC1(0x1, 0x5)
2325 0 : #define TIMER0_CC1_PB6 SILABS_DBUS_TIMER0_CC1(0x1, 0x6)
2326 0 : #define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
2327 0 : #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
2328 0 : #define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
2329 0 : #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
2330 0 : #define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
2331 0 : #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
2332 0 : #define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
2333 0 : #define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
2334 0 : #define TIMER0_CC1_PC8 SILABS_DBUS_TIMER0_CC1(0x2, 0x8)
2335 0 : #define TIMER0_CC1_PC9 SILABS_DBUS_TIMER0_CC1(0x2, 0x9)
2336 0 : #define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
2337 0 : #define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
2338 0 : #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
2339 0 : #define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
2340 0 : #define TIMER0_CC1_PD4 SILABS_DBUS_TIMER0_CC1(0x3, 0x4)
2341 0 : #define TIMER0_CC1_PD5 SILABS_DBUS_TIMER0_CC1(0x3, 0x5)
2342 0 : #define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
2343 0 : #define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
2344 0 : #define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
2345 0 : #define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
2346 0 : #define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
2347 0 : #define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
2348 0 : #define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
2349 0 : #define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
2350 0 : #define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
2351 0 : #define TIMER0_CC2_PA9 SILABS_DBUS_TIMER0_CC2(0x0, 0x9)
2352 0 : #define TIMER0_CC2_PA10 SILABS_DBUS_TIMER0_CC2(0x0, 0xa)
2353 0 : #define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
2354 0 : #define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
2355 0 : #define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
2356 0 : #define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
2357 0 : #define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
2358 0 : #define TIMER0_CC2_PB5 SILABS_DBUS_TIMER0_CC2(0x1, 0x5)
2359 0 : #define TIMER0_CC2_PB6 SILABS_DBUS_TIMER0_CC2(0x1, 0x6)
2360 0 : #define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
2361 0 : #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
2362 0 : #define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
2363 0 : #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
2364 0 : #define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
2365 0 : #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
2366 0 : #define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
2367 0 : #define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
2368 0 : #define TIMER0_CC2_PC8 SILABS_DBUS_TIMER0_CC2(0x2, 0x8)
2369 0 : #define TIMER0_CC2_PC9 SILABS_DBUS_TIMER0_CC2(0x2, 0x9)
2370 0 : #define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
2371 0 : #define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
2372 0 : #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
2373 0 : #define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
2374 0 : #define TIMER0_CC2_PD4 SILABS_DBUS_TIMER0_CC2(0x3, 0x4)
2375 0 : #define TIMER0_CC2_PD5 SILABS_DBUS_TIMER0_CC2(0x3, 0x5)
2376 0 : #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
2377 0 : #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
2378 0 : #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
2379 0 : #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
2380 0 : #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
2381 0 : #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
2382 0 : #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
2383 0 : #define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
2384 0 : #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
2385 0 : #define TIMER0_CDTI0_PA9 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x9)
2386 0 : #define TIMER0_CDTI0_PA10 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xa)
2387 0 : #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
2388 0 : #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
2389 0 : #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
2390 0 : #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
2391 0 : #define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
2392 0 : #define TIMER0_CDTI0_PB5 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x5)
2393 0 : #define TIMER0_CDTI0_PB6 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x6)
2394 0 : #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
2395 0 : #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
2396 0 : #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
2397 0 : #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
2398 0 : #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
2399 0 : #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
2400 0 : #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
2401 0 : #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
2402 0 : #define TIMER0_CDTI0_PC8 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x8)
2403 0 : #define TIMER0_CDTI0_PC9 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x9)
2404 0 : #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
2405 0 : #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
2406 0 : #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
2407 0 : #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
2408 0 : #define TIMER0_CDTI0_PD4 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x4)
2409 0 : #define TIMER0_CDTI0_PD5 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x5)
2410 0 : #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
2411 0 : #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
2412 0 : #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
2413 0 : #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
2414 0 : #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
2415 0 : #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
2416 0 : #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
2417 0 : #define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
2418 0 : #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
2419 0 : #define TIMER0_CDTI1_PA9 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x9)
2420 0 : #define TIMER0_CDTI1_PA10 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xa)
2421 0 : #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
2422 0 : #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
2423 0 : #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
2424 0 : #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
2425 0 : #define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
2426 0 : #define TIMER0_CDTI1_PB5 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x5)
2427 0 : #define TIMER0_CDTI1_PB6 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x6)
2428 0 : #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
2429 0 : #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
2430 0 : #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
2431 0 : #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
2432 0 : #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
2433 0 : #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
2434 0 : #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
2435 0 : #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
2436 0 : #define TIMER0_CDTI1_PC8 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x8)
2437 0 : #define TIMER0_CDTI1_PC9 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x9)
2438 0 : #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
2439 0 : #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
2440 0 : #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
2441 0 : #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
2442 0 : #define TIMER0_CDTI1_PD4 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x4)
2443 0 : #define TIMER0_CDTI1_PD5 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x5)
2444 0 : #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
2445 0 : #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
2446 0 : #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
2447 0 : #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
2448 0 : #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
2449 0 : #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
2450 0 : #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
2451 0 : #define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
2452 0 : #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
2453 0 : #define TIMER0_CDTI2_PA9 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x9)
2454 0 : #define TIMER0_CDTI2_PA10 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xa)
2455 0 : #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
2456 0 : #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
2457 0 : #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
2458 0 : #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
2459 0 : #define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
2460 0 : #define TIMER0_CDTI2_PB5 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x5)
2461 0 : #define TIMER0_CDTI2_PB6 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x6)
2462 0 : #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
2463 0 : #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
2464 0 : #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
2465 0 : #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
2466 0 : #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
2467 0 : #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
2468 0 : #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
2469 0 : #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
2470 0 : #define TIMER0_CDTI2_PC8 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x8)
2471 0 : #define TIMER0_CDTI2_PC9 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x9)
2472 0 : #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
2473 0 : #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
2474 0 : #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
2475 0 : #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
2476 0 : #define TIMER0_CDTI2_PD4 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x4)
2477 0 : #define TIMER0_CDTI2_PD5 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x5)
2478 :
2479 0 : #define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
2480 0 : #define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
2481 0 : #define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
2482 0 : #define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
2483 0 : #define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
2484 0 : #define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
2485 0 : #define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
2486 0 : #define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
2487 0 : #define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
2488 0 : #define TIMER1_CC0_PA9 SILABS_DBUS_TIMER1_CC0(0x0, 0x9)
2489 0 : #define TIMER1_CC0_PA10 SILABS_DBUS_TIMER1_CC0(0x0, 0xa)
2490 0 : #define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
2491 0 : #define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
2492 0 : #define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
2493 0 : #define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
2494 0 : #define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
2495 0 : #define TIMER1_CC0_PB5 SILABS_DBUS_TIMER1_CC0(0x1, 0x5)
2496 0 : #define TIMER1_CC0_PB6 SILABS_DBUS_TIMER1_CC0(0x1, 0x6)
2497 0 : #define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
2498 0 : #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
2499 0 : #define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
2500 0 : #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
2501 0 : #define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
2502 0 : #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
2503 0 : #define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
2504 0 : #define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
2505 0 : #define TIMER1_CC0_PC8 SILABS_DBUS_TIMER1_CC0(0x2, 0x8)
2506 0 : #define TIMER1_CC0_PC9 SILABS_DBUS_TIMER1_CC0(0x2, 0x9)
2507 0 : #define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
2508 0 : #define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
2509 0 : #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
2510 0 : #define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
2511 0 : #define TIMER1_CC0_PD4 SILABS_DBUS_TIMER1_CC0(0x3, 0x4)
2512 0 : #define TIMER1_CC0_PD5 SILABS_DBUS_TIMER1_CC0(0x3, 0x5)
2513 0 : #define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
2514 0 : #define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
2515 0 : #define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
2516 0 : #define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
2517 0 : #define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
2518 0 : #define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
2519 0 : #define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
2520 0 : #define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
2521 0 : #define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
2522 0 : #define TIMER1_CC1_PA9 SILABS_DBUS_TIMER1_CC1(0x0, 0x9)
2523 0 : #define TIMER1_CC1_PA10 SILABS_DBUS_TIMER1_CC1(0x0, 0xa)
2524 0 : #define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
2525 0 : #define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
2526 0 : #define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
2527 0 : #define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
2528 0 : #define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
2529 0 : #define TIMER1_CC1_PB5 SILABS_DBUS_TIMER1_CC1(0x1, 0x5)
2530 0 : #define TIMER1_CC1_PB6 SILABS_DBUS_TIMER1_CC1(0x1, 0x6)
2531 0 : #define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
2532 0 : #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
2533 0 : #define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
2534 0 : #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
2535 0 : #define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
2536 0 : #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
2537 0 : #define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
2538 0 : #define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
2539 0 : #define TIMER1_CC1_PC8 SILABS_DBUS_TIMER1_CC1(0x2, 0x8)
2540 0 : #define TIMER1_CC1_PC9 SILABS_DBUS_TIMER1_CC1(0x2, 0x9)
2541 0 : #define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
2542 0 : #define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
2543 0 : #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
2544 0 : #define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
2545 0 : #define TIMER1_CC1_PD4 SILABS_DBUS_TIMER1_CC1(0x3, 0x4)
2546 0 : #define TIMER1_CC1_PD5 SILABS_DBUS_TIMER1_CC1(0x3, 0x5)
2547 0 : #define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
2548 0 : #define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
2549 0 : #define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
2550 0 : #define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
2551 0 : #define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
2552 0 : #define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
2553 0 : #define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
2554 0 : #define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
2555 0 : #define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
2556 0 : #define TIMER1_CC2_PA9 SILABS_DBUS_TIMER1_CC2(0x0, 0x9)
2557 0 : #define TIMER1_CC2_PA10 SILABS_DBUS_TIMER1_CC2(0x0, 0xa)
2558 0 : #define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
2559 0 : #define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
2560 0 : #define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
2561 0 : #define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
2562 0 : #define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
2563 0 : #define TIMER1_CC2_PB5 SILABS_DBUS_TIMER1_CC2(0x1, 0x5)
2564 0 : #define TIMER1_CC2_PB6 SILABS_DBUS_TIMER1_CC2(0x1, 0x6)
2565 0 : #define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
2566 0 : #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
2567 0 : #define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
2568 0 : #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
2569 0 : #define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
2570 0 : #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
2571 0 : #define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
2572 0 : #define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
2573 0 : #define TIMER1_CC2_PC8 SILABS_DBUS_TIMER1_CC2(0x2, 0x8)
2574 0 : #define TIMER1_CC2_PC9 SILABS_DBUS_TIMER1_CC2(0x2, 0x9)
2575 0 : #define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
2576 0 : #define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
2577 0 : #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
2578 0 : #define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
2579 0 : #define TIMER1_CC2_PD4 SILABS_DBUS_TIMER1_CC2(0x3, 0x4)
2580 0 : #define TIMER1_CC2_PD5 SILABS_DBUS_TIMER1_CC2(0x3, 0x5)
2581 0 : #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
2582 0 : #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
2583 0 : #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
2584 0 : #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
2585 0 : #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
2586 0 : #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
2587 0 : #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
2588 0 : #define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
2589 0 : #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
2590 0 : #define TIMER1_CDTI0_PA9 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x9)
2591 0 : #define TIMER1_CDTI0_PA10 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xa)
2592 0 : #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
2593 0 : #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
2594 0 : #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
2595 0 : #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
2596 0 : #define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
2597 0 : #define TIMER1_CDTI0_PB5 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x5)
2598 0 : #define TIMER1_CDTI0_PB6 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x6)
2599 0 : #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
2600 0 : #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
2601 0 : #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
2602 0 : #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
2603 0 : #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
2604 0 : #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
2605 0 : #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
2606 0 : #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
2607 0 : #define TIMER1_CDTI0_PC8 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x8)
2608 0 : #define TIMER1_CDTI0_PC9 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x9)
2609 0 : #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
2610 0 : #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
2611 0 : #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
2612 0 : #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
2613 0 : #define TIMER1_CDTI0_PD4 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x4)
2614 0 : #define TIMER1_CDTI0_PD5 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x5)
2615 0 : #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
2616 0 : #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
2617 0 : #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
2618 0 : #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
2619 0 : #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
2620 0 : #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
2621 0 : #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
2622 0 : #define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
2623 0 : #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
2624 0 : #define TIMER1_CDTI1_PA9 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x9)
2625 0 : #define TIMER1_CDTI1_PA10 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xa)
2626 0 : #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
2627 0 : #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
2628 0 : #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
2629 0 : #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
2630 0 : #define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
2631 0 : #define TIMER1_CDTI1_PB5 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x5)
2632 0 : #define TIMER1_CDTI1_PB6 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x6)
2633 0 : #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
2634 0 : #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
2635 0 : #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
2636 0 : #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
2637 0 : #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
2638 0 : #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
2639 0 : #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
2640 0 : #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
2641 0 : #define TIMER1_CDTI1_PC8 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x8)
2642 0 : #define TIMER1_CDTI1_PC9 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x9)
2643 0 : #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
2644 0 : #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
2645 0 : #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
2646 0 : #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
2647 0 : #define TIMER1_CDTI1_PD4 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x4)
2648 0 : #define TIMER1_CDTI1_PD5 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x5)
2649 0 : #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
2650 0 : #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
2651 0 : #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
2652 0 : #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
2653 0 : #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
2654 0 : #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
2655 0 : #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
2656 0 : #define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
2657 0 : #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
2658 0 : #define TIMER1_CDTI2_PA9 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x9)
2659 0 : #define TIMER1_CDTI2_PA10 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xa)
2660 0 : #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
2661 0 : #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
2662 0 : #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
2663 0 : #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
2664 0 : #define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
2665 0 : #define TIMER1_CDTI2_PB5 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x5)
2666 0 : #define TIMER1_CDTI2_PB6 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x6)
2667 0 : #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
2668 0 : #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
2669 0 : #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
2670 0 : #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
2671 0 : #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
2672 0 : #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
2673 0 : #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
2674 0 : #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
2675 0 : #define TIMER1_CDTI2_PC8 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x8)
2676 0 : #define TIMER1_CDTI2_PC9 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x9)
2677 0 : #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
2678 0 : #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
2679 0 : #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
2680 0 : #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
2681 0 : #define TIMER1_CDTI2_PD4 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x4)
2682 0 : #define TIMER1_CDTI2_PD5 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x5)
2683 :
2684 0 : #define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
2685 0 : #define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
2686 0 : #define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
2687 0 : #define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
2688 0 : #define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
2689 0 : #define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
2690 0 : #define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
2691 0 : #define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
2692 0 : #define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
2693 0 : #define TIMER2_CC0_PA9 SILABS_DBUS_TIMER2_CC0(0x0, 0x9)
2694 0 : #define TIMER2_CC0_PA10 SILABS_DBUS_TIMER2_CC0(0x0, 0xa)
2695 0 : #define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
2696 0 : #define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
2697 0 : #define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
2698 0 : #define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
2699 0 : #define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
2700 0 : #define TIMER2_CC0_PB5 SILABS_DBUS_TIMER2_CC0(0x1, 0x5)
2701 0 : #define TIMER2_CC0_PB6 SILABS_DBUS_TIMER2_CC0(0x1, 0x6)
2702 0 : #define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
2703 0 : #define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
2704 0 : #define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
2705 0 : #define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
2706 0 : #define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
2707 0 : #define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
2708 0 : #define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
2709 0 : #define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
2710 0 : #define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
2711 0 : #define TIMER2_CC1_PA9 SILABS_DBUS_TIMER2_CC1(0x0, 0x9)
2712 0 : #define TIMER2_CC1_PA10 SILABS_DBUS_TIMER2_CC1(0x0, 0xa)
2713 0 : #define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
2714 0 : #define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
2715 0 : #define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
2716 0 : #define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
2717 0 : #define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
2718 0 : #define TIMER2_CC1_PB5 SILABS_DBUS_TIMER2_CC1(0x1, 0x5)
2719 0 : #define TIMER2_CC1_PB6 SILABS_DBUS_TIMER2_CC1(0x1, 0x6)
2720 0 : #define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
2721 0 : #define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
2722 0 : #define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
2723 0 : #define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
2724 0 : #define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
2725 0 : #define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
2726 0 : #define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
2727 0 : #define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
2728 0 : #define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
2729 0 : #define TIMER2_CC2_PA9 SILABS_DBUS_TIMER2_CC2(0x0, 0x9)
2730 0 : #define TIMER2_CC2_PA10 SILABS_DBUS_TIMER2_CC2(0x0, 0xa)
2731 0 : #define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
2732 0 : #define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
2733 0 : #define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
2734 0 : #define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
2735 0 : #define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
2736 0 : #define TIMER2_CC2_PB5 SILABS_DBUS_TIMER2_CC2(0x1, 0x5)
2737 0 : #define TIMER2_CC2_PB6 SILABS_DBUS_TIMER2_CC2(0x1, 0x6)
2738 0 : #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
2739 0 : #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
2740 0 : #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
2741 0 : #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
2742 0 : #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
2743 0 : #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
2744 0 : #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
2745 0 : #define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
2746 0 : #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
2747 0 : #define TIMER2_CDTI0_PA9 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x9)
2748 0 : #define TIMER2_CDTI0_PA10 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xa)
2749 0 : #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
2750 0 : #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
2751 0 : #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
2752 0 : #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
2753 0 : #define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
2754 0 : #define TIMER2_CDTI0_PB5 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x5)
2755 0 : #define TIMER2_CDTI0_PB6 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x6)
2756 0 : #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
2757 0 : #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
2758 0 : #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
2759 0 : #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
2760 0 : #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
2761 0 : #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
2762 0 : #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
2763 0 : #define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
2764 0 : #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
2765 0 : #define TIMER2_CDTI1_PA9 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x9)
2766 0 : #define TIMER2_CDTI1_PA10 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xa)
2767 0 : #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
2768 0 : #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
2769 0 : #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
2770 0 : #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
2771 0 : #define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
2772 0 : #define TIMER2_CDTI1_PB5 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x5)
2773 0 : #define TIMER2_CDTI1_PB6 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x6)
2774 0 : #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
2775 0 : #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
2776 0 : #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
2777 0 : #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
2778 0 : #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
2779 0 : #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
2780 0 : #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
2781 0 : #define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
2782 0 : #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
2783 0 : #define TIMER2_CDTI2_PA9 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x9)
2784 0 : #define TIMER2_CDTI2_PA10 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xa)
2785 0 : #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
2786 0 : #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
2787 0 : #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
2788 0 : #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
2789 0 : #define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
2790 0 : #define TIMER2_CDTI2_PB5 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x5)
2791 0 : #define TIMER2_CDTI2_PB6 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x6)
2792 :
2793 0 : #define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
2794 0 : #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
2795 0 : #define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
2796 0 : #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
2797 0 : #define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
2798 0 : #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
2799 0 : #define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
2800 0 : #define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
2801 0 : #define TIMER3_CC0_PC8 SILABS_DBUS_TIMER3_CC0(0x2, 0x8)
2802 0 : #define TIMER3_CC0_PC9 SILABS_DBUS_TIMER3_CC0(0x2, 0x9)
2803 0 : #define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
2804 0 : #define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
2805 0 : #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
2806 0 : #define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
2807 0 : #define TIMER3_CC0_PD4 SILABS_DBUS_TIMER3_CC0(0x3, 0x4)
2808 0 : #define TIMER3_CC0_PD5 SILABS_DBUS_TIMER3_CC0(0x3, 0x5)
2809 0 : #define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
2810 0 : #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
2811 0 : #define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
2812 0 : #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
2813 0 : #define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
2814 0 : #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
2815 0 : #define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
2816 0 : #define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
2817 0 : #define TIMER3_CC1_PC8 SILABS_DBUS_TIMER3_CC1(0x2, 0x8)
2818 0 : #define TIMER3_CC1_PC9 SILABS_DBUS_TIMER3_CC1(0x2, 0x9)
2819 0 : #define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
2820 0 : #define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
2821 0 : #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
2822 0 : #define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
2823 0 : #define TIMER3_CC1_PD4 SILABS_DBUS_TIMER3_CC1(0x3, 0x4)
2824 0 : #define TIMER3_CC1_PD5 SILABS_DBUS_TIMER3_CC1(0x3, 0x5)
2825 0 : #define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
2826 0 : #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
2827 0 : #define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
2828 0 : #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
2829 0 : #define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
2830 0 : #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
2831 0 : #define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
2832 0 : #define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
2833 0 : #define TIMER3_CC2_PC8 SILABS_DBUS_TIMER3_CC2(0x2, 0x8)
2834 0 : #define TIMER3_CC2_PC9 SILABS_DBUS_TIMER3_CC2(0x2, 0x9)
2835 0 : #define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
2836 0 : #define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
2837 0 : #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
2838 0 : #define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
2839 0 : #define TIMER3_CC2_PD4 SILABS_DBUS_TIMER3_CC2(0x3, 0x4)
2840 0 : #define TIMER3_CC2_PD5 SILABS_DBUS_TIMER3_CC2(0x3, 0x5)
2841 0 : #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
2842 0 : #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
2843 0 : #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
2844 0 : #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
2845 0 : #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
2846 0 : #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
2847 0 : #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
2848 0 : #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
2849 0 : #define TIMER3_CDTI0_PC8 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x8)
2850 0 : #define TIMER3_CDTI0_PC9 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x9)
2851 0 : #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
2852 0 : #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
2853 0 : #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
2854 0 : #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
2855 0 : #define TIMER3_CDTI0_PD4 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x4)
2856 0 : #define TIMER3_CDTI0_PD5 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x5)
2857 0 : #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
2858 0 : #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
2859 0 : #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
2860 0 : #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
2861 0 : #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
2862 0 : #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
2863 0 : #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
2864 0 : #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
2865 0 : #define TIMER3_CDTI1_PC8 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x8)
2866 0 : #define TIMER3_CDTI1_PC9 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x9)
2867 0 : #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
2868 0 : #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
2869 0 : #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
2870 0 : #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
2871 0 : #define TIMER3_CDTI1_PD4 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x4)
2872 0 : #define TIMER3_CDTI1_PD5 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x5)
2873 0 : #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
2874 0 : #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
2875 0 : #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
2876 0 : #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
2877 0 : #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
2878 0 : #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
2879 0 : #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
2880 0 : #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
2881 0 : #define TIMER3_CDTI2_PC8 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x8)
2882 0 : #define TIMER3_CDTI2_PC9 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x9)
2883 0 : #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
2884 0 : #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
2885 0 : #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
2886 0 : #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
2887 0 : #define TIMER3_CDTI2_PD4 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x4)
2888 0 : #define TIMER3_CDTI2_PD5 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x5)
2889 :
2890 0 : #define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
2891 0 : #define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
2892 0 : #define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
2893 0 : #define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
2894 0 : #define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
2895 0 : #define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
2896 0 : #define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
2897 0 : #define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
2898 0 : #define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
2899 0 : #define TIMER4_CC0_PA9 SILABS_DBUS_TIMER4_CC0(0x0, 0x9)
2900 0 : #define TIMER4_CC0_PA10 SILABS_DBUS_TIMER4_CC0(0x0, 0xa)
2901 0 : #define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
2902 0 : #define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
2903 0 : #define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
2904 0 : #define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
2905 0 : #define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
2906 0 : #define TIMER4_CC0_PB5 SILABS_DBUS_TIMER4_CC0(0x1, 0x5)
2907 0 : #define TIMER4_CC0_PB6 SILABS_DBUS_TIMER4_CC0(0x1, 0x6)
2908 0 : #define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
2909 0 : #define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
2910 0 : #define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
2911 0 : #define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
2912 0 : #define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
2913 0 : #define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
2914 0 : #define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
2915 0 : #define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
2916 0 : #define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
2917 0 : #define TIMER4_CC1_PA9 SILABS_DBUS_TIMER4_CC1(0x0, 0x9)
2918 0 : #define TIMER4_CC1_PA10 SILABS_DBUS_TIMER4_CC1(0x0, 0xa)
2919 0 : #define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
2920 0 : #define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
2921 0 : #define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
2922 0 : #define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
2923 0 : #define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
2924 0 : #define TIMER4_CC1_PB5 SILABS_DBUS_TIMER4_CC1(0x1, 0x5)
2925 0 : #define TIMER4_CC1_PB6 SILABS_DBUS_TIMER4_CC1(0x1, 0x6)
2926 0 : #define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
2927 0 : #define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
2928 0 : #define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
2929 0 : #define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
2930 0 : #define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
2931 0 : #define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
2932 0 : #define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
2933 0 : #define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
2934 0 : #define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
2935 0 : #define TIMER4_CC2_PA9 SILABS_DBUS_TIMER4_CC2(0x0, 0x9)
2936 0 : #define TIMER4_CC2_PA10 SILABS_DBUS_TIMER4_CC2(0x0, 0xa)
2937 0 : #define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
2938 0 : #define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
2939 0 : #define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
2940 0 : #define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
2941 0 : #define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
2942 0 : #define TIMER4_CC2_PB5 SILABS_DBUS_TIMER4_CC2(0x1, 0x5)
2943 0 : #define TIMER4_CC2_PB6 SILABS_DBUS_TIMER4_CC2(0x1, 0x6)
2944 0 : #define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
2945 0 : #define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
2946 0 : #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
2947 0 : #define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
2948 0 : #define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
2949 0 : #define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
2950 0 : #define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
2951 0 : #define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
2952 0 : #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
2953 0 : #define TIMER4_CDTI0_PA9 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x9)
2954 0 : #define TIMER4_CDTI0_PA10 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xa)
2955 0 : #define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
2956 0 : #define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
2957 0 : #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
2958 0 : #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
2959 0 : #define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
2960 0 : #define TIMER4_CDTI0_PB5 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x5)
2961 0 : #define TIMER4_CDTI0_PB6 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x6)
2962 0 : #define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
2963 0 : #define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
2964 0 : #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
2965 0 : #define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
2966 0 : #define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
2967 0 : #define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
2968 0 : #define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
2969 0 : #define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
2970 0 : #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
2971 0 : #define TIMER4_CDTI1_PA9 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x9)
2972 0 : #define TIMER4_CDTI1_PA10 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xa)
2973 0 : #define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
2974 0 : #define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
2975 0 : #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
2976 0 : #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
2977 0 : #define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
2978 0 : #define TIMER4_CDTI1_PB5 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x5)
2979 0 : #define TIMER4_CDTI1_PB6 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x6)
2980 0 : #define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
2981 0 : #define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
2982 0 : #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
2983 0 : #define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
2984 0 : #define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
2985 0 : #define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
2986 0 : #define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
2987 0 : #define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
2988 0 : #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
2989 0 : #define TIMER4_CDTI2_PA9 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x9)
2990 0 : #define TIMER4_CDTI2_PA10 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xa)
2991 0 : #define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
2992 0 : #define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
2993 0 : #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
2994 0 : #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
2995 0 : #define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
2996 0 : #define TIMER4_CDTI2_PB5 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x5)
2997 0 : #define TIMER4_CDTI2_PB6 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x6)
2998 :
2999 0 : #define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0)
3000 0 : #define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1)
3001 0 : #define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2)
3002 0 : #define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3)
3003 0 : #define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4)
3004 0 : #define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5)
3005 0 : #define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6)
3006 0 : #define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7)
3007 0 : #define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8)
3008 0 : #define USART0_CS_PA9 SILABS_DBUS_USART0_CS(0x0, 0x9)
3009 0 : #define USART0_CS_PA10 SILABS_DBUS_USART0_CS(0x0, 0xa)
3010 0 : #define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0)
3011 0 : #define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1)
3012 0 : #define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2)
3013 0 : #define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3)
3014 0 : #define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4)
3015 0 : #define USART0_CS_PB5 SILABS_DBUS_USART0_CS(0x1, 0x5)
3016 0 : #define USART0_CS_PB6 SILABS_DBUS_USART0_CS(0x1, 0x6)
3017 0 : #define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0)
3018 0 : #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
3019 0 : #define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2)
3020 0 : #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
3021 0 : #define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4)
3022 0 : #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
3023 0 : #define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6)
3024 0 : #define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7)
3025 0 : #define USART0_CS_PC8 SILABS_DBUS_USART0_CS(0x2, 0x8)
3026 0 : #define USART0_CS_PC9 SILABS_DBUS_USART0_CS(0x2, 0x9)
3027 0 : #define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0)
3028 0 : #define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1)
3029 0 : #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
3030 0 : #define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3)
3031 0 : #define USART0_CS_PD4 SILABS_DBUS_USART0_CS(0x3, 0x4)
3032 0 : #define USART0_CS_PD5 SILABS_DBUS_USART0_CS(0x3, 0x5)
3033 0 : #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
3034 0 : #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
3035 0 : #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
3036 0 : #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
3037 0 : #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
3038 0 : #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
3039 0 : #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
3040 0 : #define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
3041 0 : #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
3042 0 : #define USART0_RTS_PA9 SILABS_DBUS_USART0_RTS(0x0, 0x9)
3043 0 : #define USART0_RTS_PA10 SILABS_DBUS_USART0_RTS(0x0, 0xa)
3044 0 : #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
3045 0 : #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
3046 0 : #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
3047 0 : #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
3048 0 : #define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
3049 0 : #define USART0_RTS_PB5 SILABS_DBUS_USART0_RTS(0x1, 0x5)
3050 0 : #define USART0_RTS_PB6 SILABS_DBUS_USART0_RTS(0x1, 0x6)
3051 0 : #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
3052 0 : #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
3053 0 : #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
3054 0 : #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
3055 0 : #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
3056 0 : #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
3057 0 : #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
3058 0 : #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
3059 0 : #define USART0_RTS_PC8 SILABS_DBUS_USART0_RTS(0x2, 0x8)
3060 0 : #define USART0_RTS_PC9 SILABS_DBUS_USART0_RTS(0x2, 0x9)
3061 0 : #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
3062 0 : #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
3063 0 : #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
3064 0 : #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
3065 0 : #define USART0_RTS_PD4 SILABS_DBUS_USART0_RTS(0x3, 0x4)
3066 0 : #define USART0_RTS_PD5 SILABS_DBUS_USART0_RTS(0x3, 0x5)
3067 0 : #define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0)
3068 0 : #define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1)
3069 0 : #define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2)
3070 0 : #define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3)
3071 0 : #define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4)
3072 0 : #define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5)
3073 0 : #define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6)
3074 0 : #define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7)
3075 0 : #define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8)
3076 0 : #define USART0_RX_PA9 SILABS_DBUS_USART0_RX(0x0, 0x9)
3077 0 : #define USART0_RX_PA10 SILABS_DBUS_USART0_RX(0x0, 0xa)
3078 0 : #define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0)
3079 0 : #define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1)
3080 0 : #define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2)
3081 0 : #define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3)
3082 0 : #define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4)
3083 0 : #define USART0_RX_PB5 SILABS_DBUS_USART0_RX(0x1, 0x5)
3084 0 : #define USART0_RX_PB6 SILABS_DBUS_USART0_RX(0x1, 0x6)
3085 0 : #define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0)
3086 0 : #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
3087 0 : #define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2)
3088 0 : #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
3089 0 : #define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4)
3090 0 : #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
3091 0 : #define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6)
3092 0 : #define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7)
3093 0 : #define USART0_RX_PC8 SILABS_DBUS_USART0_RX(0x2, 0x8)
3094 0 : #define USART0_RX_PC9 SILABS_DBUS_USART0_RX(0x2, 0x9)
3095 0 : #define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0)
3096 0 : #define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1)
3097 0 : #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
3098 0 : #define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3)
3099 0 : #define USART0_RX_PD4 SILABS_DBUS_USART0_RX(0x3, 0x4)
3100 0 : #define USART0_RX_PD5 SILABS_DBUS_USART0_RX(0x3, 0x5)
3101 0 : #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
3102 0 : #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
3103 0 : #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
3104 0 : #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
3105 0 : #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
3106 0 : #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
3107 0 : #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
3108 0 : #define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
3109 0 : #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
3110 0 : #define USART0_CLK_PA9 SILABS_DBUS_USART0_CLK(0x0, 0x9)
3111 0 : #define USART0_CLK_PA10 SILABS_DBUS_USART0_CLK(0x0, 0xa)
3112 0 : #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
3113 0 : #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
3114 0 : #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
3115 0 : #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
3116 0 : #define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
3117 0 : #define USART0_CLK_PB5 SILABS_DBUS_USART0_CLK(0x1, 0x5)
3118 0 : #define USART0_CLK_PB6 SILABS_DBUS_USART0_CLK(0x1, 0x6)
3119 0 : #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
3120 0 : #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
3121 0 : #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
3122 0 : #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
3123 0 : #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
3124 0 : #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
3125 0 : #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
3126 0 : #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
3127 0 : #define USART0_CLK_PC8 SILABS_DBUS_USART0_CLK(0x2, 0x8)
3128 0 : #define USART0_CLK_PC9 SILABS_DBUS_USART0_CLK(0x2, 0x9)
3129 0 : #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
3130 0 : #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
3131 0 : #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
3132 0 : #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
3133 0 : #define USART0_CLK_PD4 SILABS_DBUS_USART0_CLK(0x3, 0x4)
3134 0 : #define USART0_CLK_PD5 SILABS_DBUS_USART0_CLK(0x3, 0x5)
3135 0 : #define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0)
3136 0 : #define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1)
3137 0 : #define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2)
3138 0 : #define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3)
3139 0 : #define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4)
3140 0 : #define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5)
3141 0 : #define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6)
3142 0 : #define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7)
3143 0 : #define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8)
3144 0 : #define USART0_TX_PA9 SILABS_DBUS_USART0_TX(0x0, 0x9)
3145 0 : #define USART0_TX_PA10 SILABS_DBUS_USART0_TX(0x0, 0xa)
3146 0 : #define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0)
3147 0 : #define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1)
3148 0 : #define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2)
3149 0 : #define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3)
3150 0 : #define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4)
3151 0 : #define USART0_TX_PB5 SILABS_DBUS_USART0_TX(0x1, 0x5)
3152 0 : #define USART0_TX_PB6 SILABS_DBUS_USART0_TX(0x1, 0x6)
3153 0 : #define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0)
3154 0 : #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
3155 0 : #define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2)
3156 0 : #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
3157 0 : #define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4)
3158 0 : #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
3159 0 : #define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6)
3160 0 : #define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7)
3161 0 : #define USART0_TX_PC8 SILABS_DBUS_USART0_TX(0x2, 0x8)
3162 0 : #define USART0_TX_PC9 SILABS_DBUS_USART0_TX(0x2, 0x9)
3163 0 : #define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0)
3164 0 : #define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1)
3165 0 : #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
3166 0 : #define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3)
3167 0 : #define USART0_TX_PD4 SILABS_DBUS_USART0_TX(0x3, 0x4)
3168 0 : #define USART0_TX_PD5 SILABS_DBUS_USART0_TX(0x3, 0x5)
3169 0 : #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
3170 0 : #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
3171 0 : #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
3172 0 : #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
3173 0 : #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
3174 0 : #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
3175 0 : #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
3176 0 : #define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
3177 0 : #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
3178 0 : #define USART0_CTS_PA9 SILABS_DBUS_USART0_CTS(0x0, 0x9)
3179 0 : #define USART0_CTS_PA10 SILABS_DBUS_USART0_CTS(0x0, 0xa)
3180 0 : #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
3181 0 : #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
3182 0 : #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
3183 0 : #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
3184 0 : #define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
3185 0 : #define USART0_CTS_PB5 SILABS_DBUS_USART0_CTS(0x1, 0x5)
3186 0 : #define USART0_CTS_PB6 SILABS_DBUS_USART0_CTS(0x1, 0x6)
3187 0 : #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
3188 0 : #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
3189 0 : #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
3190 0 : #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
3191 0 : #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
3192 0 : #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
3193 0 : #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
3194 0 : #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
3195 0 : #define USART0_CTS_PC8 SILABS_DBUS_USART0_CTS(0x2, 0x8)
3196 0 : #define USART0_CTS_PC9 SILABS_DBUS_USART0_CTS(0x2, 0x9)
3197 0 : #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
3198 0 : #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
3199 0 : #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
3200 0 : #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
3201 0 : #define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4)
3202 0 : #define USART0_CTS_PD5 SILABS_DBUS_USART0_CTS(0x3, 0x5)
3203 :
3204 : #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG23_PINCTRL_H_ */
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