Line data Source code
1 0 : /*
2 : * Copyright (c) 2024 Silicon Laboratories Inc.
3 : * SPDX-License-Identifier: Apache-2.0
4 : *
5 : * Pin Control for Silicon Labs XG24 devices
6 : *
7 : * This file was generated by the script gen_pinctrl.py in the hal_silabs module.
8 : * Do not manually edit.
9 : */
10 :
11 : #ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG24_PINCTRL_H_
12 : #define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG24_PINCTRL_H_
13 :
14 : #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
15 :
16 0 : #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
17 :
18 0 : #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1)
19 :
20 0 : #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2)
21 0 : #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 10, 1, 1, 3)
22 0 : #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 10, 1, 2, 4)
23 0 : #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1)
24 :
25 0 : #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 21, 1, 0, 1)
26 0 : #define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 21, 1, 1, 3)
27 0 : #define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 21, 1, 2, 4)
28 0 : #define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 21, 1, 3, 5)
29 0 : #define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 21, 1, 4, 6)
30 0 : #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 21, 0, 0, 2)
31 :
32 0 : #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 29, 1, 0, 1)
33 0 : #define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 29, 1, 1, 3)
34 0 : #define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 29, 1, 2, 4)
35 0 : #define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 29, 1, 3, 5)
36 0 : #define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 29, 1, 4, 6)
37 0 : #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 29, 0, 0, 2)
38 :
39 0 : #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 37, 1, 0, 1)
40 0 : #define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 37, 1, 1, 2)
41 0 : #define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 37, 1, 2, 3)
42 :
43 0 : #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 42, 1, 0, 1)
44 0 : #define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 42, 1, 1, 2)
45 :
46 0 : #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 46, 1, 0, 1)
47 0 : #define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 46, 1, 1, 2)
48 :
49 0 : #define SILABS_DBUS_KEYSCAN_COLOUT0(port, pin) SILABS_DBUS(port, pin, 50, 1, 0, 1)
50 0 : #define SILABS_DBUS_KEYSCAN_COLOUT1(port, pin) SILABS_DBUS(port, pin, 50, 1, 1, 2)
51 0 : #define SILABS_DBUS_KEYSCAN_COLOUT2(port, pin) SILABS_DBUS(port, pin, 50, 1, 2, 3)
52 0 : #define SILABS_DBUS_KEYSCAN_COLOUT3(port, pin) SILABS_DBUS(port, pin, 50, 1, 3, 4)
53 0 : #define SILABS_DBUS_KEYSCAN_COLOUT4(port, pin) SILABS_DBUS(port, pin, 50, 1, 4, 5)
54 0 : #define SILABS_DBUS_KEYSCAN_COLOUT5(port, pin) SILABS_DBUS(port, pin, 50, 1, 5, 6)
55 0 : #define SILABS_DBUS_KEYSCAN_COLOUT6(port, pin) SILABS_DBUS(port, pin, 50, 1, 6, 7)
56 0 : #define SILABS_DBUS_KEYSCAN_COLOUT7(port, pin) SILABS_DBUS(port, pin, 50, 1, 7, 8)
57 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE0(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 9)
58 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE1(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 10)
59 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE2(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 11)
60 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE3(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 12)
61 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE4(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 13)
62 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE5(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 14)
63 :
64 0 : #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 66, 1, 0, 1)
65 0 : #define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 66, 1, 1, 2)
66 :
67 0 : #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1)
68 0 : #define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 70, 1, 1, 2)
69 0 : #define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 70, 1, 2, 3)
70 0 : #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 70, 1, 3, 4)
71 0 : #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 70, 1, 4, 5)
72 0 : #define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 70, 1, 5, 6)
73 0 : #define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 70, 1, 6, 7)
74 0 : #define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 70, 1, 7, 8)
75 0 : #define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 70, 1, 8, 9)
76 0 : #define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 70, 1, 9, 10)
77 0 : #define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 70, 1, 10, 11)
78 0 : #define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 70, 1, 11, 12)
79 0 : #define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 70, 1, 12, 13)
80 0 : #define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 70, 1, 13, 14)
81 0 : #define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 70, 1, 14, 16)
82 0 : #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 15)
83 :
84 0 : #define SILABS_DBUS_PCNT0_S0IN(port, pin) SILABS_DBUS(port, pin, 89, 0, 0, 0)
85 0 : #define SILABS_DBUS_PCNT0_S1IN(port, pin) SILABS_DBUS(port, pin, 89, 0, 0, 1)
86 :
87 0 : #define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 92, 1, 0, 1)
88 0 : #define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 92, 1, 1, 2)
89 0 : #define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 92, 1, 2, 3)
90 0 : #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 92, 1, 3, 4)
91 0 : #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 92, 1, 4, 5)
92 0 : #define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 92, 1, 5, 6)
93 0 : #define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 92, 1, 6, 7)
94 0 : #define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 92, 1, 7, 8)
95 0 : #define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 92, 1, 8, 9)
96 0 : #define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 92, 1, 9, 10)
97 0 : #define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 92, 1, 10, 11)
98 0 : #define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 92, 1, 11, 12)
99 0 : #define SILABS_DBUS_PRS0_ASYNCH12(port, pin) SILABS_DBUS(port, pin, 92, 1, 12, 13)
100 0 : #define SILABS_DBUS_PRS0_ASYNCH13(port, pin) SILABS_DBUS(port, pin, 92, 1, 13, 14)
101 0 : #define SILABS_DBUS_PRS0_ASYNCH14(port, pin) SILABS_DBUS(port, pin, 92, 1, 14, 15)
102 0 : #define SILABS_DBUS_PRS0_ASYNCH15(port, pin) SILABS_DBUS(port, pin, 92, 1, 15, 16)
103 0 : #define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 92, 1, 16, 17)
104 0 : #define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 92, 1, 17, 18)
105 0 : #define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 92, 1, 18, 19)
106 0 : #define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 92, 1, 19, 20)
107 :
108 0 : #define SILABS_DBUS_RAC_LNAEN(port, pin) SILABS_DBUS(port, pin, 114, 1, 0, 1)
109 0 : #define SILABS_DBUS_RAC_PAEN(port, pin) SILABS_DBUS(port, pin, 114, 1, 1, 2)
110 :
111 0 : #define SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(port, pin) SILABS_DBUS(port, pin, 142, 0, 0, 0)
112 :
113 0 : #define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 144, 1, 0, 1)
114 0 : #define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 144, 1, 1, 2)
115 0 : #define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 144, 1, 2, 3)
116 0 : #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 144, 1, 3, 4)
117 0 : #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 144, 1, 4, 5)
118 0 : #define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 144, 1, 5, 6)
119 :
120 0 : #define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 152, 1, 0, 1)
121 0 : #define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 152, 1, 1, 2)
122 0 : #define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 152, 1, 2, 3)
123 0 : #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 152, 1, 3, 4)
124 0 : #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 152, 1, 4, 5)
125 0 : #define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 152, 1, 5, 6)
126 :
127 0 : #define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 160, 1, 0, 1)
128 0 : #define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 160, 1, 1, 2)
129 0 : #define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 160, 1, 2, 3)
130 0 : #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 160, 1, 3, 4)
131 0 : #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 160, 1, 4, 5)
132 0 : #define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 160, 1, 5, 6)
133 :
134 0 : #define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 168, 1, 0, 1)
135 0 : #define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 168, 1, 1, 2)
136 0 : #define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 168, 1, 2, 3)
137 0 : #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 168, 1, 3, 4)
138 0 : #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 168, 1, 4, 5)
139 0 : #define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 168, 1, 5, 6)
140 :
141 0 : #define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 176, 1, 0, 1)
142 0 : #define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 176, 1, 1, 2)
143 0 : #define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 176, 1, 2, 3)
144 0 : #define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 176, 1, 3, 4)
145 0 : #define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 176, 1, 4, 5)
146 0 : #define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 176, 1, 5, 6)
147 :
148 0 : #define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 184, 1, 0, 1)
149 0 : #define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 184, 1, 1, 3)
150 0 : #define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 184, 1, 2, 4)
151 0 : #define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 184, 1, 3, 5)
152 0 : #define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 184, 1, 4, 6)
153 0 : #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 184, 0, 0, 2)
154 :
155 0 : #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
156 0 : #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
157 0 : #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
158 0 : #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
159 0 : #define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4)
160 0 : #define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
161 0 : #define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
162 0 : #define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7)
163 0 : #define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8)
164 0 : #define ACMP0_ACMPOUT_PA9 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x9)
165 0 : #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
166 0 : #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
167 0 : #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
168 0 : #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
169 0 : #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
170 0 : #define ACMP0_ACMPOUT_PB5 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x5)
171 0 : #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
172 0 : #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
173 0 : #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
174 0 : #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
175 0 : #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
176 0 : #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
177 0 : #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
178 0 : #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
179 0 : #define ACMP0_ACMPOUT_PC8 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x8)
180 0 : #define ACMP0_ACMPOUT_PC9 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x9)
181 0 : #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
182 0 : #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
183 0 : #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
184 0 : #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
185 0 : #define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4)
186 0 : #define ACMP0_ACMPOUT_PD5 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x5)
187 :
188 0 : #define ACMP1_ACMPOUT_PA0 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x0)
189 0 : #define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1)
190 0 : #define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2)
191 0 : #define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3)
192 0 : #define ACMP1_ACMPOUT_PA4 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x4)
193 0 : #define ACMP1_ACMPOUT_PA5 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x5)
194 0 : #define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6)
195 0 : #define ACMP1_ACMPOUT_PA7 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x7)
196 0 : #define ACMP1_ACMPOUT_PA8 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x8)
197 0 : #define ACMP1_ACMPOUT_PA9 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x9)
198 0 : #define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0)
199 0 : #define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1)
200 0 : #define ACMP1_ACMPOUT_PB2 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x2)
201 0 : #define ACMP1_ACMPOUT_PB3 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x3)
202 0 : #define ACMP1_ACMPOUT_PB4 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x4)
203 0 : #define ACMP1_ACMPOUT_PB5 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x5)
204 0 : #define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0)
205 0 : #define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1)
206 0 : #define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2)
207 0 : #define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3)
208 0 : #define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4)
209 0 : #define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5)
210 0 : #define ACMP1_ACMPOUT_PC6 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x6)
211 0 : #define ACMP1_ACMPOUT_PC7 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x7)
212 0 : #define ACMP1_ACMPOUT_PC8 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x8)
213 0 : #define ACMP1_ACMPOUT_PC9 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x9)
214 0 : #define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0)
215 0 : #define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1)
216 0 : #define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2)
217 0 : #define ACMP1_ACMPOUT_PD3 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x3)
218 0 : #define ACMP1_ACMPOUT_PD4 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x4)
219 0 : #define ACMP1_ACMPOUT_PD5 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x5)
220 :
221 0 : #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
222 0 : #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
223 0 : #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
224 0 : #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
225 0 : #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
226 0 : #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
227 0 : #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
228 0 : #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
229 0 : #define CMU_CLKOUT0_PC8 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x8)
230 0 : #define CMU_CLKOUT0_PC9 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x9)
231 0 : #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
232 0 : #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
233 0 : #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
234 0 : #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
235 0 : #define CMU_CLKOUT0_PD4 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x4)
236 0 : #define CMU_CLKOUT0_PD5 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x5)
237 0 : #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
238 0 : #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
239 0 : #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
240 0 : #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
241 0 : #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
242 0 : #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
243 0 : #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
244 0 : #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
245 0 : #define CMU_CLKOUT1_PC8 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x8)
246 0 : #define CMU_CLKOUT1_PC9 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x9)
247 0 : #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
248 0 : #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
249 0 : #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
250 0 : #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
251 0 : #define CMU_CLKOUT1_PD4 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x4)
252 0 : #define CMU_CLKOUT1_PD5 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x5)
253 0 : #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
254 0 : #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
255 0 : #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
256 0 : #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
257 0 : #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
258 0 : #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
259 0 : #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
260 0 : #define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
261 0 : #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
262 0 : #define CMU_CLKOUT2_PA9 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x9)
263 0 : #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
264 0 : #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
265 0 : #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
266 0 : #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
267 0 : #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
268 0 : #define CMU_CLKOUT2_PB5 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x5)
269 0 : #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
270 0 : #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
271 0 : #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
272 0 : #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
273 0 : #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
274 0 : #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
275 0 : #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
276 0 : #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
277 0 : #define CMU_CLKIN0_PC8 SILABS_DBUS_CMU_CLKIN0(0x2, 0x8)
278 0 : #define CMU_CLKIN0_PC9 SILABS_DBUS_CMU_CLKIN0(0x2, 0x9)
279 0 : #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
280 0 : #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
281 0 : #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
282 0 : #define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
283 0 : #define CMU_CLKIN0_PD4 SILABS_DBUS_CMU_CLKIN0(0x3, 0x4)
284 0 : #define CMU_CLKIN0_PD5 SILABS_DBUS_CMU_CLKIN0(0x3, 0x5)
285 :
286 0 : #define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0)
287 0 : #define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1)
288 0 : #define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2)
289 0 : #define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3)
290 0 : #define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4)
291 0 : #define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5)
292 0 : #define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6)
293 0 : #define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7)
294 0 : #define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8)
295 0 : #define EUSART0_CS_PA9 SILABS_DBUS_EUSART0_CS(0x0, 0x9)
296 0 : #define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0)
297 0 : #define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1)
298 0 : #define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2)
299 0 : #define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3)
300 0 : #define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4)
301 0 : #define EUSART0_CS_PB5 SILABS_DBUS_EUSART0_CS(0x1, 0x5)
302 0 : #define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0)
303 0 : #define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1)
304 0 : #define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2)
305 0 : #define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3)
306 0 : #define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4)
307 0 : #define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5)
308 0 : #define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6)
309 0 : #define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7)
310 0 : #define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8)
311 0 : #define EUSART0_RTS_PA9 SILABS_DBUS_EUSART0_RTS(0x0, 0x9)
312 0 : #define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0)
313 0 : #define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1)
314 0 : #define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
315 0 : #define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
316 0 : #define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4)
317 0 : #define EUSART0_RTS_PB5 SILABS_DBUS_EUSART0_RTS(0x1, 0x5)
318 0 : #define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0)
319 0 : #define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1)
320 0 : #define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2)
321 0 : #define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3)
322 0 : #define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4)
323 0 : #define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5)
324 0 : #define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6)
325 0 : #define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7)
326 0 : #define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8)
327 0 : #define EUSART0_RX_PA9 SILABS_DBUS_EUSART0_RX(0x0, 0x9)
328 0 : #define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0)
329 0 : #define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1)
330 0 : #define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2)
331 0 : #define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3)
332 0 : #define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4)
333 0 : #define EUSART0_RX_PB5 SILABS_DBUS_EUSART0_RX(0x1, 0x5)
334 0 : #define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0)
335 0 : #define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1)
336 0 : #define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2)
337 0 : #define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3)
338 0 : #define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4)
339 0 : #define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5)
340 0 : #define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6)
341 0 : #define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7)
342 0 : #define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8)
343 0 : #define EUSART0_SCLK_PA9 SILABS_DBUS_EUSART0_SCLK(0x0, 0x9)
344 0 : #define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0)
345 0 : #define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1)
346 0 : #define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
347 0 : #define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
348 0 : #define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4)
349 0 : #define EUSART0_SCLK_PB5 SILABS_DBUS_EUSART0_SCLK(0x1, 0x5)
350 0 : #define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0)
351 0 : #define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1)
352 0 : #define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2)
353 0 : #define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3)
354 0 : #define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4)
355 0 : #define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5)
356 0 : #define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6)
357 0 : #define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7)
358 0 : #define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8)
359 0 : #define EUSART0_TX_PA9 SILABS_DBUS_EUSART0_TX(0x0, 0x9)
360 0 : #define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0)
361 0 : #define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1)
362 0 : #define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2)
363 0 : #define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3)
364 0 : #define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4)
365 0 : #define EUSART0_TX_PB5 SILABS_DBUS_EUSART0_TX(0x1, 0x5)
366 0 : #define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0)
367 0 : #define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1)
368 0 : #define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2)
369 0 : #define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3)
370 0 : #define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4)
371 0 : #define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5)
372 0 : #define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6)
373 0 : #define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7)
374 0 : #define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8)
375 0 : #define EUSART0_CTS_PA9 SILABS_DBUS_EUSART0_CTS(0x0, 0x9)
376 0 : #define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0)
377 0 : #define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1)
378 0 : #define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
379 0 : #define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
380 0 : #define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4)
381 0 : #define EUSART0_CTS_PB5 SILABS_DBUS_EUSART0_CTS(0x1, 0x5)
382 :
383 0 : #define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0)
384 0 : #define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1)
385 0 : #define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2)
386 0 : #define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3)
387 0 : #define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4)
388 0 : #define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5)
389 0 : #define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6)
390 0 : #define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7)
391 0 : #define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8)
392 0 : #define EUSART1_CS_PA9 SILABS_DBUS_EUSART1_CS(0x0, 0x9)
393 0 : #define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0)
394 0 : #define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1)
395 0 : #define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2)
396 0 : #define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3)
397 0 : #define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4)
398 0 : #define EUSART1_CS_PB5 SILABS_DBUS_EUSART1_CS(0x1, 0x5)
399 0 : #define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0)
400 0 : #define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1)
401 0 : #define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2)
402 0 : #define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3)
403 0 : #define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4)
404 0 : #define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5)
405 0 : #define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6)
406 0 : #define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7)
407 0 : #define EUSART1_CS_PC8 SILABS_DBUS_EUSART1_CS(0x2, 0x8)
408 0 : #define EUSART1_CS_PC9 SILABS_DBUS_EUSART1_CS(0x2, 0x9)
409 0 : #define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0)
410 0 : #define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1)
411 0 : #define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2)
412 0 : #define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3)
413 0 : #define EUSART1_CS_PD4 SILABS_DBUS_EUSART1_CS(0x3, 0x4)
414 0 : #define EUSART1_CS_PD5 SILABS_DBUS_EUSART1_CS(0x3, 0x5)
415 0 : #define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0)
416 0 : #define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1)
417 0 : #define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2)
418 0 : #define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3)
419 0 : #define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4)
420 0 : #define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5)
421 0 : #define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6)
422 0 : #define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7)
423 0 : #define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8)
424 0 : #define EUSART1_RTS_PA9 SILABS_DBUS_EUSART1_RTS(0x0, 0x9)
425 0 : #define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0)
426 0 : #define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1)
427 0 : #define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2)
428 0 : #define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3)
429 0 : #define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4)
430 0 : #define EUSART1_RTS_PB5 SILABS_DBUS_EUSART1_RTS(0x1, 0x5)
431 0 : #define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0)
432 0 : #define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1)
433 0 : #define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2)
434 0 : #define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3)
435 0 : #define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4)
436 0 : #define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5)
437 0 : #define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6)
438 0 : #define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7)
439 0 : #define EUSART1_RTS_PC8 SILABS_DBUS_EUSART1_RTS(0x2, 0x8)
440 0 : #define EUSART1_RTS_PC9 SILABS_DBUS_EUSART1_RTS(0x2, 0x9)
441 0 : #define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0)
442 0 : #define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1)
443 0 : #define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2)
444 0 : #define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3)
445 0 : #define EUSART1_RTS_PD4 SILABS_DBUS_EUSART1_RTS(0x3, 0x4)
446 0 : #define EUSART1_RTS_PD5 SILABS_DBUS_EUSART1_RTS(0x3, 0x5)
447 0 : #define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0)
448 0 : #define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1)
449 0 : #define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2)
450 0 : #define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3)
451 0 : #define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4)
452 0 : #define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5)
453 0 : #define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6)
454 0 : #define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7)
455 0 : #define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8)
456 0 : #define EUSART1_RX_PA9 SILABS_DBUS_EUSART1_RX(0x0, 0x9)
457 0 : #define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0)
458 0 : #define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1)
459 0 : #define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2)
460 0 : #define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3)
461 0 : #define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4)
462 0 : #define EUSART1_RX_PB5 SILABS_DBUS_EUSART1_RX(0x1, 0x5)
463 0 : #define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0)
464 0 : #define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1)
465 0 : #define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2)
466 0 : #define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3)
467 0 : #define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4)
468 0 : #define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5)
469 0 : #define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6)
470 0 : #define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7)
471 0 : #define EUSART1_RX_PC8 SILABS_DBUS_EUSART1_RX(0x2, 0x8)
472 0 : #define EUSART1_RX_PC9 SILABS_DBUS_EUSART1_RX(0x2, 0x9)
473 0 : #define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0)
474 0 : #define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1)
475 0 : #define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2)
476 0 : #define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3)
477 0 : #define EUSART1_RX_PD4 SILABS_DBUS_EUSART1_RX(0x3, 0x4)
478 0 : #define EUSART1_RX_PD5 SILABS_DBUS_EUSART1_RX(0x3, 0x5)
479 0 : #define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0)
480 0 : #define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1)
481 0 : #define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2)
482 0 : #define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3)
483 0 : #define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4)
484 0 : #define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5)
485 0 : #define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6)
486 0 : #define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7)
487 0 : #define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8)
488 0 : #define EUSART1_SCLK_PA9 SILABS_DBUS_EUSART1_SCLK(0x0, 0x9)
489 0 : #define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0)
490 0 : #define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1)
491 0 : #define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2)
492 0 : #define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3)
493 0 : #define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4)
494 0 : #define EUSART1_SCLK_PB5 SILABS_DBUS_EUSART1_SCLK(0x1, 0x5)
495 0 : #define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0)
496 0 : #define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1)
497 0 : #define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2)
498 0 : #define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3)
499 0 : #define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4)
500 0 : #define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5)
501 0 : #define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6)
502 0 : #define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7)
503 0 : #define EUSART1_SCLK_PC8 SILABS_DBUS_EUSART1_SCLK(0x2, 0x8)
504 0 : #define EUSART1_SCLK_PC9 SILABS_DBUS_EUSART1_SCLK(0x2, 0x9)
505 0 : #define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0)
506 0 : #define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1)
507 0 : #define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2)
508 0 : #define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3)
509 0 : #define EUSART1_SCLK_PD4 SILABS_DBUS_EUSART1_SCLK(0x3, 0x4)
510 0 : #define EUSART1_SCLK_PD5 SILABS_DBUS_EUSART1_SCLK(0x3, 0x5)
511 0 : #define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0)
512 0 : #define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1)
513 0 : #define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2)
514 0 : #define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3)
515 0 : #define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4)
516 0 : #define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5)
517 0 : #define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6)
518 0 : #define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7)
519 0 : #define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8)
520 0 : #define EUSART1_TX_PA9 SILABS_DBUS_EUSART1_TX(0x0, 0x9)
521 0 : #define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0)
522 0 : #define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1)
523 0 : #define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2)
524 0 : #define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3)
525 0 : #define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4)
526 0 : #define EUSART1_TX_PB5 SILABS_DBUS_EUSART1_TX(0x1, 0x5)
527 0 : #define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0)
528 0 : #define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1)
529 0 : #define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2)
530 0 : #define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3)
531 0 : #define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4)
532 0 : #define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5)
533 0 : #define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6)
534 0 : #define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7)
535 0 : #define EUSART1_TX_PC8 SILABS_DBUS_EUSART1_TX(0x2, 0x8)
536 0 : #define EUSART1_TX_PC9 SILABS_DBUS_EUSART1_TX(0x2, 0x9)
537 0 : #define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0)
538 0 : #define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1)
539 0 : #define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2)
540 0 : #define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3)
541 0 : #define EUSART1_TX_PD4 SILABS_DBUS_EUSART1_TX(0x3, 0x4)
542 0 : #define EUSART1_TX_PD5 SILABS_DBUS_EUSART1_TX(0x3, 0x5)
543 0 : #define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0)
544 0 : #define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1)
545 0 : #define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2)
546 0 : #define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3)
547 0 : #define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4)
548 0 : #define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5)
549 0 : #define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6)
550 0 : #define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7)
551 0 : #define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8)
552 0 : #define EUSART1_CTS_PA9 SILABS_DBUS_EUSART1_CTS(0x0, 0x9)
553 0 : #define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0)
554 0 : #define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1)
555 0 : #define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2)
556 0 : #define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3)
557 0 : #define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4)
558 0 : #define EUSART1_CTS_PB5 SILABS_DBUS_EUSART1_CTS(0x1, 0x5)
559 0 : #define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0)
560 0 : #define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1)
561 0 : #define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2)
562 0 : #define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3)
563 0 : #define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4)
564 0 : #define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5)
565 0 : #define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6)
566 0 : #define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7)
567 0 : #define EUSART1_CTS_PC8 SILABS_DBUS_EUSART1_CTS(0x2, 0x8)
568 0 : #define EUSART1_CTS_PC9 SILABS_DBUS_EUSART1_CTS(0x2, 0x9)
569 0 : #define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0)
570 0 : #define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1)
571 0 : #define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2)
572 0 : #define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3)
573 0 : #define EUSART1_CTS_PD4 SILABS_DBUS_EUSART1_CTS(0x3, 0x4)
574 0 : #define EUSART1_CTS_PD5 SILABS_DBUS_EUSART1_CTS(0x3, 0x5)
575 :
576 0 : #define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0)
577 0 : #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
578 0 : #define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2)
579 0 : #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
580 0 : #define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4)
581 0 : #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
582 0 : #define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6)
583 0 : #define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7)
584 0 : #define PTI_DCLK_PC8 SILABS_DBUS_PTI_DCLK(0x2, 0x8)
585 0 : #define PTI_DCLK_PC9 SILABS_DBUS_PTI_DCLK(0x2, 0x9)
586 0 : #define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0)
587 0 : #define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1)
588 0 : #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
589 0 : #define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3)
590 0 : #define PTI_DCLK_PD4 SILABS_DBUS_PTI_DCLK(0x3, 0x4)
591 0 : #define PTI_DCLK_PD5 SILABS_DBUS_PTI_DCLK(0x3, 0x5)
592 0 : #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
593 0 : #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
594 0 : #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
595 0 : #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
596 0 : #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
597 0 : #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
598 0 : #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
599 0 : #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
600 0 : #define PTI_DFRAME_PC8 SILABS_DBUS_PTI_DFRAME(0x2, 0x8)
601 0 : #define PTI_DFRAME_PC9 SILABS_DBUS_PTI_DFRAME(0x2, 0x9)
602 0 : #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
603 0 : #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
604 0 : #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
605 0 : #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
606 0 : #define PTI_DFRAME_PD4 SILABS_DBUS_PTI_DFRAME(0x3, 0x4)
607 0 : #define PTI_DFRAME_PD5 SILABS_DBUS_PTI_DFRAME(0x3, 0x5)
608 0 : #define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0)
609 0 : #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
610 0 : #define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2)
611 0 : #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
612 0 : #define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4)
613 0 : #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
614 0 : #define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6)
615 0 : #define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7)
616 0 : #define PTI_DOUT_PC8 SILABS_DBUS_PTI_DOUT(0x2, 0x8)
617 0 : #define PTI_DOUT_PC9 SILABS_DBUS_PTI_DOUT(0x2, 0x9)
618 0 : #define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0)
619 0 : #define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1)
620 0 : #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
621 0 : #define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3)
622 0 : #define PTI_DOUT_PD4 SILABS_DBUS_PTI_DOUT(0x3, 0x4)
623 0 : #define PTI_DOUT_PD5 SILABS_DBUS_PTI_DOUT(0x3, 0x5)
624 :
625 0 : #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
626 0 : #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
627 0 : #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
628 0 : #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
629 0 : #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
630 0 : #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
631 0 : #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
632 0 : #define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
633 0 : #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
634 0 : #define I2C0_SCL_PA9 SILABS_DBUS_I2C0_SCL(0x0, 0x9)
635 0 : #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
636 0 : #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
637 0 : #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
638 0 : #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
639 0 : #define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
640 0 : #define I2C0_SCL_PB5 SILABS_DBUS_I2C0_SCL(0x1, 0x5)
641 0 : #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
642 0 : #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
643 0 : #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
644 0 : #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
645 0 : #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
646 0 : #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
647 0 : #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
648 0 : #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
649 0 : #define I2C0_SCL_PC8 SILABS_DBUS_I2C0_SCL(0x2, 0x8)
650 0 : #define I2C0_SCL_PC9 SILABS_DBUS_I2C0_SCL(0x2, 0x9)
651 0 : #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
652 0 : #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
653 0 : #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
654 0 : #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
655 0 : #define I2C0_SCL_PD4 SILABS_DBUS_I2C0_SCL(0x3, 0x4)
656 0 : #define I2C0_SCL_PD5 SILABS_DBUS_I2C0_SCL(0x3, 0x5)
657 0 : #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
658 0 : #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
659 0 : #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
660 0 : #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
661 0 : #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
662 0 : #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
663 0 : #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
664 0 : #define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
665 0 : #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
666 0 : #define I2C0_SDA_PA9 SILABS_DBUS_I2C0_SDA(0x0, 0x9)
667 0 : #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
668 0 : #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
669 0 : #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
670 0 : #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
671 0 : #define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
672 0 : #define I2C0_SDA_PB5 SILABS_DBUS_I2C0_SDA(0x1, 0x5)
673 0 : #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
674 0 : #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
675 0 : #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
676 0 : #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
677 0 : #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
678 0 : #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
679 0 : #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
680 0 : #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
681 0 : #define I2C0_SDA_PC8 SILABS_DBUS_I2C0_SDA(0x2, 0x8)
682 0 : #define I2C0_SDA_PC9 SILABS_DBUS_I2C0_SDA(0x2, 0x9)
683 0 : #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
684 0 : #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
685 0 : #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
686 0 : #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
687 0 : #define I2C0_SDA_PD4 SILABS_DBUS_I2C0_SDA(0x3, 0x4)
688 0 : #define I2C0_SDA_PD5 SILABS_DBUS_I2C0_SDA(0x3, 0x5)
689 :
690 0 : #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
691 0 : #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
692 0 : #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
693 0 : #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
694 0 : #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
695 0 : #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
696 0 : #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
697 0 : #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
698 0 : #define I2C1_SCL_PC8 SILABS_DBUS_I2C1_SCL(0x2, 0x8)
699 0 : #define I2C1_SCL_PC9 SILABS_DBUS_I2C1_SCL(0x2, 0x9)
700 0 : #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
701 0 : #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
702 0 : #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
703 0 : #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
704 0 : #define I2C1_SCL_PD4 SILABS_DBUS_I2C1_SCL(0x3, 0x4)
705 0 : #define I2C1_SCL_PD5 SILABS_DBUS_I2C1_SCL(0x3, 0x5)
706 0 : #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
707 0 : #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
708 0 : #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
709 0 : #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
710 0 : #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
711 0 : #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
712 0 : #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
713 0 : #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
714 0 : #define I2C1_SDA_PC8 SILABS_DBUS_I2C1_SDA(0x2, 0x8)
715 0 : #define I2C1_SDA_PC9 SILABS_DBUS_I2C1_SDA(0x2, 0x9)
716 0 : #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
717 0 : #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
718 0 : #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
719 0 : #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
720 0 : #define I2C1_SDA_PD4 SILABS_DBUS_I2C1_SDA(0x3, 0x4)
721 0 : #define I2C1_SDA_PD5 SILABS_DBUS_I2C1_SDA(0x3, 0x5)
722 :
723 0 : #define KEYSCAN_COLOUT0_PA0 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x0)
724 0 : #define KEYSCAN_COLOUT0_PA1 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x1)
725 0 : #define KEYSCAN_COLOUT0_PA2 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x2)
726 0 : #define KEYSCAN_COLOUT0_PA3 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x3)
727 0 : #define KEYSCAN_COLOUT0_PA4 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x4)
728 0 : #define KEYSCAN_COLOUT0_PA5 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x5)
729 0 : #define KEYSCAN_COLOUT0_PA6 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x6)
730 0 : #define KEYSCAN_COLOUT0_PA7 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x7)
731 0 : #define KEYSCAN_COLOUT0_PA8 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x8)
732 0 : #define KEYSCAN_COLOUT0_PA9 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x9)
733 0 : #define KEYSCAN_COLOUT0_PB0 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x0)
734 0 : #define KEYSCAN_COLOUT0_PB1 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x1)
735 0 : #define KEYSCAN_COLOUT0_PB2 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x2)
736 0 : #define KEYSCAN_COLOUT0_PB3 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x3)
737 0 : #define KEYSCAN_COLOUT0_PB4 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x4)
738 0 : #define KEYSCAN_COLOUT0_PB5 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x5)
739 0 : #define KEYSCAN_COLOUT0_PC0 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x0)
740 0 : #define KEYSCAN_COLOUT0_PC1 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x1)
741 0 : #define KEYSCAN_COLOUT0_PC2 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x2)
742 0 : #define KEYSCAN_COLOUT0_PC3 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x3)
743 0 : #define KEYSCAN_COLOUT0_PC4 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x4)
744 0 : #define KEYSCAN_COLOUT0_PC5 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x5)
745 0 : #define KEYSCAN_COLOUT0_PC6 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x6)
746 0 : #define KEYSCAN_COLOUT0_PC7 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x7)
747 0 : #define KEYSCAN_COLOUT0_PC8 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x8)
748 0 : #define KEYSCAN_COLOUT0_PC9 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x9)
749 0 : #define KEYSCAN_COLOUT0_PD0 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x0)
750 0 : #define KEYSCAN_COLOUT0_PD1 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x1)
751 0 : #define KEYSCAN_COLOUT0_PD2 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x2)
752 0 : #define KEYSCAN_COLOUT0_PD3 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x3)
753 0 : #define KEYSCAN_COLOUT0_PD4 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x4)
754 0 : #define KEYSCAN_COLOUT0_PD5 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x5)
755 0 : #define KEYSCAN_COLOUT1_PA0 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x0)
756 0 : #define KEYSCAN_COLOUT1_PA1 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x1)
757 0 : #define KEYSCAN_COLOUT1_PA2 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x2)
758 0 : #define KEYSCAN_COLOUT1_PA3 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x3)
759 0 : #define KEYSCAN_COLOUT1_PA4 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x4)
760 0 : #define KEYSCAN_COLOUT1_PA5 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x5)
761 0 : #define KEYSCAN_COLOUT1_PA6 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x6)
762 0 : #define KEYSCAN_COLOUT1_PA7 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x7)
763 0 : #define KEYSCAN_COLOUT1_PA8 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x8)
764 0 : #define KEYSCAN_COLOUT1_PA9 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x9)
765 0 : #define KEYSCAN_COLOUT1_PB0 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x0)
766 0 : #define KEYSCAN_COLOUT1_PB1 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x1)
767 0 : #define KEYSCAN_COLOUT1_PB2 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x2)
768 0 : #define KEYSCAN_COLOUT1_PB3 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x3)
769 0 : #define KEYSCAN_COLOUT1_PB4 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x4)
770 0 : #define KEYSCAN_COLOUT1_PB5 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x5)
771 0 : #define KEYSCAN_COLOUT1_PC0 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x0)
772 0 : #define KEYSCAN_COLOUT1_PC1 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x1)
773 0 : #define KEYSCAN_COLOUT1_PC2 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x2)
774 0 : #define KEYSCAN_COLOUT1_PC3 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x3)
775 0 : #define KEYSCAN_COLOUT1_PC4 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x4)
776 0 : #define KEYSCAN_COLOUT1_PC5 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x5)
777 0 : #define KEYSCAN_COLOUT1_PC6 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x6)
778 0 : #define KEYSCAN_COLOUT1_PC7 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x7)
779 0 : #define KEYSCAN_COLOUT1_PC8 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x8)
780 0 : #define KEYSCAN_COLOUT1_PC9 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x9)
781 0 : #define KEYSCAN_COLOUT1_PD0 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x0)
782 0 : #define KEYSCAN_COLOUT1_PD1 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x1)
783 0 : #define KEYSCAN_COLOUT1_PD2 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x2)
784 0 : #define KEYSCAN_COLOUT1_PD3 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x3)
785 0 : #define KEYSCAN_COLOUT1_PD4 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x4)
786 0 : #define KEYSCAN_COLOUT1_PD5 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x5)
787 0 : #define KEYSCAN_COLOUT2_PA0 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x0)
788 0 : #define KEYSCAN_COLOUT2_PA1 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x1)
789 0 : #define KEYSCAN_COLOUT2_PA2 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x2)
790 0 : #define KEYSCAN_COLOUT2_PA3 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x3)
791 0 : #define KEYSCAN_COLOUT2_PA4 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x4)
792 0 : #define KEYSCAN_COLOUT2_PA5 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x5)
793 0 : #define KEYSCAN_COLOUT2_PA6 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x6)
794 0 : #define KEYSCAN_COLOUT2_PA7 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x7)
795 0 : #define KEYSCAN_COLOUT2_PA8 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x8)
796 0 : #define KEYSCAN_COLOUT2_PA9 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x9)
797 0 : #define KEYSCAN_COLOUT2_PB0 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x0)
798 0 : #define KEYSCAN_COLOUT2_PB1 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x1)
799 0 : #define KEYSCAN_COLOUT2_PB2 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x2)
800 0 : #define KEYSCAN_COLOUT2_PB3 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x3)
801 0 : #define KEYSCAN_COLOUT2_PB4 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x4)
802 0 : #define KEYSCAN_COLOUT2_PB5 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x5)
803 0 : #define KEYSCAN_COLOUT2_PC0 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x0)
804 0 : #define KEYSCAN_COLOUT2_PC1 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x1)
805 0 : #define KEYSCAN_COLOUT2_PC2 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x2)
806 0 : #define KEYSCAN_COLOUT2_PC3 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x3)
807 0 : #define KEYSCAN_COLOUT2_PC4 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x4)
808 0 : #define KEYSCAN_COLOUT2_PC5 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x5)
809 0 : #define KEYSCAN_COLOUT2_PC6 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x6)
810 0 : #define KEYSCAN_COLOUT2_PC7 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x7)
811 0 : #define KEYSCAN_COLOUT2_PC8 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x8)
812 0 : #define KEYSCAN_COLOUT2_PC9 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x9)
813 0 : #define KEYSCAN_COLOUT2_PD0 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x0)
814 0 : #define KEYSCAN_COLOUT2_PD1 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x1)
815 0 : #define KEYSCAN_COLOUT2_PD2 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x2)
816 0 : #define KEYSCAN_COLOUT2_PD3 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x3)
817 0 : #define KEYSCAN_COLOUT2_PD4 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x4)
818 0 : #define KEYSCAN_COLOUT2_PD5 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x5)
819 0 : #define KEYSCAN_COLOUT3_PA0 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x0)
820 0 : #define KEYSCAN_COLOUT3_PA1 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x1)
821 0 : #define KEYSCAN_COLOUT3_PA2 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x2)
822 0 : #define KEYSCAN_COLOUT3_PA3 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x3)
823 0 : #define KEYSCAN_COLOUT3_PA4 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x4)
824 0 : #define KEYSCAN_COLOUT3_PA5 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x5)
825 0 : #define KEYSCAN_COLOUT3_PA6 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x6)
826 0 : #define KEYSCAN_COLOUT3_PA7 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x7)
827 0 : #define KEYSCAN_COLOUT3_PA8 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x8)
828 0 : #define KEYSCAN_COLOUT3_PA9 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x9)
829 0 : #define KEYSCAN_COLOUT3_PB0 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x0)
830 0 : #define KEYSCAN_COLOUT3_PB1 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x1)
831 0 : #define KEYSCAN_COLOUT3_PB2 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x2)
832 0 : #define KEYSCAN_COLOUT3_PB3 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x3)
833 0 : #define KEYSCAN_COLOUT3_PB4 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x4)
834 0 : #define KEYSCAN_COLOUT3_PB5 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x5)
835 0 : #define KEYSCAN_COLOUT3_PC0 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x0)
836 0 : #define KEYSCAN_COLOUT3_PC1 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x1)
837 0 : #define KEYSCAN_COLOUT3_PC2 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x2)
838 0 : #define KEYSCAN_COLOUT3_PC3 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x3)
839 0 : #define KEYSCAN_COLOUT3_PC4 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x4)
840 0 : #define KEYSCAN_COLOUT3_PC5 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x5)
841 0 : #define KEYSCAN_COLOUT3_PC6 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x6)
842 0 : #define KEYSCAN_COLOUT3_PC7 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x7)
843 0 : #define KEYSCAN_COLOUT3_PC8 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x8)
844 0 : #define KEYSCAN_COLOUT3_PC9 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x9)
845 0 : #define KEYSCAN_COLOUT3_PD0 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x0)
846 0 : #define KEYSCAN_COLOUT3_PD1 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x1)
847 0 : #define KEYSCAN_COLOUT3_PD2 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x2)
848 0 : #define KEYSCAN_COLOUT3_PD3 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x3)
849 0 : #define KEYSCAN_COLOUT3_PD4 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x4)
850 0 : #define KEYSCAN_COLOUT3_PD5 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x5)
851 0 : #define KEYSCAN_COLOUT4_PA0 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x0)
852 0 : #define KEYSCAN_COLOUT4_PA1 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x1)
853 0 : #define KEYSCAN_COLOUT4_PA2 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x2)
854 0 : #define KEYSCAN_COLOUT4_PA3 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x3)
855 0 : #define KEYSCAN_COLOUT4_PA4 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x4)
856 0 : #define KEYSCAN_COLOUT4_PA5 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x5)
857 0 : #define KEYSCAN_COLOUT4_PA6 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x6)
858 0 : #define KEYSCAN_COLOUT4_PA7 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x7)
859 0 : #define KEYSCAN_COLOUT4_PA8 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x8)
860 0 : #define KEYSCAN_COLOUT4_PA9 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x9)
861 0 : #define KEYSCAN_COLOUT4_PB0 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x0)
862 0 : #define KEYSCAN_COLOUT4_PB1 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x1)
863 0 : #define KEYSCAN_COLOUT4_PB2 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x2)
864 0 : #define KEYSCAN_COLOUT4_PB3 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x3)
865 0 : #define KEYSCAN_COLOUT4_PB4 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x4)
866 0 : #define KEYSCAN_COLOUT4_PB5 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x5)
867 0 : #define KEYSCAN_COLOUT4_PC0 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x0)
868 0 : #define KEYSCAN_COLOUT4_PC1 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x1)
869 0 : #define KEYSCAN_COLOUT4_PC2 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x2)
870 0 : #define KEYSCAN_COLOUT4_PC3 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x3)
871 0 : #define KEYSCAN_COLOUT4_PC4 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x4)
872 0 : #define KEYSCAN_COLOUT4_PC5 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x5)
873 0 : #define KEYSCAN_COLOUT4_PC6 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x6)
874 0 : #define KEYSCAN_COLOUT4_PC7 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x7)
875 0 : #define KEYSCAN_COLOUT4_PC8 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x8)
876 0 : #define KEYSCAN_COLOUT4_PC9 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x9)
877 0 : #define KEYSCAN_COLOUT4_PD0 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x0)
878 0 : #define KEYSCAN_COLOUT4_PD1 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x1)
879 0 : #define KEYSCAN_COLOUT4_PD2 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x2)
880 0 : #define KEYSCAN_COLOUT4_PD3 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x3)
881 0 : #define KEYSCAN_COLOUT4_PD4 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x4)
882 0 : #define KEYSCAN_COLOUT4_PD5 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x5)
883 0 : #define KEYSCAN_COLOUT5_PA0 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x0)
884 0 : #define KEYSCAN_COLOUT5_PA1 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x1)
885 0 : #define KEYSCAN_COLOUT5_PA2 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x2)
886 0 : #define KEYSCAN_COLOUT5_PA3 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x3)
887 0 : #define KEYSCAN_COLOUT5_PA4 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x4)
888 0 : #define KEYSCAN_COLOUT5_PA5 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x5)
889 0 : #define KEYSCAN_COLOUT5_PA6 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x6)
890 0 : #define KEYSCAN_COLOUT5_PA7 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x7)
891 0 : #define KEYSCAN_COLOUT5_PA8 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x8)
892 0 : #define KEYSCAN_COLOUT5_PA9 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x9)
893 0 : #define KEYSCAN_COLOUT5_PB0 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x0)
894 0 : #define KEYSCAN_COLOUT5_PB1 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x1)
895 0 : #define KEYSCAN_COLOUT5_PB2 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x2)
896 0 : #define KEYSCAN_COLOUT5_PB3 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x3)
897 0 : #define KEYSCAN_COLOUT5_PB4 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x4)
898 0 : #define KEYSCAN_COLOUT5_PB5 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x5)
899 0 : #define KEYSCAN_COLOUT5_PC0 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x0)
900 0 : #define KEYSCAN_COLOUT5_PC1 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x1)
901 0 : #define KEYSCAN_COLOUT5_PC2 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x2)
902 0 : #define KEYSCAN_COLOUT5_PC3 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x3)
903 0 : #define KEYSCAN_COLOUT5_PC4 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x4)
904 0 : #define KEYSCAN_COLOUT5_PC5 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x5)
905 0 : #define KEYSCAN_COLOUT5_PC6 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x6)
906 0 : #define KEYSCAN_COLOUT5_PC7 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x7)
907 0 : #define KEYSCAN_COLOUT5_PC8 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x8)
908 0 : #define KEYSCAN_COLOUT5_PC9 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x9)
909 0 : #define KEYSCAN_COLOUT5_PD0 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x0)
910 0 : #define KEYSCAN_COLOUT5_PD1 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x1)
911 0 : #define KEYSCAN_COLOUT5_PD2 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x2)
912 0 : #define KEYSCAN_COLOUT5_PD3 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x3)
913 0 : #define KEYSCAN_COLOUT5_PD4 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x4)
914 0 : #define KEYSCAN_COLOUT5_PD5 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x5)
915 0 : #define KEYSCAN_COLOUT6_PA0 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x0)
916 0 : #define KEYSCAN_COLOUT6_PA1 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x1)
917 0 : #define KEYSCAN_COLOUT6_PA2 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x2)
918 0 : #define KEYSCAN_COLOUT6_PA3 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x3)
919 0 : #define KEYSCAN_COLOUT6_PA4 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x4)
920 0 : #define KEYSCAN_COLOUT6_PA5 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x5)
921 0 : #define KEYSCAN_COLOUT6_PA6 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x6)
922 0 : #define KEYSCAN_COLOUT6_PA7 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x7)
923 0 : #define KEYSCAN_COLOUT6_PA8 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x8)
924 0 : #define KEYSCAN_COLOUT6_PA9 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x9)
925 0 : #define KEYSCAN_COLOUT6_PB0 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x0)
926 0 : #define KEYSCAN_COLOUT6_PB1 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x1)
927 0 : #define KEYSCAN_COLOUT6_PB2 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x2)
928 0 : #define KEYSCAN_COLOUT6_PB3 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x3)
929 0 : #define KEYSCAN_COLOUT6_PB4 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x4)
930 0 : #define KEYSCAN_COLOUT6_PB5 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x5)
931 0 : #define KEYSCAN_COLOUT6_PC0 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x0)
932 0 : #define KEYSCAN_COLOUT6_PC1 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x1)
933 0 : #define KEYSCAN_COLOUT6_PC2 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x2)
934 0 : #define KEYSCAN_COLOUT6_PC3 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x3)
935 0 : #define KEYSCAN_COLOUT6_PC4 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x4)
936 0 : #define KEYSCAN_COLOUT6_PC5 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x5)
937 0 : #define KEYSCAN_COLOUT6_PC6 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x6)
938 0 : #define KEYSCAN_COLOUT6_PC7 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x7)
939 0 : #define KEYSCAN_COLOUT6_PC8 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x8)
940 0 : #define KEYSCAN_COLOUT6_PC9 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x9)
941 0 : #define KEYSCAN_COLOUT6_PD0 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x0)
942 0 : #define KEYSCAN_COLOUT6_PD1 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x1)
943 0 : #define KEYSCAN_COLOUT6_PD2 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x2)
944 0 : #define KEYSCAN_COLOUT6_PD3 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x3)
945 0 : #define KEYSCAN_COLOUT6_PD4 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x4)
946 0 : #define KEYSCAN_COLOUT6_PD5 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x5)
947 0 : #define KEYSCAN_COLOUT7_PA0 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x0)
948 0 : #define KEYSCAN_COLOUT7_PA1 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x1)
949 0 : #define KEYSCAN_COLOUT7_PA2 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x2)
950 0 : #define KEYSCAN_COLOUT7_PA3 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x3)
951 0 : #define KEYSCAN_COLOUT7_PA4 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x4)
952 0 : #define KEYSCAN_COLOUT7_PA5 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x5)
953 0 : #define KEYSCAN_COLOUT7_PA6 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x6)
954 0 : #define KEYSCAN_COLOUT7_PA7 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x7)
955 0 : #define KEYSCAN_COLOUT7_PA8 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x8)
956 0 : #define KEYSCAN_COLOUT7_PA9 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x9)
957 0 : #define KEYSCAN_COLOUT7_PB0 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x0)
958 0 : #define KEYSCAN_COLOUT7_PB1 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x1)
959 0 : #define KEYSCAN_COLOUT7_PB2 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x2)
960 0 : #define KEYSCAN_COLOUT7_PB3 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x3)
961 0 : #define KEYSCAN_COLOUT7_PB4 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x4)
962 0 : #define KEYSCAN_COLOUT7_PB5 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x5)
963 0 : #define KEYSCAN_COLOUT7_PC0 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x0)
964 0 : #define KEYSCAN_COLOUT7_PC1 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x1)
965 0 : #define KEYSCAN_COLOUT7_PC2 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x2)
966 0 : #define KEYSCAN_COLOUT7_PC3 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x3)
967 0 : #define KEYSCAN_COLOUT7_PC4 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x4)
968 0 : #define KEYSCAN_COLOUT7_PC5 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x5)
969 0 : #define KEYSCAN_COLOUT7_PC6 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x6)
970 0 : #define KEYSCAN_COLOUT7_PC7 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x7)
971 0 : #define KEYSCAN_COLOUT7_PC8 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x8)
972 0 : #define KEYSCAN_COLOUT7_PC9 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x9)
973 0 : #define KEYSCAN_COLOUT7_PD0 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x0)
974 0 : #define KEYSCAN_COLOUT7_PD1 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x1)
975 0 : #define KEYSCAN_COLOUT7_PD2 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x2)
976 0 : #define KEYSCAN_COLOUT7_PD3 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x3)
977 0 : #define KEYSCAN_COLOUT7_PD4 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x4)
978 0 : #define KEYSCAN_COLOUT7_PD5 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x5)
979 0 : #define KEYSCAN_ROWSENSE0_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x0)
980 0 : #define KEYSCAN_ROWSENSE0_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x1)
981 0 : #define KEYSCAN_ROWSENSE0_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x2)
982 0 : #define KEYSCAN_ROWSENSE0_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x3)
983 0 : #define KEYSCAN_ROWSENSE0_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x4)
984 0 : #define KEYSCAN_ROWSENSE0_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x5)
985 0 : #define KEYSCAN_ROWSENSE0_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x6)
986 0 : #define KEYSCAN_ROWSENSE0_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x7)
987 0 : #define KEYSCAN_ROWSENSE0_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x8)
988 0 : #define KEYSCAN_ROWSENSE0_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x9)
989 0 : #define KEYSCAN_ROWSENSE0_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x0)
990 0 : #define KEYSCAN_ROWSENSE0_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x1)
991 0 : #define KEYSCAN_ROWSENSE0_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x2)
992 0 : #define KEYSCAN_ROWSENSE0_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x3)
993 0 : #define KEYSCAN_ROWSENSE0_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x4)
994 0 : #define KEYSCAN_ROWSENSE0_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x5)
995 0 : #define KEYSCAN_ROWSENSE1_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x0)
996 0 : #define KEYSCAN_ROWSENSE1_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x1)
997 0 : #define KEYSCAN_ROWSENSE1_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x2)
998 0 : #define KEYSCAN_ROWSENSE1_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x3)
999 0 : #define KEYSCAN_ROWSENSE1_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x4)
1000 0 : #define KEYSCAN_ROWSENSE1_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x5)
1001 0 : #define KEYSCAN_ROWSENSE1_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x6)
1002 0 : #define KEYSCAN_ROWSENSE1_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x7)
1003 0 : #define KEYSCAN_ROWSENSE1_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x8)
1004 0 : #define KEYSCAN_ROWSENSE1_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x9)
1005 0 : #define KEYSCAN_ROWSENSE1_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x0)
1006 0 : #define KEYSCAN_ROWSENSE1_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x1)
1007 0 : #define KEYSCAN_ROWSENSE1_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x2)
1008 0 : #define KEYSCAN_ROWSENSE1_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x3)
1009 0 : #define KEYSCAN_ROWSENSE1_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x4)
1010 0 : #define KEYSCAN_ROWSENSE1_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x5)
1011 0 : #define KEYSCAN_ROWSENSE2_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x0)
1012 0 : #define KEYSCAN_ROWSENSE2_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x1)
1013 0 : #define KEYSCAN_ROWSENSE2_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x2)
1014 0 : #define KEYSCAN_ROWSENSE2_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x3)
1015 0 : #define KEYSCAN_ROWSENSE2_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x4)
1016 0 : #define KEYSCAN_ROWSENSE2_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x5)
1017 0 : #define KEYSCAN_ROWSENSE2_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x6)
1018 0 : #define KEYSCAN_ROWSENSE2_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x7)
1019 0 : #define KEYSCAN_ROWSENSE2_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x8)
1020 0 : #define KEYSCAN_ROWSENSE2_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x9)
1021 0 : #define KEYSCAN_ROWSENSE2_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x0)
1022 0 : #define KEYSCAN_ROWSENSE2_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x1)
1023 0 : #define KEYSCAN_ROWSENSE2_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x2)
1024 0 : #define KEYSCAN_ROWSENSE2_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x3)
1025 0 : #define KEYSCAN_ROWSENSE2_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x4)
1026 0 : #define KEYSCAN_ROWSENSE2_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x5)
1027 0 : #define KEYSCAN_ROWSENSE3_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x0)
1028 0 : #define KEYSCAN_ROWSENSE3_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x1)
1029 0 : #define KEYSCAN_ROWSENSE3_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x2)
1030 0 : #define KEYSCAN_ROWSENSE3_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x3)
1031 0 : #define KEYSCAN_ROWSENSE3_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x4)
1032 0 : #define KEYSCAN_ROWSENSE3_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x5)
1033 0 : #define KEYSCAN_ROWSENSE3_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x6)
1034 0 : #define KEYSCAN_ROWSENSE3_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x7)
1035 0 : #define KEYSCAN_ROWSENSE3_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x8)
1036 0 : #define KEYSCAN_ROWSENSE3_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x9)
1037 0 : #define KEYSCAN_ROWSENSE3_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x0)
1038 0 : #define KEYSCAN_ROWSENSE3_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x1)
1039 0 : #define KEYSCAN_ROWSENSE3_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x2)
1040 0 : #define KEYSCAN_ROWSENSE3_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x3)
1041 0 : #define KEYSCAN_ROWSENSE3_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x4)
1042 0 : #define KEYSCAN_ROWSENSE3_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x5)
1043 0 : #define KEYSCAN_ROWSENSE4_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x0)
1044 0 : #define KEYSCAN_ROWSENSE4_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x1)
1045 0 : #define KEYSCAN_ROWSENSE4_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x2)
1046 0 : #define KEYSCAN_ROWSENSE4_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x3)
1047 0 : #define KEYSCAN_ROWSENSE4_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x4)
1048 0 : #define KEYSCAN_ROWSENSE4_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x5)
1049 0 : #define KEYSCAN_ROWSENSE4_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x6)
1050 0 : #define KEYSCAN_ROWSENSE4_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x7)
1051 0 : #define KEYSCAN_ROWSENSE4_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x8)
1052 0 : #define KEYSCAN_ROWSENSE4_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x9)
1053 0 : #define KEYSCAN_ROWSENSE4_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x0)
1054 0 : #define KEYSCAN_ROWSENSE4_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x1)
1055 0 : #define KEYSCAN_ROWSENSE4_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x2)
1056 0 : #define KEYSCAN_ROWSENSE4_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x3)
1057 0 : #define KEYSCAN_ROWSENSE4_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x4)
1058 0 : #define KEYSCAN_ROWSENSE4_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x5)
1059 0 : #define KEYSCAN_ROWSENSE5_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x0)
1060 0 : #define KEYSCAN_ROWSENSE5_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x1)
1061 0 : #define KEYSCAN_ROWSENSE5_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x2)
1062 0 : #define KEYSCAN_ROWSENSE5_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x3)
1063 0 : #define KEYSCAN_ROWSENSE5_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x4)
1064 0 : #define KEYSCAN_ROWSENSE5_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x5)
1065 0 : #define KEYSCAN_ROWSENSE5_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x6)
1066 0 : #define KEYSCAN_ROWSENSE5_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x7)
1067 0 : #define KEYSCAN_ROWSENSE5_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x8)
1068 0 : #define KEYSCAN_ROWSENSE5_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x9)
1069 0 : #define KEYSCAN_ROWSENSE5_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x0)
1070 0 : #define KEYSCAN_ROWSENSE5_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x1)
1071 0 : #define KEYSCAN_ROWSENSE5_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x2)
1072 0 : #define KEYSCAN_ROWSENSE5_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x3)
1073 0 : #define KEYSCAN_ROWSENSE5_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x4)
1074 0 : #define KEYSCAN_ROWSENSE5_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x5)
1075 :
1076 0 : #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
1077 0 : #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
1078 0 : #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
1079 0 : #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
1080 0 : #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
1081 0 : #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
1082 0 : #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
1083 0 : #define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
1084 0 : #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
1085 0 : #define LETIMER0_OUT0_PA9 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x9)
1086 0 : #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
1087 0 : #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
1088 0 : #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
1089 0 : #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
1090 0 : #define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
1091 0 : #define LETIMER0_OUT0_PB5 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x5)
1092 0 : #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
1093 0 : #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
1094 0 : #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
1095 0 : #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
1096 0 : #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
1097 0 : #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
1098 0 : #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
1099 0 : #define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
1100 0 : #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
1101 0 : #define LETIMER0_OUT1_PA9 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x9)
1102 0 : #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
1103 0 : #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
1104 0 : #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
1105 0 : #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
1106 0 : #define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
1107 0 : #define LETIMER0_OUT1_PB5 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x5)
1108 :
1109 0 : #define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
1110 0 : #define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
1111 0 : #define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
1112 0 : #define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
1113 0 : #define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
1114 0 : #define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
1115 0 : #define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
1116 0 : #define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
1117 0 : #define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
1118 0 : #define MODEM_ANT0_PA9 SILABS_DBUS_MODEM_ANT0(0x0, 0x9)
1119 0 : #define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
1120 0 : #define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
1121 0 : #define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
1122 0 : #define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
1123 0 : #define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
1124 0 : #define MODEM_ANT0_PB5 SILABS_DBUS_MODEM_ANT0(0x1, 0x5)
1125 0 : #define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
1126 0 : #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
1127 0 : #define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
1128 0 : #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
1129 0 : #define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
1130 0 : #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
1131 0 : #define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
1132 0 : #define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
1133 0 : #define MODEM_ANT0_PC8 SILABS_DBUS_MODEM_ANT0(0x2, 0x8)
1134 0 : #define MODEM_ANT0_PC9 SILABS_DBUS_MODEM_ANT0(0x2, 0x9)
1135 0 : #define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
1136 0 : #define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
1137 0 : #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
1138 0 : #define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
1139 0 : #define MODEM_ANT0_PD4 SILABS_DBUS_MODEM_ANT0(0x3, 0x4)
1140 0 : #define MODEM_ANT0_PD5 SILABS_DBUS_MODEM_ANT0(0x3, 0x5)
1141 0 : #define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
1142 0 : #define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
1143 0 : #define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
1144 0 : #define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
1145 0 : #define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
1146 0 : #define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
1147 0 : #define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
1148 0 : #define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
1149 0 : #define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
1150 0 : #define MODEM_ANT1_PA9 SILABS_DBUS_MODEM_ANT1(0x0, 0x9)
1151 0 : #define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
1152 0 : #define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
1153 0 : #define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
1154 0 : #define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
1155 0 : #define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
1156 0 : #define MODEM_ANT1_PB5 SILABS_DBUS_MODEM_ANT1(0x1, 0x5)
1157 0 : #define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
1158 0 : #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
1159 0 : #define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
1160 0 : #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
1161 0 : #define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
1162 0 : #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
1163 0 : #define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
1164 0 : #define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
1165 0 : #define MODEM_ANT1_PC8 SILABS_DBUS_MODEM_ANT1(0x2, 0x8)
1166 0 : #define MODEM_ANT1_PC9 SILABS_DBUS_MODEM_ANT1(0x2, 0x9)
1167 0 : #define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
1168 0 : #define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
1169 0 : #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
1170 0 : #define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
1171 0 : #define MODEM_ANT1_PD4 SILABS_DBUS_MODEM_ANT1(0x3, 0x4)
1172 0 : #define MODEM_ANT1_PD5 SILABS_DBUS_MODEM_ANT1(0x3, 0x5)
1173 0 : #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
1174 0 : #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
1175 0 : #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
1176 0 : #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
1177 0 : #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
1178 0 : #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
1179 0 : #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
1180 0 : #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
1181 0 : #define MODEM_ANTROLLOVER_PC8 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x8)
1182 0 : #define MODEM_ANTROLLOVER_PC9 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x9)
1183 0 : #define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
1184 0 : #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
1185 0 : #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
1186 0 : #define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
1187 0 : #define MODEM_ANTROLLOVER_PD4 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x4)
1188 0 : #define MODEM_ANTROLLOVER_PD5 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x5)
1189 0 : #define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
1190 0 : #define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
1191 0 : #define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
1192 0 : #define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
1193 0 : #define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
1194 0 : #define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
1195 0 : #define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
1196 0 : #define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
1197 0 : #define MODEM_ANTRR0_PC8 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x8)
1198 0 : #define MODEM_ANTRR0_PC9 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x9)
1199 0 : #define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
1200 0 : #define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
1201 0 : #define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
1202 0 : #define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
1203 0 : #define MODEM_ANTRR0_PD4 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x4)
1204 0 : #define MODEM_ANTRR0_PD5 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x5)
1205 0 : #define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
1206 0 : #define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
1207 0 : #define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
1208 0 : #define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
1209 0 : #define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
1210 0 : #define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
1211 0 : #define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
1212 0 : #define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
1213 0 : #define MODEM_ANTRR1_PC8 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x8)
1214 0 : #define MODEM_ANTRR1_PC9 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x9)
1215 0 : #define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
1216 0 : #define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
1217 0 : #define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
1218 0 : #define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
1219 0 : #define MODEM_ANTRR1_PD4 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x4)
1220 0 : #define MODEM_ANTRR1_PD5 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x5)
1221 0 : #define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
1222 0 : #define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
1223 0 : #define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
1224 0 : #define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
1225 0 : #define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
1226 0 : #define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
1227 0 : #define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
1228 0 : #define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
1229 0 : #define MODEM_ANTRR2_PC8 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x8)
1230 0 : #define MODEM_ANTRR2_PC9 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x9)
1231 0 : #define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
1232 0 : #define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
1233 0 : #define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
1234 0 : #define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
1235 0 : #define MODEM_ANTRR2_PD4 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x4)
1236 0 : #define MODEM_ANTRR2_PD5 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x5)
1237 0 : #define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
1238 0 : #define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
1239 0 : #define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
1240 0 : #define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
1241 0 : #define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
1242 0 : #define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
1243 0 : #define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
1244 0 : #define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
1245 0 : #define MODEM_ANTRR3_PC8 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x8)
1246 0 : #define MODEM_ANTRR3_PC9 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x9)
1247 0 : #define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
1248 0 : #define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
1249 0 : #define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
1250 0 : #define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
1251 0 : #define MODEM_ANTRR3_PD4 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x4)
1252 0 : #define MODEM_ANTRR3_PD5 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x5)
1253 0 : #define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
1254 0 : #define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
1255 0 : #define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
1256 0 : #define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
1257 0 : #define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
1258 0 : #define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
1259 0 : #define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
1260 0 : #define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
1261 0 : #define MODEM_ANTRR4_PC8 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x8)
1262 0 : #define MODEM_ANTRR4_PC9 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x9)
1263 0 : #define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
1264 0 : #define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
1265 0 : #define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
1266 0 : #define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
1267 0 : #define MODEM_ANTRR4_PD4 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x4)
1268 0 : #define MODEM_ANTRR4_PD5 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x5)
1269 0 : #define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
1270 0 : #define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
1271 0 : #define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
1272 0 : #define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
1273 0 : #define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
1274 0 : #define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
1275 0 : #define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
1276 0 : #define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
1277 0 : #define MODEM_ANTRR5_PC8 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x8)
1278 0 : #define MODEM_ANTRR5_PC9 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x9)
1279 0 : #define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
1280 0 : #define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
1281 0 : #define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
1282 0 : #define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
1283 0 : #define MODEM_ANTRR5_PD4 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x4)
1284 0 : #define MODEM_ANTRR5_PD5 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x5)
1285 0 : #define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
1286 0 : #define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
1287 0 : #define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
1288 0 : #define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
1289 0 : #define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
1290 0 : #define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
1291 0 : #define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
1292 0 : #define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
1293 0 : #define MODEM_ANTSWEN_PC8 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x8)
1294 0 : #define MODEM_ANTSWEN_PC9 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x9)
1295 0 : #define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
1296 0 : #define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
1297 0 : #define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
1298 0 : #define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
1299 0 : #define MODEM_ANTSWEN_PD4 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x4)
1300 0 : #define MODEM_ANTSWEN_PD5 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x5)
1301 0 : #define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
1302 0 : #define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
1303 0 : #define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
1304 0 : #define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
1305 0 : #define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
1306 0 : #define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
1307 0 : #define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
1308 0 : #define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
1309 0 : #define MODEM_ANTSWUS_PC8 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x8)
1310 0 : #define MODEM_ANTSWUS_PC9 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x9)
1311 0 : #define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
1312 0 : #define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
1313 0 : #define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
1314 0 : #define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
1315 0 : #define MODEM_ANTSWUS_PD4 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x4)
1316 0 : #define MODEM_ANTSWUS_PD5 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x5)
1317 0 : #define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
1318 0 : #define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
1319 0 : #define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
1320 0 : #define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
1321 0 : #define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
1322 0 : #define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
1323 0 : #define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
1324 0 : #define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
1325 0 : #define MODEM_ANTTRIG_PC8 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x8)
1326 0 : #define MODEM_ANTTRIG_PC9 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x9)
1327 0 : #define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
1328 0 : #define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
1329 0 : #define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
1330 0 : #define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
1331 0 : #define MODEM_ANTTRIG_PD4 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x4)
1332 0 : #define MODEM_ANTTRIG_PD5 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x5)
1333 0 : #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
1334 0 : #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
1335 0 : #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
1336 0 : #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
1337 0 : #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
1338 0 : #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
1339 0 : #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
1340 0 : #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
1341 0 : #define MODEM_ANTTRIGSTOP_PC8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x8)
1342 0 : #define MODEM_ANTTRIGSTOP_PC9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x9)
1343 0 : #define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
1344 0 : #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
1345 0 : #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
1346 0 : #define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
1347 0 : #define MODEM_ANTTRIGSTOP_PD4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x4)
1348 0 : #define MODEM_ANTTRIGSTOP_PD5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x5)
1349 0 : #define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
1350 0 : #define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
1351 0 : #define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
1352 0 : #define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
1353 0 : #define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
1354 0 : #define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
1355 0 : #define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
1356 0 : #define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
1357 0 : #define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
1358 0 : #define MODEM_DCLK_PA9 SILABS_DBUS_MODEM_DCLK(0x0, 0x9)
1359 0 : #define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
1360 0 : #define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
1361 0 : #define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
1362 0 : #define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
1363 0 : #define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
1364 0 : #define MODEM_DCLK_PB5 SILABS_DBUS_MODEM_DCLK(0x1, 0x5)
1365 0 : #define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
1366 0 : #define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
1367 0 : #define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
1368 0 : #define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
1369 0 : #define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
1370 0 : #define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
1371 0 : #define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
1372 0 : #define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
1373 0 : #define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
1374 0 : #define MODEM_DOUT_PA9 SILABS_DBUS_MODEM_DOUT(0x0, 0x9)
1375 0 : #define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
1376 0 : #define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
1377 0 : #define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
1378 0 : #define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
1379 0 : #define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
1380 0 : #define MODEM_DOUT_PB5 SILABS_DBUS_MODEM_DOUT(0x1, 0x5)
1381 0 : #define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0)
1382 0 : #define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1)
1383 0 : #define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2)
1384 0 : #define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3)
1385 0 : #define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4)
1386 0 : #define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5)
1387 0 : #define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6)
1388 0 : #define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7)
1389 0 : #define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8)
1390 0 : #define MODEM_DIN_PA9 SILABS_DBUS_MODEM_DIN(0x0, 0x9)
1391 0 : #define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0)
1392 0 : #define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1)
1393 0 : #define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2)
1394 0 : #define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3)
1395 0 : #define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4)
1396 0 : #define MODEM_DIN_PB5 SILABS_DBUS_MODEM_DIN(0x1, 0x5)
1397 :
1398 0 : #define PCNT0_S0IN_PA0 SILABS_DBUS_PCNT0_S0IN(0x0, 0x0)
1399 0 : #define PCNT0_S0IN_PA1 SILABS_DBUS_PCNT0_S0IN(0x0, 0x1)
1400 0 : #define PCNT0_S0IN_PA2 SILABS_DBUS_PCNT0_S0IN(0x0, 0x2)
1401 0 : #define PCNT0_S0IN_PA3 SILABS_DBUS_PCNT0_S0IN(0x0, 0x3)
1402 0 : #define PCNT0_S0IN_PA4 SILABS_DBUS_PCNT0_S0IN(0x0, 0x4)
1403 0 : #define PCNT0_S0IN_PA5 SILABS_DBUS_PCNT0_S0IN(0x0, 0x5)
1404 0 : #define PCNT0_S0IN_PA6 SILABS_DBUS_PCNT0_S0IN(0x0, 0x6)
1405 0 : #define PCNT0_S0IN_PA7 SILABS_DBUS_PCNT0_S0IN(0x0, 0x7)
1406 0 : #define PCNT0_S0IN_PA8 SILABS_DBUS_PCNT0_S0IN(0x0, 0x8)
1407 0 : #define PCNT0_S0IN_PA9 SILABS_DBUS_PCNT0_S0IN(0x0, 0x9)
1408 0 : #define PCNT0_S0IN_PB0 SILABS_DBUS_PCNT0_S0IN(0x1, 0x0)
1409 0 : #define PCNT0_S0IN_PB1 SILABS_DBUS_PCNT0_S0IN(0x1, 0x1)
1410 0 : #define PCNT0_S0IN_PB2 SILABS_DBUS_PCNT0_S0IN(0x1, 0x2)
1411 0 : #define PCNT0_S0IN_PB3 SILABS_DBUS_PCNT0_S0IN(0x1, 0x3)
1412 0 : #define PCNT0_S0IN_PB4 SILABS_DBUS_PCNT0_S0IN(0x1, 0x4)
1413 0 : #define PCNT0_S0IN_PB5 SILABS_DBUS_PCNT0_S0IN(0x1, 0x5)
1414 0 : #define PCNT0_S1IN_PA0 SILABS_DBUS_PCNT0_S1IN(0x0, 0x0)
1415 0 : #define PCNT0_S1IN_PA1 SILABS_DBUS_PCNT0_S1IN(0x0, 0x1)
1416 0 : #define PCNT0_S1IN_PA2 SILABS_DBUS_PCNT0_S1IN(0x0, 0x2)
1417 0 : #define PCNT0_S1IN_PA3 SILABS_DBUS_PCNT0_S1IN(0x0, 0x3)
1418 0 : #define PCNT0_S1IN_PA4 SILABS_DBUS_PCNT0_S1IN(0x0, 0x4)
1419 0 : #define PCNT0_S1IN_PA5 SILABS_DBUS_PCNT0_S1IN(0x0, 0x5)
1420 0 : #define PCNT0_S1IN_PA6 SILABS_DBUS_PCNT0_S1IN(0x0, 0x6)
1421 0 : #define PCNT0_S1IN_PA7 SILABS_DBUS_PCNT0_S1IN(0x0, 0x7)
1422 0 : #define PCNT0_S1IN_PA8 SILABS_DBUS_PCNT0_S1IN(0x0, 0x8)
1423 0 : #define PCNT0_S1IN_PA9 SILABS_DBUS_PCNT0_S1IN(0x0, 0x9)
1424 0 : #define PCNT0_S1IN_PB0 SILABS_DBUS_PCNT0_S1IN(0x1, 0x0)
1425 0 : #define PCNT0_S1IN_PB1 SILABS_DBUS_PCNT0_S1IN(0x1, 0x1)
1426 0 : #define PCNT0_S1IN_PB2 SILABS_DBUS_PCNT0_S1IN(0x1, 0x2)
1427 0 : #define PCNT0_S1IN_PB3 SILABS_DBUS_PCNT0_S1IN(0x1, 0x3)
1428 0 : #define PCNT0_S1IN_PB4 SILABS_DBUS_PCNT0_S1IN(0x1, 0x4)
1429 0 : #define PCNT0_S1IN_PB5 SILABS_DBUS_PCNT0_S1IN(0x1, 0x5)
1430 :
1431 0 : #define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
1432 0 : #define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
1433 0 : #define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
1434 0 : #define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
1435 0 : #define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
1436 0 : #define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
1437 0 : #define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
1438 0 : #define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
1439 0 : #define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
1440 0 : #define PRS0_ASYNCH0_PA9 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x9)
1441 0 : #define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
1442 0 : #define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
1443 0 : #define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
1444 0 : #define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
1445 0 : #define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
1446 0 : #define PRS0_ASYNCH0_PB5 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x5)
1447 0 : #define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
1448 0 : #define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
1449 0 : #define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
1450 0 : #define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
1451 0 : #define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
1452 0 : #define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
1453 0 : #define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
1454 0 : #define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
1455 0 : #define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
1456 0 : #define PRS0_ASYNCH1_PA9 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x9)
1457 0 : #define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
1458 0 : #define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
1459 0 : #define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
1460 0 : #define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
1461 0 : #define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
1462 0 : #define PRS0_ASYNCH1_PB5 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x5)
1463 0 : #define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
1464 0 : #define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
1465 0 : #define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
1466 0 : #define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
1467 0 : #define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
1468 0 : #define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
1469 0 : #define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
1470 0 : #define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
1471 0 : #define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
1472 0 : #define PRS0_ASYNCH2_PA9 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x9)
1473 0 : #define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
1474 0 : #define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
1475 0 : #define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
1476 0 : #define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
1477 0 : #define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
1478 0 : #define PRS0_ASYNCH2_PB5 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x5)
1479 0 : #define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
1480 0 : #define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
1481 0 : #define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
1482 0 : #define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
1483 0 : #define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
1484 0 : #define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
1485 0 : #define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
1486 0 : #define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
1487 0 : #define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
1488 0 : #define PRS0_ASYNCH3_PA9 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x9)
1489 0 : #define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
1490 0 : #define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
1491 0 : #define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
1492 0 : #define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
1493 0 : #define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
1494 0 : #define PRS0_ASYNCH3_PB5 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x5)
1495 0 : #define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
1496 0 : #define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
1497 0 : #define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
1498 0 : #define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
1499 0 : #define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
1500 0 : #define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
1501 0 : #define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
1502 0 : #define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
1503 0 : #define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
1504 0 : #define PRS0_ASYNCH4_PA9 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x9)
1505 0 : #define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
1506 0 : #define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
1507 0 : #define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
1508 0 : #define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
1509 0 : #define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
1510 0 : #define PRS0_ASYNCH4_PB5 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x5)
1511 0 : #define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
1512 0 : #define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
1513 0 : #define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
1514 0 : #define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
1515 0 : #define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
1516 0 : #define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
1517 0 : #define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
1518 0 : #define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
1519 0 : #define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
1520 0 : #define PRS0_ASYNCH5_PA9 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x9)
1521 0 : #define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
1522 0 : #define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
1523 0 : #define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
1524 0 : #define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
1525 0 : #define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
1526 0 : #define PRS0_ASYNCH5_PB5 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x5)
1527 0 : #define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
1528 0 : #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
1529 0 : #define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
1530 0 : #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
1531 0 : #define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
1532 0 : #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
1533 0 : #define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
1534 0 : #define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
1535 0 : #define PRS0_ASYNCH6_PC8 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x8)
1536 0 : #define PRS0_ASYNCH6_PC9 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x9)
1537 0 : #define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
1538 0 : #define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
1539 0 : #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
1540 0 : #define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
1541 0 : #define PRS0_ASYNCH6_PD4 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x4)
1542 0 : #define PRS0_ASYNCH6_PD5 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x5)
1543 0 : #define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
1544 0 : #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
1545 0 : #define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
1546 0 : #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
1547 0 : #define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
1548 0 : #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
1549 0 : #define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
1550 0 : #define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
1551 0 : #define PRS0_ASYNCH7_PC8 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x8)
1552 0 : #define PRS0_ASYNCH7_PC9 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x9)
1553 0 : #define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
1554 0 : #define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
1555 0 : #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
1556 0 : #define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
1557 0 : #define PRS0_ASYNCH7_PD4 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x4)
1558 0 : #define PRS0_ASYNCH7_PD5 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x5)
1559 0 : #define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
1560 0 : #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
1561 0 : #define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
1562 0 : #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
1563 0 : #define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
1564 0 : #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
1565 0 : #define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
1566 0 : #define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
1567 0 : #define PRS0_ASYNCH8_PC8 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x8)
1568 0 : #define PRS0_ASYNCH8_PC9 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x9)
1569 0 : #define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
1570 0 : #define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
1571 0 : #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
1572 0 : #define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
1573 0 : #define PRS0_ASYNCH8_PD4 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x4)
1574 0 : #define PRS0_ASYNCH8_PD5 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x5)
1575 0 : #define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
1576 0 : #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
1577 0 : #define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
1578 0 : #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
1579 0 : #define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
1580 0 : #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
1581 0 : #define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
1582 0 : #define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
1583 0 : #define PRS0_ASYNCH9_PC8 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x8)
1584 0 : #define PRS0_ASYNCH9_PC9 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x9)
1585 0 : #define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
1586 0 : #define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
1587 0 : #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
1588 0 : #define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
1589 0 : #define PRS0_ASYNCH9_PD4 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x4)
1590 0 : #define PRS0_ASYNCH9_PD5 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x5)
1591 0 : #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
1592 0 : #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
1593 0 : #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
1594 0 : #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
1595 0 : #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
1596 0 : #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
1597 0 : #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
1598 0 : #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
1599 0 : #define PRS0_ASYNCH10_PC8 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x8)
1600 0 : #define PRS0_ASYNCH10_PC9 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x9)
1601 0 : #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
1602 0 : #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
1603 0 : #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
1604 0 : #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
1605 0 : #define PRS0_ASYNCH10_PD4 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x4)
1606 0 : #define PRS0_ASYNCH10_PD5 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x5)
1607 0 : #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
1608 0 : #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
1609 0 : #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
1610 0 : #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
1611 0 : #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
1612 0 : #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
1613 0 : #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
1614 0 : #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
1615 0 : #define PRS0_ASYNCH11_PC8 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x8)
1616 0 : #define PRS0_ASYNCH11_PC9 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x9)
1617 0 : #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
1618 0 : #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
1619 0 : #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
1620 0 : #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
1621 0 : #define PRS0_ASYNCH11_PD4 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x4)
1622 0 : #define PRS0_ASYNCH11_PD5 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x5)
1623 0 : #define PRS0_ASYNCH12_PA0 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x0)
1624 0 : #define PRS0_ASYNCH12_PA1 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x1)
1625 0 : #define PRS0_ASYNCH12_PA2 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x2)
1626 0 : #define PRS0_ASYNCH12_PA3 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x3)
1627 0 : #define PRS0_ASYNCH12_PA4 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x4)
1628 0 : #define PRS0_ASYNCH12_PA5 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x5)
1629 0 : #define PRS0_ASYNCH12_PA6 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x6)
1630 0 : #define PRS0_ASYNCH12_PA7 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x7)
1631 0 : #define PRS0_ASYNCH12_PA8 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x8)
1632 0 : #define PRS0_ASYNCH12_PA9 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x9)
1633 0 : #define PRS0_ASYNCH12_PB0 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x0)
1634 0 : #define PRS0_ASYNCH12_PB1 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x1)
1635 0 : #define PRS0_ASYNCH12_PB2 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x2)
1636 0 : #define PRS0_ASYNCH12_PB3 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x3)
1637 0 : #define PRS0_ASYNCH12_PB4 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x4)
1638 0 : #define PRS0_ASYNCH12_PB5 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x5)
1639 0 : #define PRS0_ASYNCH13_PA0 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x0)
1640 0 : #define PRS0_ASYNCH13_PA1 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x1)
1641 0 : #define PRS0_ASYNCH13_PA2 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x2)
1642 0 : #define PRS0_ASYNCH13_PA3 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x3)
1643 0 : #define PRS0_ASYNCH13_PA4 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x4)
1644 0 : #define PRS0_ASYNCH13_PA5 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x5)
1645 0 : #define PRS0_ASYNCH13_PA6 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x6)
1646 0 : #define PRS0_ASYNCH13_PA7 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x7)
1647 0 : #define PRS0_ASYNCH13_PA8 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x8)
1648 0 : #define PRS0_ASYNCH13_PA9 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x9)
1649 0 : #define PRS0_ASYNCH13_PB0 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x0)
1650 0 : #define PRS0_ASYNCH13_PB1 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x1)
1651 0 : #define PRS0_ASYNCH13_PB2 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x2)
1652 0 : #define PRS0_ASYNCH13_PB3 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x3)
1653 0 : #define PRS0_ASYNCH13_PB4 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x4)
1654 0 : #define PRS0_ASYNCH13_PB5 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x5)
1655 0 : #define PRS0_ASYNCH14_PA0 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x0)
1656 0 : #define PRS0_ASYNCH14_PA1 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x1)
1657 0 : #define PRS0_ASYNCH14_PA2 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x2)
1658 0 : #define PRS0_ASYNCH14_PA3 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x3)
1659 0 : #define PRS0_ASYNCH14_PA4 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x4)
1660 0 : #define PRS0_ASYNCH14_PA5 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x5)
1661 0 : #define PRS0_ASYNCH14_PA6 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x6)
1662 0 : #define PRS0_ASYNCH14_PA7 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x7)
1663 0 : #define PRS0_ASYNCH14_PA8 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x8)
1664 0 : #define PRS0_ASYNCH14_PA9 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x9)
1665 0 : #define PRS0_ASYNCH14_PB0 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x0)
1666 0 : #define PRS0_ASYNCH14_PB1 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x1)
1667 0 : #define PRS0_ASYNCH14_PB2 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x2)
1668 0 : #define PRS0_ASYNCH14_PB3 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x3)
1669 0 : #define PRS0_ASYNCH14_PB4 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x4)
1670 0 : #define PRS0_ASYNCH14_PB5 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x5)
1671 0 : #define PRS0_ASYNCH15_PA0 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x0)
1672 0 : #define PRS0_ASYNCH15_PA1 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x1)
1673 0 : #define PRS0_ASYNCH15_PA2 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x2)
1674 0 : #define PRS0_ASYNCH15_PA3 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x3)
1675 0 : #define PRS0_ASYNCH15_PA4 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x4)
1676 0 : #define PRS0_ASYNCH15_PA5 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x5)
1677 0 : #define PRS0_ASYNCH15_PA6 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x6)
1678 0 : #define PRS0_ASYNCH15_PA7 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x7)
1679 0 : #define PRS0_ASYNCH15_PA8 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x8)
1680 0 : #define PRS0_ASYNCH15_PA9 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x9)
1681 0 : #define PRS0_ASYNCH15_PB0 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x0)
1682 0 : #define PRS0_ASYNCH15_PB1 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x1)
1683 0 : #define PRS0_ASYNCH15_PB2 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x2)
1684 0 : #define PRS0_ASYNCH15_PB3 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x3)
1685 0 : #define PRS0_ASYNCH15_PB4 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x4)
1686 0 : #define PRS0_ASYNCH15_PB5 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x5)
1687 0 : #define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
1688 0 : #define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
1689 0 : #define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
1690 0 : #define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
1691 0 : #define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
1692 0 : #define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
1693 0 : #define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
1694 0 : #define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
1695 0 : #define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
1696 0 : #define PRS0_SYNCH0_PA9 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x9)
1697 0 : #define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
1698 0 : #define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
1699 0 : #define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
1700 0 : #define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
1701 0 : #define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
1702 0 : #define PRS0_SYNCH0_PB5 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x5)
1703 0 : #define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
1704 0 : #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
1705 0 : #define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
1706 0 : #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
1707 0 : #define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
1708 0 : #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
1709 0 : #define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
1710 0 : #define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
1711 0 : #define PRS0_SYNCH0_PC8 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x8)
1712 0 : #define PRS0_SYNCH0_PC9 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x9)
1713 0 : #define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
1714 0 : #define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
1715 0 : #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
1716 0 : #define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
1717 0 : #define PRS0_SYNCH0_PD4 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x4)
1718 0 : #define PRS0_SYNCH0_PD5 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x5)
1719 0 : #define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
1720 0 : #define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
1721 0 : #define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
1722 0 : #define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
1723 0 : #define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
1724 0 : #define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
1725 0 : #define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
1726 0 : #define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
1727 0 : #define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
1728 0 : #define PRS0_SYNCH1_PA9 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x9)
1729 0 : #define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
1730 0 : #define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
1731 0 : #define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
1732 0 : #define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
1733 0 : #define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
1734 0 : #define PRS0_SYNCH1_PB5 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x5)
1735 0 : #define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
1736 0 : #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
1737 0 : #define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
1738 0 : #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
1739 0 : #define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
1740 0 : #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
1741 0 : #define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
1742 0 : #define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
1743 0 : #define PRS0_SYNCH1_PC8 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x8)
1744 0 : #define PRS0_SYNCH1_PC9 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x9)
1745 0 : #define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
1746 0 : #define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
1747 0 : #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
1748 0 : #define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
1749 0 : #define PRS0_SYNCH1_PD4 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x4)
1750 0 : #define PRS0_SYNCH1_PD5 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x5)
1751 0 : #define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
1752 0 : #define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
1753 0 : #define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
1754 0 : #define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
1755 0 : #define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
1756 0 : #define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
1757 0 : #define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
1758 0 : #define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
1759 0 : #define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
1760 0 : #define PRS0_SYNCH2_PA9 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x9)
1761 0 : #define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
1762 0 : #define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
1763 0 : #define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
1764 0 : #define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
1765 0 : #define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
1766 0 : #define PRS0_SYNCH2_PB5 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x5)
1767 0 : #define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
1768 0 : #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
1769 0 : #define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
1770 0 : #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
1771 0 : #define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
1772 0 : #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
1773 0 : #define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
1774 0 : #define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
1775 0 : #define PRS0_SYNCH2_PC8 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x8)
1776 0 : #define PRS0_SYNCH2_PC9 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x9)
1777 0 : #define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
1778 0 : #define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
1779 0 : #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
1780 0 : #define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
1781 0 : #define PRS0_SYNCH2_PD4 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x4)
1782 0 : #define PRS0_SYNCH2_PD5 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x5)
1783 0 : #define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
1784 0 : #define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
1785 0 : #define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
1786 0 : #define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
1787 0 : #define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
1788 0 : #define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
1789 0 : #define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
1790 0 : #define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
1791 0 : #define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
1792 0 : #define PRS0_SYNCH3_PA9 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x9)
1793 0 : #define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
1794 0 : #define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
1795 0 : #define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
1796 0 : #define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
1797 0 : #define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
1798 0 : #define PRS0_SYNCH3_PB5 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x5)
1799 0 : #define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
1800 0 : #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
1801 0 : #define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
1802 0 : #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
1803 0 : #define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
1804 0 : #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
1805 0 : #define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
1806 0 : #define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
1807 0 : #define PRS0_SYNCH3_PC8 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x8)
1808 0 : #define PRS0_SYNCH3_PC9 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x9)
1809 0 : #define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
1810 0 : #define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
1811 0 : #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
1812 0 : #define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
1813 0 : #define PRS0_SYNCH3_PD4 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x4)
1814 0 : #define PRS0_SYNCH3_PD5 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x5)
1815 :
1816 0 : #define HFXO0_BUFOUTREQINASYNC_PA0 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x0)
1817 0 : #define HFXO0_BUFOUTREQINASYNC_PA1 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x1)
1818 0 : #define HFXO0_BUFOUTREQINASYNC_PA2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x2)
1819 0 : #define HFXO0_BUFOUTREQINASYNC_PA3 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x3)
1820 0 : #define HFXO0_BUFOUTREQINASYNC_PA4 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x4)
1821 0 : #define HFXO0_BUFOUTREQINASYNC_PA5 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x5)
1822 0 : #define HFXO0_BUFOUTREQINASYNC_PA6 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x6)
1823 0 : #define HFXO0_BUFOUTREQINASYNC_PA7 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x7)
1824 0 : #define HFXO0_BUFOUTREQINASYNC_PA8 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x8)
1825 0 : #define HFXO0_BUFOUTREQINASYNC_PA9 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x9)
1826 0 : #define HFXO0_BUFOUTREQINASYNC_PB0 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x0)
1827 0 : #define HFXO0_BUFOUTREQINASYNC_PB1 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x1)
1828 0 : #define HFXO0_BUFOUTREQINASYNC_PB2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x2)
1829 0 : #define HFXO0_BUFOUTREQINASYNC_PB3 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x3)
1830 0 : #define HFXO0_BUFOUTREQINASYNC_PB4 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x4)
1831 0 : #define HFXO0_BUFOUTREQINASYNC_PB5 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x5)
1832 :
1833 0 : #define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
1834 0 : #define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
1835 0 : #define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
1836 0 : #define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
1837 0 : #define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
1838 0 : #define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
1839 0 : #define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
1840 0 : #define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
1841 0 : #define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
1842 0 : #define TIMER0_CC0_PA9 SILABS_DBUS_TIMER0_CC0(0x0, 0x9)
1843 0 : #define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
1844 0 : #define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
1845 0 : #define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
1846 0 : #define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
1847 0 : #define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
1848 0 : #define TIMER0_CC0_PB5 SILABS_DBUS_TIMER0_CC0(0x1, 0x5)
1849 0 : #define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
1850 0 : #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
1851 0 : #define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
1852 0 : #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
1853 0 : #define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
1854 0 : #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
1855 0 : #define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
1856 0 : #define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
1857 0 : #define TIMER0_CC0_PC8 SILABS_DBUS_TIMER0_CC0(0x2, 0x8)
1858 0 : #define TIMER0_CC0_PC9 SILABS_DBUS_TIMER0_CC0(0x2, 0x9)
1859 0 : #define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
1860 0 : #define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
1861 0 : #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
1862 0 : #define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
1863 0 : #define TIMER0_CC0_PD4 SILABS_DBUS_TIMER0_CC0(0x3, 0x4)
1864 0 : #define TIMER0_CC0_PD5 SILABS_DBUS_TIMER0_CC0(0x3, 0x5)
1865 0 : #define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
1866 0 : #define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
1867 0 : #define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
1868 0 : #define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
1869 0 : #define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
1870 0 : #define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
1871 0 : #define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
1872 0 : #define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
1873 0 : #define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
1874 0 : #define TIMER0_CC1_PA9 SILABS_DBUS_TIMER0_CC1(0x0, 0x9)
1875 0 : #define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
1876 0 : #define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
1877 0 : #define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
1878 0 : #define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
1879 0 : #define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
1880 0 : #define TIMER0_CC1_PB5 SILABS_DBUS_TIMER0_CC1(0x1, 0x5)
1881 0 : #define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
1882 0 : #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
1883 0 : #define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
1884 0 : #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
1885 0 : #define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
1886 0 : #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
1887 0 : #define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
1888 0 : #define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
1889 0 : #define TIMER0_CC1_PC8 SILABS_DBUS_TIMER0_CC1(0x2, 0x8)
1890 0 : #define TIMER0_CC1_PC9 SILABS_DBUS_TIMER0_CC1(0x2, 0x9)
1891 0 : #define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
1892 0 : #define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
1893 0 : #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
1894 0 : #define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
1895 0 : #define TIMER0_CC1_PD4 SILABS_DBUS_TIMER0_CC1(0x3, 0x4)
1896 0 : #define TIMER0_CC1_PD5 SILABS_DBUS_TIMER0_CC1(0x3, 0x5)
1897 0 : #define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
1898 0 : #define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
1899 0 : #define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
1900 0 : #define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
1901 0 : #define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
1902 0 : #define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
1903 0 : #define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
1904 0 : #define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
1905 0 : #define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
1906 0 : #define TIMER0_CC2_PA9 SILABS_DBUS_TIMER0_CC2(0x0, 0x9)
1907 0 : #define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
1908 0 : #define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
1909 0 : #define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
1910 0 : #define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
1911 0 : #define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
1912 0 : #define TIMER0_CC2_PB5 SILABS_DBUS_TIMER0_CC2(0x1, 0x5)
1913 0 : #define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
1914 0 : #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
1915 0 : #define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
1916 0 : #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
1917 0 : #define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
1918 0 : #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
1919 0 : #define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
1920 0 : #define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
1921 0 : #define TIMER0_CC2_PC8 SILABS_DBUS_TIMER0_CC2(0x2, 0x8)
1922 0 : #define TIMER0_CC2_PC9 SILABS_DBUS_TIMER0_CC2(0x2, 0x9)
1923 0 : #define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
1924 0 : #define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
1925 0 : #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
1926 0 : #define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
1927 0 : #define TIMER0_CC2_PD4 SILABS_DBUS_TIMER0_CC2(0x3, 0x4)
1928 0 : #define TIMER0_CC2_PD5 SILABS_DBUS_TIMER0_CC2(0x3, 0x5)
1929 0 : #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
1930 0 : #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
1931 0 : #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
1932 0 : #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
1933 0 : #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
1934 0 : #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
1935 0 : #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
1936 0 : #define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
1937 0 : #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
1938 0 : #define TIMER0_CDTI0_PA9 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x9)
1939 0 : #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
1940 0 : #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
1941 0 : #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
1942 0 : #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
1943 0 : #define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
1944 0 : #define TIMER0_CDTI0_PB5 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x5)
1945 0 : #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
1946 0 : #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
1947 0 : #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
1948 0 : #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
1949 0 : #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
1950 0 : #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
1951 0 : #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
1952 0 : #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
1953 0 : #define TIMER0_CDTI0_PC8 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x8)
1954 0 : #define TIMER0_CDTI0_PC9 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x9)
1955 0 : #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
1956 0 : #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
1957 0 : #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
1958 0 : #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
1959 0 : #define TIMER0_CDTI0_PD4 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x4)
1960 0 : #define TIMER0_CDTI0_PD5 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x5)
1961 0 : #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
1962 0 : #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
1963 0 : #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
1964 0 : #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
1965 0 : #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
1966 0 : #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
1967 0 : #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
1968 0 : #define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
1969 0 : #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
1970 0 : #define TIMER0_CDTI1_PA9 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x9)
1971 0 : #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
1972 0 : #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
1973 0 : #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
1974 0 : #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
1975 0 : #define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
1976 0 : #define TIMER0_CDTI1_PB5 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x5)
1977 0 : #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
1978 0 : #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
1979 0 : #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
1980 0 : #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
1981 0 : #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
1982 0 : #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
1983 0 : #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
1984 0 : #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
1985 0 : #define TIMER0_CDTI1_PC8 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x8)
1986 0 : #define TIMER0_CDTI1_PC9 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x9)
1987 0 : #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
1988 0 : #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
1989 0 : #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
1990 0 : #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
1991 0 : #define TIMER0_CDTI1_PD4 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x4)
1992 0 : #define TIMER0_CDTI1_PD5 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x5)
1993 0 : #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
1994 0 : #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
1995 0 : #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
1996 0 : #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
1997 0 : #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
1998 0 : #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
1999 0 : #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
2000 0 : #define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
2001 0 : #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
2002 0 : #define TIMER0_CDTI2_PA9 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x9)
2003 0 : #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
2004 0 : #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
2005 0 : #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
2006 0 : #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
2007 0 : #define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
2008 0 : #define TIMER0_CDTI2_PB5 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x5)
2009 0 : #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
2010 0 : #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
2011 0 : #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
2012 0 : #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
2013 0 : #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
2014 0 : #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
2015 0 : #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
2016 0 : #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
2017 0 : #define TIMER0_CDTI2_PC8 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x8)
2018 0 : #define TIMER0_CDTI2_PC9 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x9)
2019 0 : #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
2020 0 : #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
2021 0 : #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
2022 0 : #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
2023 0 : #define TIMER0_CDTI2_PD4 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x4)
2024 0 : #define TIMER0_CDTI2_PD5 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x5)
2025 :
2026 0 : #define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
2027 0 : #define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
2028 0 : #define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
2029 0 : #define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
2030 0 : #define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
2031 0 : #define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
2032 0 : #define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
2033 0 : #define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
2034 0 : #define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
2035 0 : #define TIMER1_CC0_PA9 SILABS_DBUS_TIMER1_CC0(0x0, 0x9)
2036 0 : #define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
2037 0 : #define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
2038 0 : #define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
2039 0 : #define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
2040 0 : #define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
2041 0 : #define TIMER1_CC0_PB5 SILABS_DBUS_TIMER1_CC0(0x1, 0x5)
2042 0 : #define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
2043 0 : #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
2044 0 : #define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
2045 0 : #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
2046 0 : #define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
2047 0 : #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
2048 0 : #define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
2049 0 : #define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
2050 0 : #define TIMER1_CC0_PC8 SILABS_DBUS_TIMER1_CC0(0x2, 0x8)
2051 0 : #define TIMER1_CC0_PC9 SILABS_DBUS_TIMER1_CC0(0x2, 0x9)
2052 0 : #define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
2053 0 : #define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
2054 0 : #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
2055 0 : #define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
2056 0 : #define TIMER1_CC0_PD4 SILABS_DBUS_TIMER1_CC0(0x3, 0x4)
2057 0 : #define TIMER1_CC0_PD5 SILABS_DBUS_TIMER1_CC0(0x3, 0x5)
2058 0 : #define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
2059 0 : #define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
2060 0 : #define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
2061 0 : #define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
2062 0 : #define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
2063 0 : #define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
2064 0 : #define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
2065 0 : #define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
2066 0 : #define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
2067 0 : #define TIMER1_CC1_PA9 SILABS_DBUS_TIMER1_CC1(0x0, 0x9)
2068 0 : #define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
2069 0 : #define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
2070 0 : #define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
2071 0 : #define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
2072 0 : #define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
2073 0 : #define TIMER1_CC1_PB5 SILABS_DBUS_TIMER1_CC1(0x1, 0x5)
2074 0 : #define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
2075 0 : #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
2076 0 : #define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
2077 0 : #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
2078 0 : #define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
2079 0 : #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
2080 0 : #define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
2081 0 : #define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
2082 0 : #define TIMER1_CC1_PC8 SILABS_DBUS_TIMER1_CC1(0x2, 0x8)
2083 0 : #define TIMER1_CC1_PC9 SILABS_DBUS_TIMER1_CC1(0x2, 0x9)
2084 0 : #define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
2085 0 : #define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
2086 0 : #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
2087 0 : #define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
2088 0 : #define TIMER1_CC1_PD4 SILABS_DBUS_TIMER1_CC1(0x3, 0x4)
2089 0 : #define TIMER1_CC1_PD5 SILABS_DBUS_TIMER1_CC1(0x3, 0x5)
2090 0 : #define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
2091 0 : #define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
2092 0 : #define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
2093 0 : #define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
2094 0 : #define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
2095 0 : #define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
2096 0 : #define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
2097 0 : #define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
2098 0 : #define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
2099 0 : #define TIMER1_CC2_PA9 SILABS_DBUS_TIMER1_CC2(0x0, 0x9)
2100 0 : #define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
2101 0 : #define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
2102 0 : #define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
2103 0 : #define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
2104 0 : #define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
2105 0 : #define TIMER1_CC2_PB5 SILABS_DBUS_TIMER1_CC2(0x1, 0x5)
2106 0 : #define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
2107 0 : #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
2108 0 : #define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
2109 0 : #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
2110 0 : #define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
2111 0 : #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
2112 0 : #define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
2113 0 : #define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
2114 0 : #define TIMER1_CC2_PC8 SILABS_DBUS_TIMER1_CC2(0x2, 0x8)
2115 0 : #define TIMER1_CC2_PC9 SILABS_DBUS_TIMER1_CC2(0x2, 0x9)
2116 0 : #define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
2117 0 : #define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
2118 0 : #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
2119 0 : #define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
2120 0 : #define TIMER1_CC2_PD4 SILABS_DBUS_TIMER1_CC2(0x3, 0x4)
2121 0 : #define TIMER1_CC2_PD5 SILABS_DBUS_TIMER1_CC2(0x3, 0x5)
2122 0 : #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
2123 0 : #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
2124 0 : #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
2125 0 : #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
2126 0 : #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
2127 0 : #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
2128 0 : #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
2129 0 : #define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
2130 0 : #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
2131 0 : #define TIMER1_CDTI0_PA9 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x9)
2132 0 : #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
2133 0 : #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
2134 0 : #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
2135 0 : #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
2136 0 : #define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
2137 0 : #define TIMER1_CDTI0_PB5 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x5)
2138 0 : #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
2139 0 : #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
2140 0 : #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
2141 0 : #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
2142 0 : #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
2143 0 : #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
2144 0 : #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
2145 0 : #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
2146 0 : #define TIMER1_CDTI0_PC8 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x8)
2147 0 : #define TIMER1_CDTI0_PC9 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x9)
2148 0 : #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
2149 0 : #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
2150 0 : #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
2151 0 : #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
2152 0 : #define TIMER1_CDTI0_PD4 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x4)
2153 0 : #define TIMER1_CDTI0_PD5 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x5)
2154 0 : #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
2155 0 : #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
2156 0 : #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
2157 0 : #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
2158 0 : #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
2159 0 : #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
2160 0 : #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
2161 0 : #define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
2162 0 : #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
2163 0 : #define TIMER1_CDTI1_PA9 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x9)
2164 0 : #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
2165 0 : #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
2166 0 : #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
2167 0 : #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
2168 0 : #define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
2169 0 : #define TIMER1_CDTI1_PB5 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x5)
2170 0 : #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
2171 0 : #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
2172 0 : #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
2173 0 : #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
2174 0 : #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
2175 0 : #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
2176 0 : #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
2177 0 : #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
2178 0 : #define TIMER1_CDTI1_PC8 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x8)
2179 0 : #define TIMER1_CDTI1_PC9 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x9)
2180 0 : #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
2181 0 : #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
2182 0 : #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
2183 0 : #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
2184 0 : #define TIMER1_CDTI1_PD4 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x4)
2185 0 : #define TIMER1_CDTI1_PD5 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x5)
2186 0 : #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
2187 0 : #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
2188 0 : #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
2189 0 : #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
2190 0 : #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
2191 0 : #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
2192 0 : #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
2193 0 : #define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
2194 0 : #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
2195 0 : #define TIMER1_CDTI2_PA9 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x9)
2196 0 : #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
2197 0 : #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
2198 0 : #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
2199 0 : #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
2200 0 : #define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
2201 0 : #define TIMER1_CDTI2_PB5 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x5)
2202 0 : #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
2203 0 : #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
2204 0 : #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
2205 0 : #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
2206 0 : #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
2207 0 : #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
2208 0 : #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
2209 0 : #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
2210 0 : #define TIMER1_CDTI2_PC8 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x8)
2211 0 : #define TIMER1_CDTI2_PC9 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x9)
2212 0 : #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
2213 0 : #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
2214 0 : #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
2215 0 : #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
2216 0 : #define TIMER1_CDTI2_PD4 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x4)
2217 0 : #define TIMER1_CDTI2_PD5 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x5)
2218 :
2219 0 : #define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
2220 0 : #define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
2221 0 : #define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
2222 0 : #define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
2223 0 : #define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
2224 0 : #define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
2225 0 : #define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
2226 0 : #define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
2227 0 : #define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
2228 0 : #define TIMER2_CC0_PA9 SILABS_DBUS_TIMER2_CC0(0x0, 0x9)
2229 0 : #define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
2230 0 : #define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
2231 0 : #define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
2232 0 : #define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
2233 0 : #define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
2234 0 : #define TIMER2_CC0_PB5 SILABS_DBUS_TIMER2_CC0(0x1, 0x5)
2235 0 : #define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
2236 0 : #define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
2237 0 : #define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
2238 0 : #define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
2239 0 : #define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
2240 0 : #define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
2241 0 : #define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
2242 0 : #define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
2243 0 : #define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
2244 0 : #define TIMER2_CC1_PA9 SILABS_DBUS_TIMER2_CC1(0x0, 0x9)
2245 0 : #define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
2246 0 : #define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
2247 0 : #define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
2248 0 : #define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
2249 0 : #define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
2250 0 : #define TIMER2_CC1_PB5 SILABS_DBUS_TIMER2_CC1(0x1, 0x5)
2251 0 : #define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
2252 0 : #define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
2253 0 : #define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
2254 0 : #define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
2255 0 : #define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
2256 0 : #define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
2257 0 : #define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
2258 0 : #define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
2259 0 : #define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
2260 0 : #define TIMER2_CC2_PA9 SILABS_DBUS_TIMER2_CC2(0x0, 0x9)
2261 0 : #define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
2262 0 : #define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
2263 0 : #define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
2264 0 : #define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
2265 0 : #define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
2266 0 : #define TIMER2_CC2_PB5 SILABS_DBUS_TIMER2_CC2(0x1, 0x5)
2267 0 : #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
2268 0 : #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
2269 0 : #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
2270 0 : #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
2271 0 : #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
2272 0 : #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
2273 0 : #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
2274 0 : #define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
2275 0 : #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
2276 0 : #define TIMER2_CDTI0_PA9 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x9)
2277 0 : #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
2278 0 : #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
2279 0 : #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
2280 0 : #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
2281 0 : #define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
2282 0 : #define TIMER2_CDTI0_PB5 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x5)
2283 0 : #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
2284 0 : #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
2285 0 : #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
2286 0 : #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
2287 0 : #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
2288 0 : #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
2289 0 : #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
2290 0 : #define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
2291 0 : #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
2292 0 : #define TIMER2_CDTI1_PA9 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x9)
2293 0 : #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
2294 0 : #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
2295 0 : #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
2296 0 : #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
2297 0 : #define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
2298 0 : #define TIMER2_CDTI1_PB5 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x5)
2299 0 : #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
2300 0 : #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
2301 0 : #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
2302 0 : #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
2303 0 : #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
2304 0 : #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
2305 0 : #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
2306 0 : #define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
2307 0 : #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
2308 0 : #define TIMER2_CDTI2_PA9 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x9)
2309 0 : #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
2310 0 : #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
2311 0 : #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
2312 0 : #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
2313 0 : #define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
2314 0 : #define TIMER2_CDTI2_PB5 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x5)
2315 :
2316 0 : #define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
2317 0 : #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
2318 0 : #define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
2319 0 : #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
2320 0 : #define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
2321 0 : #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
2322 0 : #define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
2323 0 : #define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
2324 0 : #define TIMER3_CC0_PC8 SILABS_DBUS_TIMER3_CC0(0x2, 0x8)
2325 0 : #define TIMER3_CC0_PC9 SILABS_DBUS_TIMER3_CC0(0x2, 0x9)
2326 0 : #define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
2327 0 : #define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
2328 0 : #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
2329 0 : #define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
2330 0 : #define TIMER3_CC0_PD4 SILABS_DBUS_TIMER3_CC0(0x3, 0x4)
2331 0 : #define TIMER3_CC0_PD5 SILABS_DBUS_TIMER3_CC0(0x3, 0x5)
2332 0 : #define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
2333 0 : #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
2334 0 : #define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
2335 0 : #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
2336 0 : #define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
2337 0 : #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
2338 0 : #define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
2339 0 : #define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
2340 0 : #define TIMER3_CC1_PC8 SILABS_DBUS_TIMER3_CC1(0x2, 0x8)
2341 0 : #define TIMER3_CC1_PC9 SILABS_DBUS_TIMER3_CC1(0x2, 0x9)
2342 0 : #define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
2343 0 : #define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
2344 0 : #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
2345 0 : #define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
2346 0 : #define TIMER3_CC1_PD4 SILABS_DBUS_TIMER3_CC1(0x3, 0x4)
2347 0 : #define TIMER3_CC1_PD5 SILABS_DBUS_TIMER3_CC1(0x3, 0x5)
2348 0 : #define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
2349 0 : #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
2350 0 : #define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
2351 0 : #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
2352 0 : #define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
2353 0 : #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
2354 0 : #define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
2355 0 : #define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
2356 0 : #define TIMER3_CC2_PC8 SILABS_DBUS_TIMER3_CC2(0x2, 0x8)
2357 0 : #define TIMER3_CC2_PC9 SILABS_DBUS_TIMER3_CC2(0x2, 0x9)
2358 0 : #define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
2359 0 : #define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
2360 0 : #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
2361 0 : #define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
2362 0 : #define TIMER3_CC2_PD4 SILABS_DBUS_TIMER3_CC2(0x3, 0x4)
2363 0 : #define TIMER3_CC2_PD5 SILABS_DBUS_TIMER3_CC2(0x3, 0x5)
2364 0 : #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
2365 0 : #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
2366 0 : #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
2367 0 : #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
2368 0 : #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
2369 0 : #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
2370 0 : #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
2371 0 : #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
2372 0 : #define TIMER3_CDTI0_PC8 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x8)
2373 0 : #define TIMER3_CDTI0_PC9 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x9)
2374 0 : #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
2375 0 : #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
2376 0 : #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
2377 0 : #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
2378 0 : #define TIMER3_CDTI0_PD4 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x4)
2379 0 : #define TIMER3_CDTI0_PD5 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x5)
2380 0 : #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
2381 0 : #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
2382 0 : #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
2383 0 : #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
2384 0 : #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
2385 0 : #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
2386 0 : #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
2387 0 : #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
2388 0 : #define TIMER3_CDTI1_PC8 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x8)
2389 0 : #define TIMER3_CDTI1_PC9 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x9)
2390 0 : #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
2391 0 : #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
2392 0 : #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
2393 0 : #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
2394 0 : #define TIMER3_CDTI1_PD4 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x4)
2395 0 : #define TIMER3_CDTI1_PD5 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x5)
2396 0 : #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
2397 0 : #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
2398 0 : #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
2399 0 : #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
2400 0 : #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
2401 0 : #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
2402 0 : #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
2403 0 : #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
2404 0 : #define TIMER3_CDTI2_PC8 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x8)
2405 0 : #define TIMER3_CDTI2_PC9 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x9)
2406 0 : #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
2407 0 : #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
2408 0 : #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
2409 0 : #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
2410 0 : #define TIMER3_CDTI2_PD4 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x4)
2411 0 : #define TIMER3_CDTI2_PD5 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x5)
2412 :
2413 0 : #define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
2414 0 : #define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
2415 0 : #define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
2416 0 : #define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
2417 0 : #define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
2418 0 : #define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
2419 0 : #define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
2420 0 : #define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
2421 0 : #define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
2422 0 : #define TIMER4_CC0_PA9 SILABS_DBUS_TIMER4_CC0(0x0, 0x9)
2423 0 : #define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
2424 0 : #define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
2425 0 : #define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
2426 0 : #define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
2427 0 : #define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
2428 0 : #define TIMER4_CC0_PB5 SILABS_DBUS_TIMER4_CC0(0x1, 0x5)
2429 0 : #define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
2430 0 : #define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
2431 0 : #define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
2432 0 : #define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
2433 0 : #define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
2434 0 : #define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
2435 0 : #define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
2436 0 : #define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
2437 0 : #define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
2438 0 : #define TIMER4_CC1_PA9 SILABS_DBUS_TIMER4_CC1(0x0, 0x9)
2439 0 : #define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
2440 0 : #define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
2441 0 : #define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
2442 0 : #define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
2443 0 : #define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
2444 0 : #define TIMER4_CC1_PB5 SILABS_DBUS_TIMER4_CC1(0x1, 0x5)
2445 0 : #define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
2446 0 : #define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
2447 0 : #define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
2448 0 : #define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
2449 0 : #define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
2450 0 : #define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
2451 0 : #define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
2452 0 : #define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
2453 0 : #define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
2454 0 : #define TIMER4_CC2_PA9 SILABS_DBUS_TIMER4_CC2(0x0, 0x9)
2455 0 : #define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
2456 0 : #define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
2457 0 : #define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
2458 0 : #define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
2459 0 : #define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
2460 0 : #define TIMER4_CC2_PB5 SILABS_DBUS_TIMER4_CC2(0x1, 0x5)
2461 0 : #define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
2462 0 : #define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
2463 0 : #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
2464 0 : #define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
2465 0 : #define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
2466 0 : #define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
2467 0 : #define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
2468 0 : #define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
2469 0 : #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
2470 0 : #define TIMER4_CDTI0_PA9 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x9)
2471 0 : #define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
2472 0 : #define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
2473 0 : #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
2474 0 : #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
2475 0 : #define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
2476 0 : #define TIMER4_CDTI0_PB5 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x5)
2477 0 : #define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
2478 0 : #define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
2479 0 : #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
2480 0 : #define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
2481 0 : #define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
2482 0 : #define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
2483 0 : #define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
2484 0 : #define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
2485 0 : #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
2486 0 : #define TIMER4_CDTI1_PA9 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x9)
2487 0 : #define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
2488 0 : #define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
2489 0 : #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
2490 0 : #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
2491 0 : #define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
2492 0 : #define TIMER4_CDTI1_PB5 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x5)
2493 0 : #define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
2494 0 : #define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
2495 0 : #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
2496 0 : #define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
2497 0 : #define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
2498 0 : #define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
2499 0 : #define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
2500 0 : #define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
2501 0 : #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
2502 0 : #define TIMER4_CDTI2_PA9 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x9)
2503 0 : #define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
2504 0 : #define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
2505 0 : #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
2506 0 : #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
2507 0 : #define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
2508 0 : #define TIMER4_CDTI2_PB5 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x5)
2509 :
2510 0 : #define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0)
2511 0 : #define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1)
2512 0 : #define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2)
2513 0 : #define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3)
2514 0 : #define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4)
2515 0 : #define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5)
2516 0 : #define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6)
2517 0 : #define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7)
2518 0 : #define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8)
2519 0 : #define USART0_CS_PA9 SILABS_DBUS_USART0_CS(0x0, 0x9)
2520 0 : #define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0)
2521 0 : #define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1)
2522 0 : #define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2)
2523 0 : #define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3)
2524 0 : #define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4)
2525 0 : #define USART0_CS_PB5 SILABS_DBUS_USART0_CS(0x1, 0x5)
2526 0 : #define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0)
2527 0 : #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
2528 0 : #define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2)
2529 0 : #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
2530 0 : #define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4)
2531 0 : #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
2532 0 : #define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6)
2533 0 : #define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7)
2534 0 : #define USART0_CS_PC8 SILABS_DBUS_USART0_CS(0x2, 0x8)
2535 0 : #define USART0_CS_PC9 SILABS_DBUS_USART0_CS(0x2, 0x9)
2536 0 : #define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0)
2537 0 : #define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1)
2538 0 : #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
2539 0 : #define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3)
2540 0 : #define USART0_CS_PD4 SILABS_DBUS_USART0_CS(0x3, 0x4)
2541 0 : #define USART0_CS_PD5 SILABS_DBUS_USART0_CS(0x3, 0x5)
2542 0 : #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
2543 0 : #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
2544 0 : #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
2545 0 : #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
2546 0 : #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
2547 0 : #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
2548 0 : #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
2549 0 : #define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
2550 0 : #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
2551 0 : #define USART0_RTS_PA9 SILABS_DBUS_USART0_RTS(0x0, 0x9)
2552 0 : #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
2553 0 : #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
2554 0 : #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
2555 0 : #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
2556 0 : #define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
2557 0 : #define USART0_RTS_PB5 SILABS_DBUS_USART0_RTS(0x1, 0x5)
2558 0 : #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
2559 0 : #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
2560 0 : #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
2561 0 : #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
2562 0 : #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
2563 0 : #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
2564 0 : #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
2565 0 : #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
2566 0 : #define USART0_RTS_PC8 SILABS_DBUS_USART0_RTS(0x2, 0x8)
2567 0 : #define USART0_RTS_PC9 SILABS_DBUS_USART0_RTS(0x2, 0x9)
2568 0 : #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
2569 0 : #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
2570 0 : #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
2571 0 : #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
2572 0 : #define USART0_RTS_PD4 SILABS_DBUS_USART0_RTS(0x3, 0x4)
2573 0 : #define USART0_RTS_PD5 SILABS_DBUS_USART0_RTS(0x3, 0x5)
2574 0 : #define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0)
2575 0 : #define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1)
2576 0 : #define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2)
2577 0 : #define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3)
2578 0 : #define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4)
2579 0 : #define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5)
2580 0 : #define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6)
2581 0 : #define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7)
2582 0 : #define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8)
2583 0 : #define USART0_RX_PA9 SILABS_DBUS_USART0_RX(0x0, 0x9)
2584 0 : #define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0)
2585 0 : #define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1)
2586 0 : #define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2)
2587 0 : #define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3)
2588 0 : #define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4)
2589 0 : #define USART0_RX_PB5 SILABS_DBUS_USART0_RX(0x1, 0x5)
2590 0 : #define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0)
2591 0 : #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
2592 0 : #define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2)
2593 0 : #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
2594 0 : #define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4)
2595 0 : #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
2596 0 : #define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6)
2597 0 : #define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7)
2598 0 : #define USART0_RX_PC8 SILABS_DBUS_USART0_RX(0x2, 0x8)
2599 0 : #define USART0_RX_PC9 SILABS_DBUS_USART0_RX(0x2, 0x9)
2600 0 : #define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0)
2601 0 : #define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1)
2602 0 : #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
2603 0 : #define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3)
2604 0 : #define USART0_RX_PD4 SILABS_DBUS_USART0_RX(0x3, 0x4)
2605 0 : #define USART0_RX_PD5 SILABS_DBUS_USART0_RX(0x3, 0x5)
2606 0 : #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
2607 0 : #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
2608 0 : #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
2609 0 : #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
2610 0 : #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
2611 0 : #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
2612 0 : #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
2613 0 : #define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
2614 0 : #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
2615 0 : #define USART0_CLK_PA9 SILABS_DBUS_USART0_CLK(0x0, 0x9)
2616 0 : #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
2617 0 : #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
2618 0 : #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
2619 0 : #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
2620 0 : #define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
2621 0 : #define USART0_CLK_PB5 SILABS_DBUS_USART0_CLK(0x1, 0x5)
2622 0 : #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
2623 0 : #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
2624 0 : #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
2625 0 : #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
2626 0 : #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
2627 0 : #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
2628 0 : #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
2629 0 : #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
2630 0 : #define USART0_CLK_PC8 SILABS_DBUS_USART0_CLK(0x2, 0x8)
2631 0 : #define USART0_CLK_PC9 SILABS_DBUS_USART0_CLK(0x2, 0x9)
2632 0 : #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
2633 0 : #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
2634 0 : #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
2635 0 : #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
2636 0 : #define USART0_CLK_PD4 SILABS_DBUS_USART0_CLK(0x3, 0x4)
2637 0 : #define USART0_CLK_PD5 SILABS_DBUS_USART0_CLK(0x3, 0x5)
2638 0 : #define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0)
2639 0 : #define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1)
2640 0 : #define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2)
2641 0 : #define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3)
2642 0 : #define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4)
2643 0 : #define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5)
2644 0 : #define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6)
2645 0 : #define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7)
2646 0 : #define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8)
2647 0 : #define USART0_TX_PA9 SILABS_DBUS_USART0_TX(0x0, 0x9)
2648 0 : #define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0)
2649 0 : #define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1)
2650 0 : #define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2)
2651 0 : #define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3)
2652 0 : #define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4)
2653 0 : #define USART0_TX_PB5 SILABS_DBUS_USART0_TX(0x1, 0x5)
2654 0 : #define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0)
2655 0 : #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
2656 0 : #define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2)
2657 0 : #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
2658 0 : #define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4)
2659 0 : #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
2660 0 : #define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6)
2661 0 : #define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7)
2662 0 : #define USART0_TX_PC8 SILABS_DBUS_USART0_TX(0x2, 0x8)
2663 0 : #define USART0_TX_PC9 SILABS_DBUS_USART0_TX(0x2, 0x9)
2664 0 : #define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0)
2665 0 : #define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1)
2666 0 : #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
2667 0 : #define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3)
2668 0 : #define USART0_TX_PD4 SILABS_DBUS_USART0_TX(0x3, 0x4)
2669 0 : #define USART0_TX_PD5 SILABS_DBUS_USART0_TX(0x3, 0x5)
2670 0 : #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
2671 0 : #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
2672 0 : #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
2673 0 : #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
2674 0 : #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
2675 0 : #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
2676 0 : #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
2677 0 : #define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
2678 0 : #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
2679 0 : #define USART0_CTS_PA9 SILABS_DBUS_USART0_CTS(0x0, 0x9)
2680 0 : #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
2681 0 : #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
2682 0 : #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
2683 0 : #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
2684 0 : #define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
2685 0 : #define USART0_CTS_PB5 SILABS_DBUS_USART0_CTS(0x1, 0x5)
2686 0 : #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
2687 0 : #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
2688 0 : #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
2689 0 : #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
2690 0 : #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
2691 0 : #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
2692 0 : #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
2693 0 : #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
2694 0 : #define USART0_CTS_PC8 SILABS_DBUS_USART0_CTS(0x2, 0x8)
2695 0 : #define USART0_CTS_PC9 SILABS_DBUS_USART0_CTS(0x2, 0x9)
2696 0 : #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
2697 0 : #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
2698 0 : #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
2699 0 : #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
2700 0 : #define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4)
2701 0 : #define USART0_CTS_PD5 SILABS_DBUS_USART0_CTS(0x3, 0x5)
2702 :
2703 : #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG24_PINCTRL_H_ */
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