Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Silicon Laboratories Inc.
3 : * SPDX-License-Identifier: Apache-2.0
4 : *
5 : * Pin Control for Silicon Labs XG28 devices
6 : *
7 : * This file was generated by the script gen_pinctrl.py in the hal_silabs module.
8 : * Do not manually edit.
9 : */
10 :
11 : #ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG28_PINCTRL_H_
12 : #define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG28_PINCTRL_H_
13 :
14 : #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
15 :
16 0 : #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1)
17 :
18 0 : #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
19 :
20 0 : #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 2)
21 0 : #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 22, 1, 1, 3)
22 0 : #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 22, 1, 2, 4)
23 0 : #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1)
24 :
25 0 : #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 33, 1, 0, 1)
26 0 : #define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 33, 1, 1, 3)
27 0 : #define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 33, 1, 2, 4)
28 0 : #define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 33, 1, 3, 5)
29 0 : #define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 33, 1, 4, 6)
30 0 : #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 33, 0, 0, 2)
31 :
32 0 : #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1)
33 0 : #define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 41, 1, 1, 3)
34 0 : #define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 41, 1, 2, 4)
35 0 : #define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 41, 1, 3, 5)
36 0 : #define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 41, 1, 4, 6)
37 0 : #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 41, 0, 0, 2)
38 :
39 0 : #define SILABS_DBUS_EUSART2_CS(port, pin) SILABS_DBUS(port, pin, 49, 1, 0, 1)
40 0 : #define SILABS_DBUS_EUSART2_RTS(port, pin) SILABS_DBUS(port, pin, 49, 1, 1, 3)
41 0 : #define SILABS_DBUS_EUSART2_RX(port, pin) SILABS_DBUS(port, pin, 49, 1, 2, 4)
42 0 : #define SILABS_DBUS_EUSART2_SCLK(port, pin) SILABS_DBUS(port, pin, 49, 1, 3, 5)
43 0 : #define SILABS_DBUS_EUSART2_TX(port, pin) SILABS_DBUS(port, pin, 49, 1, 4, 6)
44 0 : #define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 49, 0, 0, 2)
45 :
46 0 : #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 57, 1, 0, 1)
47 0 : #define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 57, 1, 1, 2)
48 0 : #define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 57, 1, 2, 3)
49 :
50 0 : #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 62, 1, 0, 1)
51 0 : #define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 62, 1, 1, 2)
52 :
53 0 : #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 66, 1, 0, 1)
54 0 : #define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 66, 1, 1, 2)
55 :
56 0 : #define SILABS_DBUS_KEYSCAN_COLOUT0(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1)
57 0 : #define SILABS_DBUS_KEYSCAN_COLOUT1(port, pin) SILABS_DBUS(port, pin, 70, 1, 1, 2)
58 0 : #define SILABS_DBUS_KEYSCAN_COLOUT2(port, pin) SILABS_DBUS(port, pin, 70, 1, 2, 3)
59 0 : #define SILABS_DBUS_KEYSCAN_COLOUT3(port, pin) SILABS_DBUS(port, pin, 70, 1, 3, 4)
60 0 : #define SILABS_DBUS_KEYSCAN_COLOUT4(port, pin) SILABS_DBUS(port, pin, 70, 1, 4, 5)
61 0 : #define SILABS_DBUS_KEYSCAN_COLOUT5(port, pin) SILABS_DBUS(port, pin, 70, 1, 5, 6)
62 0 : #define SILABS_DBUS_KEYSCAN_COLOUT6(port, pin) SILABS_DBUS(port, pin, 70, 1, 6, 7)
63 0 : #define SILABS_DBUS_KEYSCAN_COLOUT7(port, pin) SILABS_DBUS(port, pin, 70, 1, 7, 8)
64 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE0(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 9)
65 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE1(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 10)
66 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE2(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 11)
67 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE3(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 12)
68 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE4(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 13)
69 0 : #define SILABS_DBUS_KEYSCAN_ROWSENSE5(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 14)
70 :
71 0 : #define SILABS_DBUS_LESENSE_CH0OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 0, 1)
72 0 : #define SILABS_DBUS_LESENSE_CH1OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 1, 2)
73 0 : #define SILABS_DBUS_LESENSE_CH2OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 2, 3)
74 0 : #define SILABS_DBUS_LESENSE_CH3OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 3, 4)
75 0 : #define SILABS_DBUS_LESENSE_CH4OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 4, 5)
76 0 : #define SILABS_DBUS_LESENSE_CH5OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 5, 6)
77 0 : #define SILABS_DBUS_LESENSE_CH6OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 6, 7)
78 0 : #define SILABS_DBUS_LESENSE_CH7OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 7, 8)
79 0 : #define SILABS_DBUS_LESENSE_CH8OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 8, 9)
80 0 : #define SILABS_DBUS_LESENSE_CH9OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 9, 10)
81 0 : #define SILABS_DBUS_LESENSE_CH10OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 10, 11)
82 0 : #define SILABS_DBUS_LESENSE_CH11OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 11, 12)
83 0 : #define SILABS_DBUS_LESENSE_CH12OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 12, 13)
84 0 : #define SILABS_DBUS_LESENSE_CH13OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 13, 14)
85 0 : #define SILABS_DBUS_LESENSE_CH14OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 14, 15)
86 0 : #define SILABS_DBUS_LESENSE_CH15OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 15, 16)
87 :
88 0 : #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 104, 1, 0, 1)
89 0 : #define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 104, 1, 1, 2)
90 :
91 0 : #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 108, 1, 0, 1)
92 0 : #define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 108, 1, 1, 2)
93 0 : #define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 108, 1, 2, 3)
94 0 : #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 108, 1, 3, 4)
95 0 : #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 108, 1, 4, 5)
96 0 : #define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 108, 1, 5, 6)
97 0 : #define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 108, 1, 6, 7)
98 0 : #define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 108, 1, 7, 8)
99 0 : #define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 108, 1, 8, 9)
100 0 : #define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 108, 1, 9, 10)
101 0 : #define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 108, 1, 10, 11)
102 0 : #define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 108, 1, 11, 12)
103 0 : #define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 108, 1, 12, 13)
104 0 : #define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 108, 1, 13, 14)
105 0 : #define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 108, 1, 14, 16)
106 0 : #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 108, 0, 0, 15)
107 :
108 0 : #define SILABS_DBUS_PCNT0_S0IN(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 0)
109 0 : #define SILABS_DBUS_PCNT0_S1IN(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 1)
110 :
111 0 : #define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 130, 1, 0, 1)
112 0 : #define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 130, 1, 1, 2)
113 0 : #define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 130, 1, 2, 3)
114 0 : #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 130, 1, 3, 4)
115 0 : #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 130, 1, 4, 5)
116 0 : #define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 130, 1, 5, 6)
117 0 : #define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 130, 1, 6, 7)
118 0 : #define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 130, 1, 7, 8)
119 0 : #define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 130, 1, 8, 9)
120 0 : #define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 130, 1, 9, 10)
121 0 : #define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 130, 1, 10, 11)
122 0 : #define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 130, 1, 11, 12)
123 0 : #define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 130, 1, 12, 13)
124 0 : #define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 130, 1, 13, 14)
125 0 : #define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 130, 1, 14, 15)
126 0 : #define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 130, 1, 15, 16)
127 :
128 0 : #define SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(port, pin) SILABS_DBUS(port, pin, 172, 0, 0, 0)
129 :
130 0 : #define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 174, 1, 0, 1)
131 0 : #define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 174, 1, 1, 2)
132 0 : #define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 174, 1, 2, 3)
133 0 : #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 174, 1, 3, 4)
134 0 : #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 174, 1, 4, 5)
135 0 : #define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 174, 1, 5, 6)
136 :
137 0 : #define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 182, 1, 0, 1)
138 0 : #define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 182, 1, 1, 2)
139 0 : #define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 182, 1, 2, 3)
140 0 : #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 182, 1, 3, 4)
141 0 : #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 182, 1, 4, 5)
142 0 : #define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 182, 1, 5, 6)
143 :
144 0 : #define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 190, 1, 0, 1)
145 0 : #define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 190, 1, 1, 2)
146 0 : #define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 190, 1, 2, 3)
147 0 : #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 190, 1, 3, 4)
148 0 : #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 190, 1, 4, 5)
149 0 : #define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 190, 1, 5, 6)
150 :
151 0 : #define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 198, 1, 0, 1)
152 0 : #define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 198, 1, 1, 2)
153 0 : #define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 198, 1, 2, 3)
154 0 : #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 198, 1, 3, 4)
155 0 : #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 198, 1, 4, 5)
156 0 : #define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 198, 1, 5, 6)
157 :
158 0 : #define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 206, 1, 0, 1)
159 0 : #define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 206, 1, 1, 2)
160 0 : #define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 206, 1, 2, 3)
161 0 : #define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 206, 1, 3, 4)
162 0 : #define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 206, 1, 4, 5)
163 0 : #define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 206, 1, 5, 6)
164 :
165 0 : #define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 214, 1, 0, 1)
166 0 : #define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 214, 1, 1, 3)
167 0 : #define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 214, 1, 2, 4)
168 0 : #define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 214, 1, 3, 5)
169 0 : #define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 214, 1, 4, 6)
170 0 : #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 214, 0, 0, 2)
171 :
172 0 : #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
173 0 : #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
174 0 : #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
175 0 : #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
176 0 : #define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4)
177 0 : #define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
178 0 : #define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
179 0 : #define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7)
180 0 : #define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8)
181 0 : #define ACMP0_ACMPOUT_PA9 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x9)
182 0 : #define ACMP0_ACMPOUT_PA10 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xa)
183 0 : #define ACMP0_ACMPOUT_PA11 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xb)
184 0 : #define ACMP0_ACMPOUT_PA12 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xc)
185 0 : #define ACMP0_ACMPOUT_PA13 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xd)
186 0 : #define ACMP0_ACMPOUT_PA14 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xe)
187 0 : #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
188 0 : #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
189 0 : #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
190 0 : #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
191 0 : #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
192 0 : #define ACMP0_ACMPOUT_PB5 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x5)
193 0 : #define ACMP0_ACMPOUT_PB6 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x6)
194 0 : #define ACMP0_ACMPOUT_PB7 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x7)
195 0 : #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
196 0 : #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
197 0 : #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
198 0 : #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
199 0 : #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
200 0 : #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
201 0 : #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
202 0 : #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
203 0 : #define ACMP0_ACMPOUT_PC8 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x8)
204 0 : #define ACMP0_ACMPOUT_PC9 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x9)
205 0 : #define ACMP0_ACMPOUT_PC10 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xa)
206 0 : #define ACMP0_ACMPOUT_PC11 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xb)
207 0 : #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
208 0 : #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
209 0 : #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
210 0 : #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
211 0 : #define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4)
212 0 : #define ACMP0_ACMPOUT_PD5 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x5)
213 0 : #define ACMP0_ACMPOUT_PD6 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x6)
214 0 : #define ACMP0_ACMPOUT_PD7 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x7)
215 0 : #define ACMP0_ACMPOUT_PD8 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x8)
216 0 : #define ACMP0_ACMPOUT_PD9 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x9)
217 0 : #define ACMP0_ACMPOUT_PD10 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xa)
218 0 : #define ACMP0_ACMPOUT_PD11 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xb)
219 0 : #define ACMP0_ACMPOUT_PD12 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xc)
220 0 : #define ACMP0_ACMPOUT_PD13 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xd)
221 0 : #define ACMP0_ACMPOUT_PD14 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xe)
222 0 : #define ACMP0_ACMPOUT_PD15 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xf)
223 :
224 0 : #define ACMP1_ACMPOUT_PA0 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x0)
225 0 : #define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1)
226 0 : #define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2)
227 0 : #define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3)
228 0 : #define ACMP1_ACMPOUT_PA4 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x4)
229 0 : #define ACMP1_ACMPOUT_PA5 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x5)
230 0 : #define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6)
231 0 : #define ACMP1_ACMPOUT_PA7 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x7)
232 0 : #define ACMP1_ACMPOUT_PA8 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x8)
233 0 : #define ACMP1_ACMPOUT_PA9 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x9)
234 0 : #define ACMP1_ACMPOUT_PA10 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xa)
235 0 : #define ACMP1_ACMPOUT_PA11 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xb)
236 0 : #define ACMP1_ACMPOUT_PA12 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xc)
237 0 : #define ACMP1_ACMPOUT_PA13 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xd)
238 0 : #define ACMP1_ACMPOUT_PA14 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xe)
239 0 : #define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0)
240 0 : #define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1)
241 0 : #define ACMP1_ACMPOUT_PB2 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x2)
242 0 : #define ACMP1_ACMPOUT_PB3 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x3)
243 0 : #define ACMP1_ACMPOUT_PB4 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x4)
244 0 : #define ACMP1_ACMPOUT_PB5 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x5)
245 0 : #define ACMP1_ACMPOUT_PB6 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x6)
246 0 : #define ACMP1_ACMPOUT_PB7 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x7)
247 0 : #define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0)
248 0 : #define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1)
249 0 : #define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2)
250 0 : #define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3)
251 0 : #define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4)
252 0 : #define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5)
253 0 : #define ACMP1_ACMPOUT_PC6 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x6)
254 0 : #define ACMP1_ACMPOUT_PC7 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x7)
255 0 : #define ACMP1_ACMPOUT_PC8 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x8)
256 0 : #define ACMP1_ACMPOUT_PC9 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x9)
257 0 : #define ACMP1_ACMPOUT_PC10 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xa)
258 0 : #define ACMP1_ACMPOUT_PC11 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xb)
259 0 : #define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0)
260 0 : #define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1)
261 0 : #define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2)
262 0 : #define ACMP1_ACMPOUT_PD3 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x3)
263 0 : #define ACMP1_ACMPOUT_PD4 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x4)
264 0 : #define ACMP1_ACMPOUT_PD5 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x5)
265 0 : #define ACMP1_ACMPOUT_PD6 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x6)
266 0 : #define ACMP1_ACMPOUT_PD7 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x7)
267 0 : #define ACMP1_ACMPOUT_PD8 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x8)
268 0 : #define ACMP1_ACMPOUT_PD9 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x9)
269 0 : #define ACMP1_ACMPOUT_PD10 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xa)
270 0 : #define ACMP1_ACMPOUT_PD11 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xb)
271 0 : #define ACMP1_ACMPOUT_PD12 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xc)
272 0 : #define ACMP1_ACMPOUT_PD13 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xd)
273 0 : #define ACMP1_ACMPOUT_PD14 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xe)
274 0 : #define ACMP1_ACMPOUT_PD15 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xf)
275 :
276 0 : #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
277 0 : #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
278 0 : #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
279 0 : #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
280 0 : #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
281 0 : #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
282 0 : #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
283 0 : #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
284 0 : #define CMU_CLKOUT0_PC8 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x8)
285 0 : #define CMU_CLKOUT0_PC9 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x9)
286 0 : #define CMU_CLKOUT0_PC10 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xa)
287 0 : #define CMU_CLKOUT0_PC11 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xb)
288 0 : #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
289 0 : #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
290 0 : #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
291 0 : #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
292 0 : #define CMU_CLKOUT0_PD4 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x4)
293 0 : #define CMU_CLKOUT0_PD5 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x5)
294 0 : #define CMU_CLKOUT0_PD6 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x6)
295 0 : #define CMU_CLKOUT0_PD7 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x7)
296 0 : #define CMU_CLKOUT0_PD8 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x8)
297 0 : #define CMU_CLKOUT0_PD9 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x9)
298 0 : #define CMU_CLKOUT0_PD10 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xa)
299 0 : #define CMU_CLKOUT0_PD11 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xb)
300 0 : #define CMU_CLKOUT0_PD12 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xc)
301 0 : #define CMU_CLKOUT0_PD13 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xd)
302 0 : #define CMU_CLKOUT0_PD14 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xe)
303 0 : #define CMU_CLKOUT0_PD15 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xf)
304 0 : #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
305 0 : #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
306 0 : #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
307 0 : #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
308 0 : #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
309 0 : #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
310 0 : #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
311 0 : #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
312 0 : #define CMU_CLKOUT1_PC8 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x8)
313 0 : #define CMU_CLKOUT1_PC9 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x9)
314 0 : #define CMU_CLKOUT1_PC10 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xa)
315 0 : #define CMU_CLKOUT1_PC11 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xb)
316 0 : #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
317 0 : #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
318 0 : #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
319 0 : #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
320 0 : #define CMU_CLKOUT1_PD4 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x4)
321 0 : #define CMU_CLKOUT1_PD5 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x5)
322 0 : #define CMU_CLKOUT1_PD6 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x6)
323 0 : #define CMU_CLKOUT1_PD7 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x7)
324 0 : #define CMU_CLKOUT1_PD8 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x8)
325 0 : #define CMU_CLKOUT1_PD9 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x9)
326 0 : #define CMU_CLKOUT1_PD10 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xa)
327 0 : #define CMU_CLKOUT1_PD11 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xb)
328 0 : #define CMU_CLKOUT1_PD12 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xc)
329 0 : #define CMU_CLKOUT1_PD13 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xd)
330 0 : #define CMU_CLKOUT1_PD14 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xe)
331 0 : #define CMU_CLKOUT1_PD15 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xf)
332 0 : #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
333 0 : #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
334 0 : #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
335 0 : #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
336 0 : #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
337 0 : #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
338 0 : #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
339 0 : #define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
340 0 : #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
341 0 : #define CMU_CLKOUT2_PA9 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x9)
342 0 : #define CMU_CLKOUT2_PA10 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xa)
343 0 : #define CMU_CLKOUT2_PA11 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xb)
344 0 : #define CMU_CLKOUT2_PA12 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xc)
345 0 : #define CMU_CLKOUT2_PA13 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xd)
346 0 : #define CMU_CLKOUT2_PA14 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xe)
347 0 : #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
348 0 : #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
349 0 : #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
350 0 : #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
351 0 : #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
352 0 : #define CMU_CLKOUT2_PB5 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x5)
353 0 : #define CMU_CLKOUT2_PB6 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x6)
354 0 : #define CMU_CLKOUT2_PB7 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x7)
355 0 : #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
356 0 : #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
357 0 : #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
358 0 : #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
359 0 : #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
360 0 : #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
361 0 : #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
362 0 : #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
363 0 : #define CMU_CLKIN0_PC8 SILABS_DBUS_CMU_CLKIN0(0x2, 0x8)
364 0 : #define CMU_CLKIN0_PC9 SILABS_DBUS_CMU_CLKIN0(0x2, 0x9)
365 0 : #define CMU_CLKIN0_PC10 SILABS_DBUS_CMU_CLKIN0(0x2, 0xa)
366 0 : #define CMU_CLKIN0_PC11 SILABS_DBUS_CMU_CLKIN0(0x2, 0xb)
367 0 : #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
368 0 : #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
369 0 : #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
370 0 : #define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
371 0 : #define CMU_CLKIN0_PD4 SILABS_DBUS_CMU_CLKIN0(0x3, 0x4)
372 0 : #define CMU_CLKIN0_PD5 SILABS_DBUS_CMU_CLKIN0(0x3, 0x5)
373 0 : #define CMU_CLKIN0_PD6 SILABS_DBUS_CMU_CLKIN0(0x3, 0x6)
374 0 : #define CMU_CLKIN0_PD7 SILABS_DBUS_CMU_CLKIN0(0x3, 0x7)
375 0 : #define CMU_CLKIN0_PD8 SILABS_DBUS_CMU_CLKIN0(0x3, 0x8)
376 0 : #define CMU_CLKIN0_PD9 SILABS_DBUS_CMU_CLKIN0(0x3, 0x9)
377 0 : #define CMU_CLKIN0_PD10 SILABS_DBUS_CMU_CLKIN0(0x3, 0xa)
378 0 : #define CMU_CLKIN0_PD11 SILABS_DBUS_CMU_CLKIN0(0x3, 0xb)
379 0 : #define CMU_CLKIN0_PD12 SILABS_DBUS_CMU_CLKIN0(0x3, 0xc)
380 0 : #define CMU_CLKIN0_PD13 SILABS_DBUS_CMU_CLKIN0(0x3, 0xd)
381 0 : #define CMU_CLKIN0_PD14 SILABS_DBUS_CMU_CLKIN0(0x3, 0xe)
382 0 : #define CMU_CLKIN0_PD15 SILABS_DBUS_CMU_CLKIN0(0x3, 0xf)
383 :
384 0 : #define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0)
385 0 : #define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1)
386 0 : #define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2)
387 0 : #define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3)
388 0 : #define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4)
389 0 : #define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5)
390 0 : #define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6)
391 0 : #define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7)
392 0 : #define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8)
393 0 : #define EUSART0_CS_PA9 SILABS_DBUS_EUSART0_CS(0x0, 0x9)
394 0 : #define EUSART0_CS_PA10 SILABS_DBUS_EUSART0_CS(0x0, 0xa)
395 0 : #define EUSART0_CS_PA11 SILABS_DBUS_EUSART0_CS(0x0, 0xb)
396 0 : #define EUSART0_CS_PA12 SILABS_DBUS_EUSART0_CS(0x0, 0xc)
397 0 : #define EUSART0_CS_PA13 SILABS_DBUS_EUSART0_CS(0x0, 0xd)
398 0 : #define EUSART0_CS_PA14 SILABS_DBUS_EUSART0_CS(0x0, 0xe)
399 0 : #define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0)
400 0 : #define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1)
401 0 : #define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2)
402 0 : #define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3)
403 0 : #define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4)
404 0 : #define EUSART0_CS_PB5 SILABS_DBUS_EUSART0_CS(0x1, 0x5)
405 0 : #define EUSART0_CS_PB6 SILABS_DBUS_EUSART0_CS(0x1, 0x6)
406 0 : #define EUSART0_CS_PB7 SILABS_DBUS_EUSART0_CS(0x1, 0x7)
407 0 : #define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0)
408 0 : #define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1)
409 0 : #define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2)
410 0 : #define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3)
411 0 : #define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4)
412 0 : #define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5)
413 0 : #define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6)
414 0 : #define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7)
415 0 : #define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8)
416 0 : #define EUSART0_RTS_PA9 SILABS_DBUS_EUSART0_RTS(0x0, 0x9)
417 0 : #define EUSART0_RTS_PA10 SILABS_DBUS_EUSART0_RTS(0x0, 0xa)
418 0 : #define EUSART0_RTS_PA11 SILABS_DBUS_EUSART0_RTS(0x0, 0xb)
419 0 : #define EUSART0_RTS_PA12 SILABS_DBUS_EUSART0_RTS(0x0, 0xc)
420 0 : #define EUSART0_RTS_PA13 SILABS_DBUS_EUSART0_RTS(0x0, 0xd)
421 0 : #define EUSART0_RTS_PA14 SILABS_DBUS_EUSART0_RTS(0x0, 0xe)
422 0 : #define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0)
423 0 : #define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1)
424 0 : #define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
425 0 : #define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
426 0 : #define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4)
427 0 : #define EUSART0_RTS_PB5 SILABS_DBUS_EUSART0_RTS(0x1, 0x5)
428 0 : #define EUSART0_RTS_PB6 SILABS_DBUS_EUSART0_RTS(0x1, 0x6)
429 0 : #define EUSART0_RTS_PB7 SILABS_DBUS_EUSART0_RTS(0x1, 0x7)
430 0 : #define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0)
431 0 : #define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1)
432 0 : #define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2)
433 0 : #define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3)
434 0 : #define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4)
435 0 : #define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5)
436 0 : #define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6)
437 0 : #define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7)
438 0 : #define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8)
439 0 : #define EUSART0_RX_PA9 SILABS_DBUS_EUSART0_RX(0x0, 0x9)
440 0 : #define EUSART0_RX_PA10 SILABS_DBUS_EUSART0_RX(0x0, 0xa)
441 0 : #define EUSART0_RX_PA11 SILABS_DBUS_EUSART0_RX(0x0, 0xb)
442 0 : #define EUSART0_RX_PA12 SILABS_DBUS_EUSART0_RX(0x0, 0xc)
443 0 : #define EUSART0_RX_PA13 SILABS_DBUS_EUSART0_RX(0x0, 0xd)
444 0 : #define EUSART0_RX_PA14 SILABS_DBUS_EUSART0_RX(0x0, 0xe)
445 0 : #define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0)
446 0 : #define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1)
447 0 : #define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2)
448 0 : #define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3)
449 0 : #define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4)
450 0 : #define EUSART0_RX_PB5 SILABS_DBUS_EUSART0_RX(0x1, 0x5)
451 0 : #define EUSART0_RX_PB6 SILABS_DBUS_EUSART0_RX(0x1, 0x6)
452 0 : #define EUSART0_RX_PB7 SILABS_DBUS_EUSART0_RX(0x1, 0x7)
453 0 : #define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0)
454 0 : #define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1)
455 0 : #define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2)
456 0 : #define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3)
457 0 : #define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4)
458 0 : #define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5)
459 0 : #define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6)
460 0 : #define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7)
461 0 : #define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8)
462 0 : #define EUSART0_SCLK_PA9 SILABS_DBUS_EUSART0_SCLK(0x0, 0x9)
463 0 : #define EUSART0_SCLK_PA10 SILABS_DBUS_EUSART0_SCLK(0x0, 0xa)
464 0 : #define EUSART0_SCLK_PA11 SILABS_DBUS_EUSART0_SCLK(0x0, 0xb)
465 0 : #define EUSART0_SCLK_PA12 SILABS_DBUS_EUSART0_SCLK(0x0, 0xc)
466 0 : #define EUSART0_SCLK_PA13 SILABS_DBUS_EUSART0_SCLK(0x0, 0xd)
467 0 : #define EUSART0_SCLK_PA14 SILABS_DBUS_EUSART0_SCLK(0x0, 0xe)
468 0 : #define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0)
469 0 : #define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1)
470 0 : #define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
471 0 : #define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
472 0 : #define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4)
473 0 : #define EUSART0_SCLK_PB5 SILABS_DBUS_EUSART0_SCLK(0x1, 0x5)
474 0 : #define EUSART0_SCLK_PB6 SILABS_DBUS_EUSART0_SCLK(0x1, 0x6)
475 0 : #define EUSART0_SCLK_PB7 SILABS_DBUS_EUSART0_SCLK(0x1, 0x7)
476 0 : #define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0)
477 0 : #define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1)
478 0 : #define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2)
479 0 : #define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3)
480 0 : #define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4)
481 0 : #define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5)
482 0 : #define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6)
483 0 : #define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7)
484 0 : #define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8)
485 0 : #define EUSART0_TX_PA9 SILABS_DBUS_EUSART0_TX(0x0, 0x9)
486 0 : #define EUSART0_TX_PA10 SILABS_DBUS_EUSART0_TX(0x0, 0xa)
487 0 : #define EUSART0_TX_PA11 SILABS_DBUS_EUSART0_TX(0x0, 0xb)
488 0 : #define EUSART0_TX_PA12 SILABS_DBUS_EUSART0_TX(0x0, 0xc)
489 0 : #define EUSART0_TX_PA13 SILABS_DBUS_EUSART0_TX(0x0, 0xd)
490 0 : #define EUSART0_TX_PA14 SILABS_DBUS_EUSART0_TX(0x0, 0xe)
491 0 : #define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0)
492 0 : #define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1)
493 0 : #define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2)
494 0 : #define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3)
495 0 : #define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4)
496 0 : #define EUSART0_TX_PB5 SILABS_DBUS_EUSART0_TX(0x1, 0x5)
497 0 : #define EUSART0_TX_PB6 SILABS_DBUS_EUSART0_TX(0x1, 0x6)
498 0 : #define EUSART0_TX_PB7 SILABS_DBUS_EUSART0_TX(0x1, 0x7)
499 0 : #define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0)
500 0 : #define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1)
501 0 : #define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2)
502 0 : #define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3)
503 0 : #define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4)
504 0 : #define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5)
505 0 : #define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6)
506 0 : #define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7)
507 0 : #define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8)
508 0 : #define EUSART0_CTS_PA9 SILABS_DBUS_EUSART0_CTS(0x0, 0x9)
509 0 : #define EUSART0_CTS_PA10 SILABS_DBUS_EUSART0_CTS(0x0, 0xa)
510 0 : #define EUSART0_CTS_PA11 SILABS_DBUS_EUSART0_CTS(0x0, 0xb)
511 0 : #define EUSART0_CTS_PA12 SILABS_DBUS_EUSART0_CTS(0x0, 0xc)
512 0 : #define EUSART0_CTS_PA13 SILABS_DBUS_EUSART0_CTS(0x0, 0xd)
513 0 : #define EUSART0_CTS_PA14 SILABS_DBUS_EUSART0_CTS(0x0, 0xe)
514 0 : #define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0)
515 0 : #define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1)
516 0 : #define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
517 0 : #define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
518 0 : #define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4)
519 0 : #define EUSART0_CTS_PB5 SILABS_DBUS_EUSART0_CTS(0x1, 0x5)
520 0 : #define EUSART0_CTS_PB6 SILABS_DBUS_EUSART0_CTS(0x1, 0x6)
521 0 : #define EUSART0_CTS_PB7 SILABS_DBUS_EUSART0_CTS(0x1, 0x7)
522 :
523 0 : #define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0)
524 0 : #define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1)
525 0 : #define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2)
526 0 : #define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3)
527 0 : #define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4)
528 0 : #define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5)
529 0 : #define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6)
530 0 : #define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7)
531 0 : #define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8)
532 0 : #define EUSART1_CS_PA9 SILABS_DBUS_EUSART1_CS(0x0, 0x9)
533 0 : #define EUSART1_CS_PA10 SILABS_DBUS_EUSART1_CS(0x0, 0xa)
534 0 : #define EUSART1_CS_PA11 SILABS_DBUS_EUSART1_CS(0x0, 0xb)
535 0 : #define EUSART1_CS_PA12 SILABS_DBUS_EUSART1_CS(0x0, 0xc)
536 0 : #define EUSART1_CS_PA13 SILABS_DBUS_EUSART1_CS(0x0, 0xd)
537 0 : #define EUSART1_CS_PA14 SILABS_DBUS_EUSART1_CS(0x0, 0xe)
538 0 : #define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0)
539 0 : #define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1)
540 0 : #define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2)
541 0 : #define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3)
542 0 : #define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4)
543 0 : #define EUSART1_CS_PB5 SILABS_DBUS_EUSART1_CS(0x1, 0x5)
544 0 : #define EUSART1_CS_PB6 SILABS_DBUS_EUSART1_CS(0x1, 0x6)
545 0 : #define EUSART1_CS_PB7 SILABS_DBUS_EUSART1_CS(0x1, 0x7)
546 0 : #define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0)
547 0 : #define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1)
548 0 : #define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2)
549 0 : #define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3)
550 0 : #define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4)
551 0 : #define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5)
552 0 : #define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6)
553 0 : #define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7)
554 0 : #define EUSART1_CS_PC8 SILABS_DBUS_EUSART1_CS(0x2, 0x8)
555 0 : #define EUSART1_CS_PC9 SILABS_DBUS_EUSART1_CS(0x2, 0x9)
556 0 : #define EUSART1_CS_PC10 SILABS_DBUS_EUSART1_CS(0x2, 0xa)
557 0 : #define EUSART1_CS_PC11 SILABS_DBUS_EUSART1_CS(0x2, 0xb)
558 0 : #define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0)
559 0 : #define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1)
560 0 : #define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2)
561 0 : #define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3)
562 0 : #define EUSART1_CS_PD4 SILABS_DBUS_EUSART1_CS(0x3, 0x4)
563 0 : #define EUSART1_CS_PD5 SILABS_DBUS_EUSART1_CS(0x3, 0x5)
564 0 : #define EUSART1_CS_PD6 SILABS_DBUS_EUSART1_CS(0x3, 0x6)
565 0 : #define EUSART1_CS_PD7 SILABS_DBUS_EUSART1_CS(0x3, 0x7)
566 0 : #define EUSART1_CS_PD8 SILABS_DBUS_EUSART1_CS(0x3, 0x8)
567 0 : #define EUSART1_CS_PD9 SILABS_DBUS_EUSART1_CS(0x3, 0x9)
568 0 : #define EUSART1_CS_PD10 SILABS_DBUS_EUSART1_CS(0x3, 0xa)
569 0 : #define EUSART1_CS_PD11 SILABS_DBUS_EUSART1_CS(0x3, 0xb)
570 0 : #define EUSART1_CS_PD12 SILABS_DBUS_EUSART1_CS(0x3, 0xc)
571 0 : #define EUSART1_CS_PD13 SILABS_DBUS_EUSART1_CS(0x3, 0xd)
572 0 : #define EUSART1_CS_PD14 SILABS_DBUS_EUSART1_CS(0x3, 0xe)
573 0 : #define EUSART1_CS_PD15 SILABS_DBUS_EUSART1_CS(0x3, 0xf)
574 0 : #define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0)
575 0 : #define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1)
576 0 : #define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2)
577 0 : #define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3)
578 0 : #define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4)
579 0 : #define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5)
580 0 : #define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6)
581 0 : #define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7)
582 0 : #define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8)
583 0 : #define EUSART1_RTS_PA9 SILABS_DBUS_EUSART1_RTS(0x0, 0x9)
584 0 : #define EUSART1_RTS_PA10 SILABS_DBUS_EUSART1_RTS(0x0, 0xa)
585 0 : #define EUSART1_RTS_PA11 SILABS_DBUS_EUSART1_RTS(0x0, 0xb)
586 0 : #define EUSART1_RTS_PA12 SILABS_DBUS_EUSART1_RTS(0x0, 0xc)
587 0 : #define EUSART1_RTS_PA13 SILABS_DBUS_EUSART1_RTS(0x0, 0xd)
588 0 : #define EUSART1_RTS_PA14 SILABS_DBUS_EUSART1_RTS(0x0, 0xe)
589 0 : #define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0)
590 0 : #define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1)
591 0 : #define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2)
592 0 : #define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3)
593 0 : #define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4)
594 0 : #define EUSART1_RTS_PB5 SILABS_DBUS_EUSART1_RTS(0x1, 0x5)
595 0 : #define EUSART1_RTS_PB6 SILABS_DBUS_EUSART1_RTS(0x1, 0x6)
596 0 : #define EUSART1_RTS_PB7 SILABS_DBUS_EUSART1_RTS(0x1, 0x7)
597 0 : #define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0)
598 0 : #define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1)
599 0 : #define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2)
600 0 : #define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3)
601 0 : #define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4)
602 0 : #define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5)
603 0 : #define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6)
604 0 : #define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7)
605 0 : #define EUSART1_RTS_PC8 SILABS_DBUS_EUSART1_RTS(0x2, 0x8)
606 0 : #define EUSART1_RTS_PC9 SILABS_DBUS_EUSART1_RTS(0x2, 0x9)
607 0 : #define EUSART1_RTS_PC10 SILABS_DBUS_EUSART1_RTS(0x2, 0xa)
608 0 : #define EUSART1_RTS_PC11 SILABS_DBUS_EUSART1_RTS(0x2, 0xb)
609 0 : #define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0)
610 0 : #define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1)
611 0 : #define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2)
612 0 : #define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3)
613 0 : #define EUSART1_RTS_PD4 SILABS_DBUS_EUSART1_RTS(0x3, 0x4)
614 0 : #define EUSART1_RTS_PD5 SILABS_DBUS_EUSART1_RTS(0x3, 0x5)
615 0 : #define EUSART1_RTS_PD6 SILABS_DBUS_EUSART1_RTS(0x3, 0x6)
616 0 : #define EUSART1_RTS_PD7 SILABS_DBUS_EUSART1_RTS(0x3, 0x7)
617 0 : #define EUSART1_RTS_PD8 SILABS_DBUS_EUSART1_RTS(0x3, 0x8)
618 0 : #define EUSART1_RTS_PD9 SILABS_DBUS_EUSART1_RTS(0x3, 0x9)
619 0 : #define EUSART1_RTS_PD10 SILABS_DBUS_EUSART1_RTS(0x3, 0xa)
620 0 : #define EUSART1_RTS_PD11 SILABS_DBUS_EUSART1_RTS(0x3, 0xb)
621 0 : #define EUSART1_RTS_PD12 SILABS_DBUS_EUSART1_RTS(0x3, 0xc)
622 0 : #define EUSART1_RTS_PD13 SILABS_DBUS_EUSART1_RTS(0x3, 0xd)
623 0 : #define EUSART1_RTS_PD14 SILABS_DBUS_EUSART1_RTS(0x3, 0xe)
624 0 : #define EUSART1_RTS_PD15 SILABS_DBUS_EUSART1_RTS(0x3, 0xf)
625 0 : #define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0)
626 0 : #define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1)
627 0 : #define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2)
628 0 : #define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3)
629 0 : #define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4)
630 0 : #define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5)
631 0 : #define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6)
632 0 : #define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7)
633 0 : #define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8)
634 0 : #define EUSART1_RX_PA9 SILABS_DBUS_EUSART1_RX(0x0, 0x9)
635 0 : #define EUSART1_RX_PA10 SILABS_DBUS_EUSART1_RX(0x0, 0xa)
636 0 : #define EUSART1_RX_PA11 SILABS_DBUS_EUSART1_RX(0x0, 0xb)
637 0 : #define EUSART1_RX_PA12 SILABS_DBUS_EUSART1_RX(0x0, 0xc)
638 0 : #define EUSART1_RX_PA13 SILABS_DBUS_EUSART1_RX(0x0, 0xd)
639 0 : #define EUSART1_RX_PA14 SILABS_DBUS_EUSART1_RX(0x0, 0xe)
640 0 : #define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0)
641 0 : #define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1)
642 0 : #define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2)
643 0 : #define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3)
644 0 : #define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4)
645 0 : #define EUSART1_RX_PB5 SILABS_DBUS_EUSART1_RX(0x1, 0x5)
646 0 : #define EUSART1_RX_PB6 SILABS_DBUS_EUSART1_RX(0x1, 0x6)
647 0 : #define EUSART1_RX_PB7 SILABS_DBUS_EUSART1_RX(0x1, 0x7)
648 0 : #define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0)
649 0 : #define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1)
650 0 : #define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2)
651 0 : #define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3)
652 0 : #define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4)
653 0 : #define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5)
654 0 : #define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6)
655 0 : #define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7)
656 0 : #define EUSART1_RX_PC8 SILABS_DBUS_EUSART1_RX(0x2, 0x8)
657 0 : #define EUSART1_RX_PC9 SILABS_DBUS_EUSART1_RX(0x2, 0x9)
658 0 : #define EUSART1_RX_PC10 SILABS_DBUS_EUSART1_RX(0x2, 0xa)
659 0 : #define EUSART1_RX_PC11 SILABS_DBUS_EUSART1_RX(0x2, 0xb)
660 0 : #define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0)
661 0 : #define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1)
662 0 : #define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2)
663 0 : #define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3)
664 0 : #define EUSART1_RX_PD4 SILABS_DBUS_EUSART1_RX(0x3, 0x4)
665 0 : #define EUSART1_RX_PD5 SILABS_DBUS_EUSART1_RX(0x3, 0x5)
666 0 : #define EUSART1_RX_PD6 SILABS_DBUS_EUSART1_RX(0x3, 0x6)
667 0 : #define EUSART1_RX_PD7 SILABS_DBUS_EUSART1_RX(0x3, 0x7)
668 0 : #define EUSART1_RX_PD8 SILABS_DBUS_EUSART1_RX(0x3, 0x8)
669 0 : #define EUSART1_RX_PD9 SILABS_DBUS_EUSART1_RX(0x3, 0x9)
670 0 : #define EUSART1_RX_PD10 SILABS_DBUS_EUSART1_RX(0x3, 0xa)
671 0 : #define EUSART1_RX_PD11 SILABS_DBUS_EUSART1_RX(0x3, 0xb)
672 0 : #define EUSART1_RX_PD12 SILABS_DBUS_EUSART1_RX(0x3, 0xc)
673 0 : #define EUSART1_RX_PD13 SILABS_DBUS_EUSART1_RX(0x3, 0xd)
674 0 : #define EUSART1_RX_PD14 SILABS_DBUS_EUSART1_RX(0x3, 0xe)
675 0 : #define EUSART1_RX_PD15 SILABS_DBUS_EUSART1_RX(0x3, 0xf)
676 0 : #define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0)
677 0 : #define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1)
678 0 : #define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2)
679 0 : #define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3)
680 0 : #define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4)
681 0 : #define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5)
682 0 : #define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6)
683 0 : #define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7)
684 0 : #define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8)
685 0 : #define EUSART1_SCLK_PA9 SILABS_DBUS_EUSART1_SCLK(0x0, 0x9)
686 0 : #define EUSART1_SCLK_PA10 SILABS_DBUS_EUSART1_SCLK(0x0, 0xa)
687 0 : #define EUSART1_SCLK_PA11 SILABS_DBUS_EUSART1_SCLK(0x0, 0xb)
688 0 : #define EUSART1_SCLK_PA12 SILABS_DBUS_EUSART1_SCLK(0x0, 0xc)
689 0 : #define EUSART1_SCLK_PA13 SILABS_DBUS_EUSART1_SCLK(0x0, 0xd)
690 0 : #define EUSART1_SCLK_PA14 SILABS_DBUS_EUSART1_SCLK(0x0, 0xe)
691 0 : #define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0)
692 0 : #define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1)
693 0 : #define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2)
694 0 : #define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3)
695 0 : #define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4)
696 0 : #define EUSART1_SCLK_PB5 SILABS_DBUS_EUSART1_SCLK(0x1, 0x5)
697 0 : #define EUSART1_SCLK_PB6 SILABS_DBUS_EUSART1_SCLK(0x1, 0x6)
698 0 : #define EUSART1_SCLK_PB7 SILABS_DBUS_EUSART1_SCLK(0x1, 0x7)
699 0 : #define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0)
700 0 : #define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1)
701 0 : #define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2)
702 0 : #define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3)
703 0 : #define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4)
704 0 : #define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5)
705 0 : #define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6)
706 0 : #define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7)
707 0 : #define EUSART1_SCLK_PC8 SILABS_DBUS_EUSART1_SCLK(0x2, 0x8)
708 0 : #define EUSART1_SCLK_PC9 SILABS_DBUS_EUSART1_SCLK(0x2, 0x9)
709 0 : #define EUSART1_SCLK_PC10 SILABS_DBUS_EUSART1_SCLK(0x2, 0xa)
710 0 : #define EUSART1_SCLK_PC11 SILABS_DBUS_EUSART1_SCLK(0x2, 0xb)
711 0 : #define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0)
712 0 : #define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1)
713 0 : #define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2)
714 0 : #define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3)
715 0 : #define EUSART1_SCLK_PD4 SILABS_DBUS_EUSART1_SCLK(0x3, 0x4)
716 0 : #define EUSART1_SCLK_PD5 SILABS_DBUS_EUSART1_SCLK(0x3, 0x5)
717 0 : #define EUSART1_SCLK_PD6 SILABS_DBUS_EUSART1_SCLK(0x3, 0x6)
718 0 : #define EUSART1_SCLK_PD7 SILABS_DBUS_EUSART1_SCLK(0x3, 0x7)
719 0 : #define EUSART1_SCLK_PD8 SILABS_DBUS_EUSART1_SCLK(0x3, 0x8)
720 0 : #define EUSART1_SCLK_PD9 SILABS_DBUS_EUSART1_SCLK(0x3, 0x9)
721 0 : #define EUSART1_SCLK_PD10 SILABS_DBUS_EUSART1_SCLK(0x3, 0xa)
722 0 : #define EUSART1_SCLK_PD11 SILABS_DBUS_EUSART1_SCLK(0x3, 0xb)
723 0 : #define EUSART1_SCLK_PD12 SILABS_DBUS_EUSART1_SCLK(0x3, 0xc)
724 0 : #define EUSART1_SCLK_PD13 SILABS_DBUS_EUSART1_SCLK(0x3, 0xd)
725 0 : #define EUSART1_SCLK_PD14 SILABS_DBUS_EUSART1_SCLK(0x3, 0xe)
726 0 : #define EUSART1_SCLK_PD15 SILABS_DBUS_EUSART1_SCLK(0x3, 0xf)
727 0 : #define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0)
728 0 : #define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1)
729 0 : #define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2)
730 0 : #define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3)
731 0 : #define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4)
732 0 : #define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5)
733 0 : #define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6)
734 0 : #define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7)
735 0 : #define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8)
736 0 : #define EUSART1_TX_PA9 SILABS_DBUS_EUSART1_TX(0x0, 0x9)
737 0 : #define EUSART1_TX_PA10 SILABS_DBUS_EUSART1_TX(0x0, 0xa)
738 0 : #define EUSART1_TX_PA11 SILABS_DBUS_EUSART1_TX(0x0, 0xb)
739 0 : #define EUSART1_TX_PA12 SILABS_DBUS_EUSART1_TX(0x0, 0xc)
740 0 : #define EUSART1_TX_PA13 SILABS_DBUS_EUSART1_TX(0x0, 0xd)
741 0 : #define EUSART1_TX_PA14 SILABS_DBUS_EUSART1_TX(0x0, 0xe)
742 0 : #define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0)
743 0 : #define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1)
744 0 : #define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2)
745 0 : #define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3)
746 0 : #define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4)
747 0 : #define EUSART1_TX_PB5 SILABS_DBUS_EUSART1_TX(0x1, 0x5)
748 0 : #define EUSART1_TX_PB6 SILABS_DBUS_EUSART1_TX(0x1, 0x6)
749 0 : #define EUSART1_TX_PB7 SILABS_DBUS_EUSART1_TX(0x1, 0x7)
750 0 : #define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0)
751 0 : #define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1)
752 0 : #define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2)
753 0 : #define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3)
754 0 : #define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4)
755 0 : #define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5)
756 0 : #define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6)
757 0 : #define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7)
758 0 : #define EUSART1_TX_PC8 SILABS_DBUS_EUSART1_TX(0x2, 0x8)
759 0 : #define EUSART1_TX_PC9 SILABS_DBUS_EUSART1_TX(0x2, 0x9)
760 0 : #define EUSART1_TX_PC10 SILABS_DBUS_EUSART1_TX(0x2, 0xa)
761 0 : #define EUSART1_TX_PC11 SILABS_DBUS_EUSART1_TX(0x2, 0xb)
762 0 : #define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0)
763 0 : #define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1)
764 0 : #define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2)
765 0 : #define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3)
766 0 : #define EUSART1_TX_PD4 SILABS_DBUS_EUSART1_TX(0x3, 0x4)
767 0 : #define EUSART1_TX_PD5 SILABS_DBUS_EUSART1_TX(0x3, 0x5)
768 0 : #define EUSART1_TX_PD6 SILABS_DBUS_EUSART1_TX(0x3, 0x6)
769 0 : #define EUSART1_TX_PD7 SILABS_DBUS_EUSART1_TX(0x3, 0x7)
770 0 : #define EUSART1_TX_PD8 SILABS_DBUS_EUSART1_TX(0x3, 0x8)
771 0 : #define EUSART1_TX_PD9 SILABS_DBUS_EUSART1_TX(0x3, 0x9)
772 0 : #define EUSART1_TX_PD10 SILABS_DBUS_EUSART1_TX(0x3, 0xa)
773 0 : #define EUSART1_TX_PD11 SILABS_DBUS_EUSART1_TX(0x3, 0xb)
774 0 : #define EUSART1_TX_PD12 SILABS_DBUS_EUSART1_TX(0x3, 0xc)
775 0 : #define EUSART1_TX_PD13 SILABS_DBUS_EUSART1_TX(0x3, 0xd)
776 0 : #define EUSART1_TX_PD14 SILABS_DBUS_EUSART1_TX(0x3, 0xe)
777 0 : #define EUSART1_TX_PD15 SILABS_DBUS_EUSART1_TX(0x3, 0xf)
778 0 : #define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0)
779 0 : #define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1)
780 0 : #define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2)
781 0 : #define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3)
782 0 : #define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4)
783 0 : #define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5)
784 0 : #define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6)
785 0 : #define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7)
786 0 : #define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8)
787 0 : #define EUSART1_CTS_PA9 SILABS_DBUS_EUSART1_CTS(0x0, 0x9)
788 0 : #define EUSART1_CTS_PA10 SILABS_DBUS_EUSART1_CTS(0x0, 0xa)
789 0 : #define EUSART1_CTS_PA11 SILABS_DBUS_EUSART1_CTS(0x0, 0xb)
790 0 : #define EUSART1_CTS_PA12 SILABS_DBUS_EUSART1_CTS(0x0, 0xc)
791 0 : #define EUSART1_CTS_PA13 SILABS_DBUS_EUSART1_CTS(0x0, 0xd)
792 0 : #define EUSART1_CTS_PA14 SILABS_DBUS_EUSART1_CTS(0x0, 0xe)
793 0 : #define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0)
794 0 : #define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1)
795 0 : #define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2)
796 0 : #define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3)
797 0 : #define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4)
798 0 : #define EUSART1_CTS_PB5 SILABS_DBUS_EUSART1_CTS(0x1, 0x5)
799 0 : #define EUSART1_CTS_PB6 SILABS_DBUS_EUSART1_CTS(0x1, 0x6)
800 0 : #define EUSART1_CTS_PB7 SILABS_DBUS_EUSART1_CTS(0x1, 0x7)
801 0 : #define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0)
802 0 : #define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1)
803 0 : #define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2)
804 0 : #define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3)
805 0 : #define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4)
806 0 : #define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5)
807 0 : #define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6)
808 0 : #define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7)
809 0 : #define EUSART1_CTS_PC8 SILABS_DBUS_EUSART1_CTS(0x2, 0x8)
810 0 : #define EUSART1_CTS_PC9 SILABS_DBUS_EUSART1_CTS(0x2, 0x9)
811 0 : #define EUSART1_CTS_PC10 SILABS_DBUS_EUSART1_CTS(0x2, 0xa)
812 0 : #define EUSART1_CTS_PC11 SILABS_DBUS_EUSART1_CTS(0x2, 0xb)
813 0 : #define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0)
814 0 : #define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1)
815 0 : #define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2)
816 0 : #define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3)
817 0 : #define EUSART1_CTS_PD4 SILABS_DBUS_EUSART1_CTS(0x3, 0x4)
818 0 : #define EUSART1_CTS_PD5 SILABS_DBUS_EUSART1_CTS(0x3, 0x5)
819 0 : #define EUSART1_CTS_PD6 SILABS_DBUS_EUSART1_CTS(0x3, 0x6)
820 0 : #define EUSART1_CTS_PD7 SILABS_DBUS_EUSART1_CTS(0x3, 0x7)
821 0 : #define EUSART1_CTS_PD8 SILABS_DBUS_EUSART1_CTS(0x3, 0x8)
822 0 : #define EUSART1_CTS_PD9 SILABS_DBUS_EUSART1_CTS(0x3, 0x9)
823 0 : #define EUSART1_CTS_PD10 SILABS_DBUS_EUSART1_CTS(0x3, 0xa)
824 0 : #define EUSART1_CTS_PD11 SILABS_DBUS_EUSART1_CTS(0x3, 0xb)
825 0 : #define EUSART1_CTS_PD12 SILABS_DBUS_EUSART1_CTS(0x3, 0xc)
826 0 : #define EUSART1_CTS_PD13 SILABS_DBUS_EUSART1_CTS(0x3, 0xd)
827 0 : #define EUSART1_CTS_PD14 SILABS_DBUS_EUSART1_CTS(0x3, 0xe)
828 0 : #define EUSART1_CTS_PD15 SILABS_DBUS_EUSART1_CTS(0x3, 0xf)
829 :
830 0 : #define EUSART2_CS_PC0 SILABS_DBUS_EUSART2_CS(0x2, 0x0)
831 0 : #define EUSART2_CS_PC1 SILABS_DBUS_EUSART2_CS(0x2, 0x1)
832 0 : #define EUSART2_CS_PC2 SILABS_DBUS_EUSART2_CS(0x2, 0x2)
833 0 : #define EUSART2_CS_PC3 SILABS_DBUS_EUSART2_CS(0x2, 0x3)
834 0 : #define EUSART2_CS_PC4 SILABS_DBUS_EUSART2_CS(0x2, 0x4)
835 0 : #define EUSART2_CS_PC5 SILABS_DBUS_EUSART2_CS(0x2, 0x5)
836 0 : #define EUSART2_CS_PC6 SILABS_DBUS_EUSART2_CS(0x2, 0x6)
837 0 : #define EUSART2_CS_PC7 SILABS_DBUS_EUSART2_CS(0x2, 0x7)
838 0 : #define EUSART2_CS_PC8 SILABS_DBUS_EUSART2_CS(0x2, 0x8)
839 0 : #define EUSART2_CS_PC9 SILABS_DBUS_EUSART2_CS(0x2, 0x9)
840 0 : #define EUSART2_CS_PC10 SILABS_DBUS_EUSART2_CS(0x2, 0xa)
841 0 : #define EUSART2_CS_PC11 SILABS_DBUS_EUSART2_CS(0x2, 0xb)
842 0 : #define EUSART2_CS_PD0 SILABS_DBUS_EUSART2_CS(0x3, 0x0)
843 0 : #define EUSART2_CS_PD1 SILABS_DBUS_EUSART2_CS(0x3, 0x1)
844 0 : #define EUSART2_CS_PD2 SILABS_DBUS_EUSART2_CS(0x3, 0x2)
845 0 : #define EUSART2_CS_PD3 SILABS_DBUS_EUSART2_CS(0x3, 0x3)
846 0 : #define EUSART2_CS_PD4 SILABS_DBUS_EUSART2_CS(0x3, 0x4)
847 0 : #define EUSART2_CS_PD5 SILABS_DBUS_EUSART2_CS(0x3, 0x5)
848 0 : #define EUSART2_CS_PD6 SILABS_DBUS_EUSART2_CS(0x3, 0x6)
849 0 : #define EUSART2_CS_PD7 SILABS_DBUS_EUSART2_CS(0x3, 0x7)
850 0 : #define EUSART2_CS_PD8 SILABS_DBUS_EUSART2_CS(0x3, 0x8)
851 0 : #define EUSART2_CS_PD9 SILABS_DBUS_EUSART2_CS(0x3, 0x9)
852 0 : #define EUSART2_CS_PD10 SILABS_DBUS_EUSART2_CS(0x3, 0xa)
853 0 : #define EUSART2_CS_PD11 SILABS_DBUS_EUSART2_CS(0x3, 0xb)
854 0 : #define EUSART2_CS_PD12 SILABS_DBUS_EUSART2_CS(0x3, 0xc)
855 0 : #define EUSART2_CS_PD13 SILABS_DBUS_EUSART2_CS(0x3, 0xd)
856 0 : #define EUSART2_CS_PD14 SILABS_DBUS_EUSART2_CS(0x3, 0xe)
857 0 : #define EUSART2_CS_PD15 SILABS_DBUS_EUSART2_CS(0x3, 0xf)
858 0 : #define EUSART2_RTS_PC0 SILABS_DBUS_EUSART2_RTS(0x2, 0x0)
859 0 : #define EUSART2_RTS_PC1 SILABS_DBUS_EUSART2_RTS(0x2, 0x1)
860 0 : #define EUSART2_RTS_PC2 SILABS_DBUS_EUSART2_RTS(0x2, 0x2)
861 0 : #define EUSART2_RTS_PC3 SILABS_DBUS_EUSART2_RTS(0x2, 0x3)
862 0 : #define EUSART2_RTS_PC4 SILABS_DBUS_EUSART2_RTS(0x2, 0x4)
863 0 : #define EUSART2_RTS_PC5 SILABS_DBUS_EUSART2_RTS(0x2, 0x5)
864 0 : #define EUSART2_RTS_PC6 SILABS_DBUS_EUSART2_RTS(0x2, 0x6)
865 0 : #define EUSART2_RTS_PC7 SILABS_DBUS_EUSART2_RTS(0x2, 0x7)
866 0 : #define EUSART2_RTS_PC8 SILABS_DBUS_EUSART2_RTS(0x2, 0x8)
867 0 : #define EUSART2_RTS_PC9 SILABS_DBUS_EUSART2_RTS(0x2, 0x9)
868 0 : #define EUSART2_RTS_PC10 SILABS_DBUS_EUSART2_RTS(0x2, 0xa)
869 0 : #define EUSART2_RTS_PC11 SILABS_DBUS_EUSART2_RTS(0x2, 0xb)
870 0 : #define EUSART2_RTS_PD0 SILABS_DBUS_EUSART2_RTS(0x3, 0x0)
871 0 : #define EUSART2_RTS_PD1 SILABS_DBUS_EUSART2_RTS(0x3, 0x1)
872 0 : #define EUSART2_RTS_PD2 SILABS_DBUS_EUSART2_RTS(0x3, 0x2)
873 0 : #define EUSART2_RTS_PD3 SILABS_DBUS_EUSART2_RTS(0x3, 0x3)
874 0 : #define EUSART2_RTS_PD4 SILABS_DBUS_EUSART2_RTS(0x3, 0x4)
875 0 : #define EUSART2_RTS_PD5 SILABS_DBUS_EUSART2_RTS(0x3, 0x5)
876 0 : #define EUSART2_RTS_PD6 SILABS_DBUS_EUSART2_RTS(0x3, 0x6)
877 0 : #define EUSART2_RTS_PD7 SILABS_DBUS_EUSART2_RTS(0x3, 0x7)
878 0 : #define EUSART2_RTS_PD8 SILABS_DBUS_EUSART2_RTS(0x3, 0x8)
879 0 : #define EUSART2_RTS_PD9 SILABS_DBUS_EUSART2_RTS(0x3, 0x9)
880 0 : #define EUSART2_RTS_PD10 SILABS_DBUS_EUSART2_RTS(0x3, 0xa)
881 0 : #define EUSART2_RTS_PD11 SILABS_DBUS_EUSART2_RTS(0x3, 0xb)
882 0 : #define EUSART2_RTS_PD12 SILABS_DBUS_EUSART2_RTS(0x3, 0xc)
883 0 : #define EUSART2_RTS_PD13 SILABS_DBUS_EUSART2_RTS(0x3, 0xd)
884 0 : #define EUSART2_RTS_PD14 SILABS_DBUS_EUSART2_RTS(0x3, 0xe)
885 0 : #define EUSART2_RTS_PD15 SILABS_DBUS_EUSART2_RTS(0x3, 0xf)
886 0 : #define EUSART2_RX_PC0 SILABS_DBUS_EUSART2_RX(0x2, 0x0)
887 0 : #define EUSART2_RX_PC1 SILABS_DBUS_EUSART2_RX(0x2, 0x1)
888 0 : #define EUSART2_RX_PC2 SILABS_DBUS_EUSART2_RX(0x2, 0x2)
889 0 : #define EUSART2_RX_PC3 SILABS_DBUS_EUSART2_RX(0x2, 0x3)
890 0 : #define EUSART2_RX_PC4 SILABS_DBUS_EUSART2_RX(0x2, 0x4)
891 0 : #define EUSART2_RX_PC5 SILABS_DBUS_EUSART2_RX(0x2, 0x5)
892 0 : #define EUSART2_RX_PC6 SILABS_DBUS_EUSART2_RX(0x2, 0x6)
893 0 : #define EUSART2_RX_PC7 SILABS_DBUS_EUSART2_RX(0x2, 0x7)
894 0 : #define EUSART2_RX_PC8 SILABS_DBUS_EUSART2_RX(0x2, 0x8)
895 0 : #define EUSART2_RX_PC9 SILABS_DBUS_EUSART2_RX(0x2, 0x9)
896 0 : #define EUSART2_RX_PC10 SILABS_DBUS_EUSART2_RX(0x2, 0xa)
897 0 : #define EUSART2_RX_PC11 SILABS_DBUS_EUSART2_RX(0x2, 0xb)
898 0 : #define EUSART2_RX_PD0 SILABS_DBUS_EUSART2_RX(0x3, 0x0)
899 0 : #define EUSART2_RX_PD1 SILABS_DBUS_EUSART2_RX(0x3, 0x1)
900 0 : #define EUSART2_RX_PD2 SILABS_DBUS_EUSART2_RX(0x3, 0x2)
901 0 : #define EUSART2_RX_PD3 SILABS_DBUS_EUSART2_RX(0x3, 0x3)
902 0 : #define EUSART2_RX_PD4 SILABS_DBUS_EUSART2_RX(0x3, 0x4)
903 0 : #define EUSART2_RX_PD5 SILABS_DBUS_EUSART2_RX(0x3, 0x5)
904 0 : #define EUSART2_RX_PD6 SILABS_DBUS_EUSART2_RX(0x3, 0x6)
905 0 : #define EUSART2_RX_PD7 SILABS_DBUS_EUSART2_RX(0x3, 0x7)
906 0 : #define EUSART2_RX_PD8 SILABS_DBUS_EUSART2_RX(0x3, 0x8)
907 0 : #define EUSART2_RX_PD9 SILABS_DBUS_EUSART2_RX(0x3, 0x9)
908 0 : #define EUSART2_RX_PD10 SILABS_DBUS_EUSART2_RX(0x3, 0xa)
909 0 : #define EUSART2_RX_PD11 SILABS_DBUS_EUSART2_RX(0x3, 0xb)
910 0 : #define EUSART2_RX_PD12 SILABS_DBUS_EUSART2_RX(0x3, 0xc)
911 0 : #define EUSART2_RX_PD13 SILABS_DBUS_EUSART2_RX(0x3, 0xd)
912 0 : #define EUSART2_RX_PD14 SILABS_DBUS_EUSART2_RX(0x3, 0xe)
913 0 : #define EUSART2_RX_PD15 SILABS_DBUS_EUSART2_RX(0x3, 0xf)
914 0 : #define EUSART2_SCLK_PC0 SILABS_DBUS_EUSART2_SCLK(0x2, 0x0)
915 0 : #define EUSART2_SCLK_PC1 SILABS_DBUS_EUSART2_SCLK(0x2, 0x1)
916 0 : #define EUSART2_SCLK_PC2 SILABS_DBUS_EUSART2_SCLK(0x2, 0x2)
917 0 : #define EUSART2_SCLK_PC3 SILABS_DBUS_EUSART2_SCLK(0x2, 0x3)
918 0 : #define EUSART2_SCLK_PC4 SILABS_DBUS_EUSART2_SCLK(0x2, 0x4)
919 0 : #define EUSART2_SCLK_PC5 SILABS_DBUS_EUSART2_SCLK(0x2, 0x5)
920 0 : #define EUSART2_SCLK_PC6 SILABS_DBUS_EUSART2_SCLK(0x2, 0x6)
921 0 : #define EUSART2_SCLK_PC7 SILABS_DBUS_EUSART2_SCLK(0x2, 0x7)
922 0 : #define EUSART2_SCLK_PC8 SILABS_DBUS_EUSART2_SCLK(0x2, 0x8)
923 0 : #define EUSART2_SCLK_PC9 SILABS_DBUS_EUSART2_SCLK(0x2, 0x9)
924 0 : #define EUSART2_SCLK_PC10 SILABS_DBUS_EUSART2_SCLK(0x2, 0xa)
925 0 : #define EUSART2_SCLK_PC11 SILABS_DBUS_EUSART2_SCLK(0x2, 0xb)
926 0 : #define EUSART2_SCLK_PD0 SILABS_DBUS_EUSART2_SCLK(0x3, 0x0)
927 0 : #define EUSART2_SCLK_PD1 SILABS_DBUS_EUSART2_SCLK(0x3, 0x1)
928 0 : #define EUSART2_SCLK_PD2 SILABS_DBUS_EUSART2_SCLK(0x3, 0x2)
929 0 : #define EUSART2_SCLK_PD3 SILABS_DBUS_EUSART2_SCLK(0x3, 0x3)
930 0 : #define EUSART2_SCLK_PD4 SILABS_DBUS_EUSART2_SCLK(0x3, 0x4)
931 0 : #define EUSART2_SCLK_PD5 SILABS_DBUS_EUSART2_SCLK(0x3, 0x5)
932 0 : #define EUSART2_SCLK_PD6 SILABS_DBUS_EUSART2_SCLK(0x3, 0x6)
933 0 : #define EUSART2_SCLK_PD7 SILABS_DBUS_EUSART2_SCLK(0x3, 0x7)
934 0 : #define EUSART2_SCLK_PD8 SILABS_DBUS_EUSART2_SCLK(0x3, 0x8)
935 0 : #define EUSART2_SCLK_PD9 SILABS_DBUS_EUSART2_SCLK(0x3, 0x9)
936 0 : #define EUSART2_SCLK_PD10 SILABS_DBUS_EUSART2_SCLK(0x3, 0xa)
937 0 : #define EUSART2_SCLK_PD11 SILABS_DBUS_EUSART2_SCLK(0x3, 0xb)
938 0 : #define EUSART2_SCLK_PD12 SILABS_DBUS_EUSART2_SCLK(0x3, 0xc)
939 0 : #define EUSART2_SCLK_PD13 SILABS_DBUS_EUSART2_SCLK(0x3, 0xd)
940 0 : #define EUSART2_SCLK_PD14 SILABS_DBUS_EUSART2_SCLK(0x3, 0xe)
941 0 : #define EUSART2_SCLK_PD15 SILABS_DBUS_EUSART2_SCLK(0x3, 0xf)
942 0 : #define EUSART2_TX_PC0 SILABS_DBUS_EUSART2_TX(0x2, 0x0)
943 0 : #define EUSART2_TX_PC1 SILABS_DBUS_EUSART2_TX(0x2, 0x1)
944 0 : #define EUSART2_TX_PC2 SILABS_DBUS_EUSART2_TX(0x2, 0x2)
945 0 : #define EUSART2_TX_PC3 SILABS_DBUS_EUSART2_TX(0x2, 0x3)
946 0 : #define EUSART2_TX_PC4 SILABS_DBUS_EUSART2_TX(0x2, 0x4)
947 0 : #define EUSART2_TX_PC5 SILABS_DBUS_EUSART2_TX(0x2, 0x5)
948 0 : #define EUSART2_TX_PC6 SILABS_DBUS_EUSART2_TX(0x2, 0x6)
949 0 : #define EUSART2_TX_PC7 SILABS_DBUS_EUSART2_TX(0x2, 0x7)
950 0 : #define EUSART2_TX_PC8 SILABS_DBUS_EUSART2_TX(0x2, 0x8)
951 0 : #define EUSART2_TX_PC9 SILABS_DBUS_EUSART2_TX(0x2, 0x9)
952 0 : #define EUSART2_TX_PC10 SILABS_DBUS_EUSART2_TX(0x2, 0xa)
953 0 : #define EUSART2_TX_PC11 SILABS_DBUS_EUSART2_TX(0x2, 0xb)
954 0 : #define EUSART2_TX_PD0 SILABS_DBUS_EUSART2_TX(0x3, 0x0)
955 0 : #define EUSART2_TX_PD1 SILABS_DBUS_EUSART2_TX(0x3, 0x1)
956 0 : #define EUSART2_TX_PD2 SILABS_DBUS_EUSART2_TX(0x3, 0x2)
957 0 : #define EUSART2_TX_PD3 SILABS_DBUS_EUSART2_TX(0x3, 0x3)
958 0 : #define EUSART2_TX_PD4 SILABS_DBUS_EUSART2_TX(0x3, 0x4)
959 0 : #define EUSART2_TX_PD5 SILABS_DBUS_EUSART2_TX(0x3, 0x5)
960 0 : #define EUSART2_TX_PD6 SILABS_DBUS_EUSART2_TX(0x3, 0x6)
961 0 : #define EUSART2_TX_PD7 SILABS_DBUS_EUSART2_TX(0x3, 0x7)
962 0 : #define EUSART2_TX_PD8 SILABS_DBUS_EUSART2_TX(0x3, 0x8)
963 0 : #define EUSART2_TX_PD9 SILABS_DBUS_EUSART2_TX(0x3, 0x9)
964 0 : #define EUSART2_TX_PD10 SILABS_DBUS_EUSART2_TX(0x3, 0xa)
965 0 : #define EUSART2_TX_PD11 SILABS_DBUS_EUSART2_TX(0x3, 0xb)
966 0 : #define EUSART2_TX_PD12 SILABS_DBUS_EUSART2_TX(0x3, 0xc)
967 0 : #define EUSART2_TX_PD13 SILABS_DBUS_EUSART2_TX(0x3, 0xd)
968 0 : #define EUSART2_TX_PD14 SILABS_DBUS_EUSART2_TX(0x3, 0xe)
969 0 : #define EUSART2_TX_PD15 SILABS_DBUS_EUSART2_TX(0x3, 0xf)
970 0 : #define EUSART2_CTS_PC0 SILABS_DBUS_EUSART2_CTS(0x2, 0x0)
971 0 : #define EUSART2_CTS_PC1 SILABS_DBUS_EUSART2_CTS(0x2, 0x1)
972 0 : #define EUSART2_CTS_PC2 SILABS_DBUS_EUSART2_CTS(0x2, 0x2)
973 0 : #define EUSART2_CTS_PC3 SILABS_DBUS_EUSART2_CTS(0x2, 0x3)
974 0 : #define EUSART2_CTS_PC4 SILABS_DBUS_EUSART2_CTS(0x2, 0x4)
975 0 : #define EUSART2_CTS_PC5 SILABS_DBUS_EUSART2_CTS(0x2, 0x5)
976 0 : #define EUSART2_CTS_PC6 SILABS_DBUS_EUSART2_CTS(0x2, 0x6)
977 0 : #define EUSART2_CTS_PC7 SILABS_DBUS_EUSART2_CTS(0x2, 0x7)
978 0 : #define EUSART2_CTS_PC8 SILABS_DBUS_EUSART2_CTS(0x2, 0x8)
979 0 : #define EUSART2_CTS_PC9 SILABS_DBUS_EUSART2_CTS(0x2, 0x9)
980 0 : #define EUSART2_CTS_PC10 SILABS_DBUS_EUSART2_CTS(0x2, 0xa)
981 0 : #define EUSART2_CTS_PC11 SILABS_DBUS_EUSART2_CTS(0x2, 0xb)
982 0 : #define EUSART2_CTS_PD0 SILABS_DBUS_EUSART2_CTS(0x3, 0x0)
983 0 : #define EUSART2_CTS_PD1 SILABS_DBUS_EUSART2_CTS(0x3, 0x1)
984 0 : #define EUSART2_CTS_PD2 SILABS_DBUS_EUSART2_CTS(0x3, 0x2)
985 0 : #define EUSART2_CTS_PD3 SILABS_DBUS_EUSART2_CTS(0x3, 0x3)
986 0 : #define EUSART2_CTS_PD4 SILABS_DBUS_EUSART2_CTS(0x3, 0x4)
987 0 : #define EUSART2_CTS_PD5 SILABS_DBUS_EUSART2_CTS(0x3, 0x5)
988 0 : #define EUSART2_CTS_PD6 SILABS_DBUS_EUSART2_CTS(0x3, 0x6)
989 0 : #define EUSART2_CTS_PD7 SILABS_DBUS_EUSART2_CTS(0x3, 0x7)
990 0 : #define EUSART2_CTS_PD8 SILABS_DBUS_EUSART2_CTS(0x3, 0x8)
991 0 : #define EUSART2_CTS_PD9 SILABS_DBUS_EUSART2_CTS(0x3, 0x9)
992 0 : #define EUSART2_CTS_PD10 SILABS_DBUS_EUSART2_CTS(0x3, 0xa)
993 0 : #define EUSART2_CTS_PD11 SILABS_DBUS_EUSART2_CTS(0x3, 0xb)
994 0 : #define EUSART2_CTS_PD12 SILABS_DBUS_EUSART2_CTS(0x3, 0xc)
995 0 : #define EUSART2_CTS_PD13 SILABS_DBUS_EUSART2_CTS(0x3, 0xd)
996 0 : #define EUSART2_CTS_PD14 SILABS_DBUS_EUSART2_CTS(0x3, 0xe)
997 0 : #define EUSART2_CTS_PD15 SILABS_DBUS_EUSART2_CTS(0x3, 0xf)
998 :
999 0 : #define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0)
1000 0 : #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
1001 0 : #define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2)
1002 0 : #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
1003 0 : #define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4)
1004 0 : #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
1005 0 : #define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6)
1006 0 : #define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7)
1007 0 : #define PTI_DCLK_PC8 SILABS_DBUS_PTI_DCLK(0x2, 0x8)
1008 0 : #define PTI_DCLK_PC9 SILABS_DBUS_PTI_DCLK(0x2, 0x9)
1009 0 : #define PTI_DCLK_PC10 SILABS_DBUS_PTI_DCLK(0x2, 0xa)
1010 0 : #define PTI_DCLK_PC11 SILABS_DBUS_PTI_DCLK(0x2, 0xb)
1011 0 : #define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0)
1012 0 : #define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1)
1013 0 : #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
1014 0 : #define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3)
1015 0 : #define PTI_DCLK_PD4 SILABS_DBUS_PTI_DCLK(0x3, 0x4)
1016 0 : #define PTI_DCLK_PD5 SILABS_DBUS_PTI_DCLK(0x3, 0x5)
1017 0 : #define PTI_DCLK_PD6 SILABS_DBUS_PTI_DCLK(0x3, 0x6)
1018 0 : #define PTI_DCLK_PD7 SILABS_DBUS_PTI_DCLK(0x3, 0x7)
1019 0 : #define PTI_DCLK_PD8 SILABS_DBUS_PTI_DCLK(0x3, 0x8)
1020 0 : #define PTI_DCLK_PD9 SILABS_DBUS_PTI_DCLK(0x3, 0x9)
1021 0 : #define PTI_DCLK_PD10 SILABS_DBUS_PTI_DCLK(0x3, 0xa)
1022 0 : #define PTI_DCLK_PD11 SILABS_DBUS_PTI_DCLK(0x3, 0xb)
1023 0 : #define PTI_DCLK_PD12 SILABS_DBUS_PTI_DCLK(0x3, 0xc)
1024 0 : #define PTI_DCLK_PD13 SILABS_DBUS_PTI_DCLK(0x3, 0xd)
1025 0 : #define PTI_DCLK_PD14 SILABS_DBUS_PTI_DCLK(0x3, 0xe)
1026 0 : #define PTI_DCLK_PD15 SILABS_DBUS_PTI_DCLK(0x3, 0xf)
1027 0 : #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
1028 0 : #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
1029 0 : #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
1030 0 : #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
1031 0 : #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
1032 0 : #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
1033 0 : #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
1034 0 : #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
1035 0 : #define PTI_DFRAME_PC8 SILABS_DBUS_PTI_DFRAME(0x2, 0x8)
1036 0 : #define PTI_DFRAME_PC9 SILABS_DBUS_PTI_DFRAME(0x2, 0x9)
1037 0 : #define PTI_DFRAME_PC10 SILABS_DBUS_PTI_DFRAME(0x2, 0xa)
1038 0 : #define PTI_DFRAME_PC11 SILABS_DBUS_PTI_DFRAME(0x2, 0xb)
1039 0 : #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
1040 0 : #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
1041 0 : #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
1042 0 : #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
1043 0 : #define PTI_DFRAME_PD4 SILABS_DBUS_PTI_DFRAME(0x3, 0x4)
1044 0 : #define PTI_DFRAME_PD5 SILABS_DBUS_PTI_DFRAME(0x3, 0x5)
1045 0 : #define PTI_DFRAME_PD6 SILABS_DBUS_PTI_DFRAME(0x3, 0x6)
1046 0 : #define PTI_DFRAME_PD7 SILABS_DBUS_PTI_DFRAME(0x3, 0x7)
1047 0 : #define PTI_DFRAME_PD8 SILABS_DBUS_PTI_DFRAME(0x3, 0x8)
1048 0 : #define PTI_DFRAME_PD9 SILABS_DBUS_PTI_DFRAME(0x3, 0x9)
1049 0 : #define PTI_DFRAME_PD10 SILABS_DBUS_PTI_DFRAME(0x3, 0xa)
1050 0 : #define PTI_DFRAME_PD11 SILABS_DBUS_PTI_DFRAME(0x3, 0xb)
1051 0 : #define PTI_DFRAME_PD12 SILABS_DBUS_PTI_DFRAME(0x3, 0xc)
1052 0 : #define PTI_DFRAME_PD13 SILABS_DBUS_PTI_DFRAME(0x3, 0xd)
1053 0 : #define PTI_DFRAME_PD14 SILABS_DBUS_PTI_DFRAME(0x3, 0xe)
1054 0 : #define PTI_DFRAME_PD15 SILABS_DBUS_PTI_DFRAME(0x3, 0xf)
1055 0 : #define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0)
1056 0 : #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
1057 0 : #define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2)
1058 0 : #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
1059 0 : #define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4)
1060 0 : #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
1061 0 : #define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6)
1062 0 : #define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7)
1063 0 : #define PTI_DOUT_PC8 SILABS_DBUS_PTI_DOUT(0x2, 0x8)
1064 0 : #define PTI_DOUT_PC9 SILABS_DBUS_PTI_DOUT(0x2, 0x9)
1065 0 : #define PTI_DOUT_PC10 SILABS_DBUS_PTI_DOUT(0x2, 0xa)
1066 0 : #define PTI_DOUT_PC11 SILABS_DBUS_PTI_DOUT(0x2, 0xb)
1067 0 : #define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0)
1068 0 : #define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1)
1069 0 : #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
1070 0 : #define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3)
1071 0 : #define PTI_DOUT_PD4 SILABS_DBUS_PTI_DOUT(0x3, 0x4)
1072 0 : #define PTI_DOUT_PD5 SILABS_DBUS_PTI_DOUT(0x3, 0x5)
1073 0 : #define PTI_DOUT_PD6 SILABS_DBUS_PTI_DOUT(0x3, 0x6)
1074 0 : #define PTI_DOUT_PD7 SILABS_DBUS_PTI_DOUT(0x3, 0x7)
1075 0 : #define PTI_DOUT_PD8 SILABS_DBUS_PTI_DOUT(0x3, 0x8)
1076 0 : #define PTI_DOUT_PD9 SILABS_DBUS_PTI_DOUT(0x3, 0x9)
1077 0 : #define PTI_DOUT_PD10 SILABS_DBUS_PTI_DOUT(0x3, 0xa)
1078 0 : #define PTI_DOUT_PD11 SILABS_DBUS_PTI_DOUT(0x3, 0xb)
1079 0 : #define PTI_DOUT_PD12 SILABS_DBUS_PTI_DOUT(0x3, 0xc)
1080 0 : #define PTI_DOUT_PD13 SILABS_DBUS_PTI_DOUT(0x3, 0xd)
1081 0 : #define PTI_DOUT_PD14 SILABS_DBUS_PTI_DOUT(0x3, 0xe)
1082 0 : #define PTI_DOUT_PD15 SILABS_DBUS_PTI_DOUT(0x3, 0xf)
1083 :
1084 0 : #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
1085 0 : #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
1086 0 : #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
1087 0 : #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
1088 0 : #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
1089 0 : #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
1090 0 : #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
1091 0 : #define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
1092 0 : #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
1093 0 : #define I2C0_SCL_PA9 SILABS_DBUS_I2C0_SCL(0x0, 0x9)
1094 0 : #define I2C0_SCL_PA10 SILABS_DBUS_I2C0_SCL(0x0, 0xa)
1095 0 : #define I2C0_SCL_PA11 SILABS_DBUS_I2C0_SCL(0x0, 0xb)
1096 0 : #define I2C0_SCL_PA12 SILABS_DBUS_I2C0_SCL(0x0, 0xc)
1097 0 : #define I2C0_SCL_PA13 SILABS_DBUS_I2C0_SCL(0x0, 0xd)
1098 0 : #define I2C0_SCL_PA14 SILABS_DBUS_I2C0_SCL(0x0, 0xe)
1099 0 : #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
1100 0 : #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
1101 0 : #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
1102 0 : #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
1103 0 : #define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
1104 0 : #define I2C0_SCL_PB5 SILABS_DBUS_I2C0_SCL(0x1, 0x5)
1105 0 : #define I2C0_SCL_PB6 SILABS_DBUS_I2C0_SCL(0x1, 0x6)
1106 0 : #define I2C0_SCL_PB7 SILABS_DBUS_I2C0_SCL(0x1, 0x7)
1107 0 : #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
1108 0 : #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
1109 0 : #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
1110 0 : #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
1111 0 : #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
1112 0 : #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
1113 0 : #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
1114 0 : #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
1115 0 : #define I2C0_SCL_PC8 SILABS_DBUS_I2C0_SCL(0x2, 0x8)
1116 0 : #define I2C0_SCL_PC9 SILABS_DBUS_I2C0_SCL(0x2, 0x9)
1117 0 : #define I2C0_SCL_PC10 SILABS_DBUS_I2C0_SCL(0x2, 0xa)
1118 0 : #define I2C0_SCL_PC11 SILABS_DBUS_I2C0_SCL(0x2, 0xb)
1119 0 : #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
1120 0 : #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
1121 0 : #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
1122 0 : #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
1123 0 : #define I2C0_SCL_PD4 SILABS_DBUS_I2C0_SCL(0x3, 0x4)
1124 0 : #define I2C0_SCL_PD5 SILABS_DBUS_I2C0_SCL(0x3, 0x5)
1125 0 : #define I2C0_SCL_PD6 SILABS_DBUS_I2C0_SCL(0x3, 0x6)
1126 0 : #define I2C0_SCL_PD7 SILABS_DBUS_I2C0_SCL(0x3, 0x7)
1127 0 : #define I2C0_SCL_PD8 SILABS_DBUS_I2C0_SCL(0x3, 0x8)
1128 0 : #define I2C0_SCL_PD9 SILABS_DBUS_I2C0_SCL(0x3, 0x9)
1129 0 : #define I2C0_SCL_PD10 SILABS_DBUS_I2C0_SCL(0x3, 0xa)
1130 0 : #define I2C0_SCL_PD11 SILABS_DBUS_I2C0_SCL(0x3, 0xb)
1131 0 : #define I2C0_SCL_PD12 SILABS_DBUS_I2C0_SCL(0x3, 0xc)
1132 0 : #define I2C0_SCL_PD13 SILABS_DBUS_I2C0_SCL(0x3, 0xd)
1133 0 : #define I2C0_SCL_PD14 SILABS_DBUS_I2C0_SCL(0x3, 0xe)
1134 0 : #define I2C0_SCL_PD15 SILABS_DBUS_I2C0_SCL(0x3, 0xf)
1135 0 : #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
1136 0 : #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
1137 0 : #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
1138 0 : #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
1139 0 : #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
1140 0 : #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
1141 0 : #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
1142 0 : #define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
1143 0 : #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
1144 0 : #define I2C0_SDA_PA9 SILABS_DBUS_I2C0_SDA(0x0, 0x9)
1145 0 : #define I2C0_SDA_PA10 SILABS_DBUS_I2C0_SDA(0x0, 0xa)
1146 0 : #define I2C0_SDA_PA11 SILABS_DBUS_I2C0_SDA(0x0, 0xb)
1147 0 : #define I2C0_SDA_PA12 SILABS_DBUS_I2C0_SDA(0x0, 0xc)
1148 0 : #define I2C0_SDA_PA13 SILABS_DBUS_I2C0_SDA(0x0, 0xd)
1149 0 : #define I2C0_SDA_PA14 SILABS_DBUS_I2C0_SDA(0x0, 0xe)
1150 0 : #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
1151 0 : #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
1152 0 : #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
1153 0 : #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
1154 0 : #define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
1155 0 : #define I2C0_SDA_PB5 SILABS_DBUS_I2C0_SDA(0x1, 0x5)
1156 0 : #define I2C0_SDA_PB6 SILABS_DBUS_I2C0_SDA(0x1, 0x6)
1157 0 : #define I2C0_SDA_PB7 SILABS_DBUS_I2C0_SDA(0x1, 0x7)
1158 0 : #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
1159 0 : #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
1160 0 : #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
1161 0 : #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
1162 0 : #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
1163 0 : #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
1164 0 : #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
1165 0 : #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
1166 0 : #define I2C0_SDA_PC8 SILABS_DBUS_I2C0_SDA(0x2, 0x8)
1167 0 : #define I2C0_SDA_PC9 SILABS_DBUS_I2C0_SDA(0x2, 0x9)
1168 0 : #define I2C0_SDA_PC10 SILABS_DBUS_I2C0_SDA(0x2, 0xa)
1169 0 : #define I2C0_SDA_PC11 SILABS_DBUS_I2C0_SDA(0x2, 0xb)
1170 0 : #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
1171 0 : #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
1172 0 : #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
1173 0 : #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
1174 0 : #define I2C0_SDA_PD4 SILABS_DBUS_I2C0_SDA(0x3, 0x4)
1175 0 : #define I2C0_SDA_PD5 SILABS_DBUS_I2C0_SDA(0x3, 0x5)
1176 0 : #define I2C0_SDA_PD6 SILABS_DBUS_I2C0_SDA(0x3, 0x6)
1177 0 : #define I2C0_SDA_PD7 SILABS_DBUS_I2C0_SDA(0x3, 0x7)
1178 0 : #define I2C0_SDA_PD8 SILABS_DBUS_I2C0_SDA(0x3, 0x8)
1179 0 : #define I2C0_SDA_PD9 SILABS_DBUS_I2C0_SDA(0x3, 0x9)
1180 0 : #define I2C0_SDA_PD10 SILABS_DBUS_I2C0_SDA(0x3, 0xa)
1181 0 : #define I2C0_SDA_PD11 SILABS_DBUS_I2C0_SDA(0x3, 0xb)
1182 0 : #define I2C0_SDA_PD12 SILABS_DBUS_I2C0_SDA(0x3, 0xc)
1183 0 : #define I2C0_SDA_PD13 SILABS_DBUS_I2C0_SDA(0x3, 0xd)
1184 0 : #define I2C0_SDA_PD14 SILABS_DBUS_I2C0_SDA(0x3, 0xe)
1185 0 : #define I2C0_SDA_PD15 SILABS_DBUS_I2C0_SDA(0x3, 0xf)
1186 :
1187 0 : #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
1188 0 : #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
1189 0 : #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
1190 0 : #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
1191 0 : #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
1192 0 : #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
1193 0 : #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
1194 0 : #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
1195 0 : #define I2C1_SCL_PC8 SILABS_DBUS_I2C1_SCL(0x2, 0x8)
1196 0 : #define I2C1_SCL_PC9 SILABS_DBUS_I2C1_SCL(0x2, 0x9)
1197 0 : #define I2C1_SCL_PC10 SILABS_DBUS_I2C1_SCL(0x2, 0xa)
1198 0 : #define I2C1_SCL_PC11 SILABS_DBUS_I2C1_SCL(0x2, 0xb)
1199 0 : #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
1200 0 : #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
1201 0 : #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
1202 0 : #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
1203 0 : #define I2C1_SCL_PD4 SILABS_DBUS_I2C1_SCL(0x3, 0x4)
1204 0 : #define I2C1_SCL_PD5 SILABS_DBUS_I2C1_SCL(0x3, 0x5)
1205 0 : #define I2C1_SCL_PD6 SILABS_DBUS_I2C1_SCL(0x3, 0x6)
1206 0 : #define I2C1_SCL_PD7 SILABS_DBUS_I2C1_SCL(0x3, 0x7)
1207 0 : #define I2C1_SCL_PD8 SILABS_DBUS_I2C1_SCL(0x3, 0x8)
1208 0 : #define I2C1_SCL_PD9 SILABS_DBUS_I2C1_SCL(0x3, 0x9)
1209 0 : #define I2C1_SCL_PD10 SILABS_DBUS_I2C1_SCL(0x3, 0xa)
1210 0 : #define I2C1_SCL_PD11 SILABS_DBUS_I2C1_SCL(0x3, 0xb)
1211 0 : #define I2C1_SCL_PD12 SILABS_DBUS_I2C1_SCL(0x3, 0xc)
1212 0 : #define I2C1_SCL_PD13 SILABS_DBUS_I2C1_SCL(0x3, 0xd)
1213 0 : #define I2C1_SCL_PD14 SILABS_DBUS_I2C1_SCL(0x3, 0xe)
1214 0 : #define I2C1_SCL_PD15 SILABS_DBUS_I2C1_SCL(0x3, 0xf)
1215 0 : #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
1216 0 : #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
1217 0 : #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
1218 0 : #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
1219 0 : #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
1220 0 : #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
1221 0 : #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
1222 0 : #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
1223 0 : #define I2C1_SDA_PC8 SILABS_DBUS_I2C1_SDA(0x2, 0x8)
1224 0 : #define I2C1_SDA_PC9 SILABS_DBUS_I2C1_SDA(0x2, 0x9)
1225 0 : #define I2C1_SDA_PC10 SILABS_DBUS_I2C1_SDA(0x2, 0xa)
1226 0 : #define I2C1_SDA_PC11 SILABS_DBUS_I2C1_SDA(0x2, 0xb)
1227 0 : #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
1228 0 : #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
1229 0 : #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
1230 0 : #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
1231 0 : #define I2C1_SDA_PD4 SILABS_DBUS_I2C1_SDA(0x3, 0x4)
1232 0 : #define I2C1_SDA_PD5 SILABS_DBUS_I2C1_SDA(0x3, 0x5)
1233 0 : #define I2C1_SDA_PD6 SILABS_DBUS_I2C1_SDA(0x3, 0x6)
1234 0 : #define I2C1_SDA_PD7 SILABS_DBUS_I2C1_SDA(0x3, 0x7)
1235 0 : #define I2C1_SDA_PD8 SILABS_DBUS_I2C1_SDA(0x3, 0x8)
1236 0 : #define I2C1_SDA_PD9 SILABS_DBUS_I2C1_SDA(0x3, 0x9)
1237 0 : #define I2C1_SDA_PD10 SILABS_DBUS_I2C1_SDA(0x3, 0xa)
1238 0 : #define I2C1_SDA_PD11 SILABS_DBUS_I2C1_SDA(0x3, 0xb)
1239 0 : #define I2C1_SDA_PD12 SILABS_DBUS_I2C1_SDA(0x3, 0xc)
1240 0 : #define I2C1_SDA_PD13 SILABS_DBUS_I2C1_SDA(0x3, 0xd)
1241 0 : #define I2C1_SDA_PD14 SILABS_DBUS_I2C1_SDA(0x3, 0xe)
1242 0 : #define I2C1_SDA_PD15 SILABS_DBUS_I2C1_SDA(0x3, 0xf)
1243 :
1244 0 : #define KEYSCAN_COLOUT0_PA0 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x0)
1245 0 : #define KEYSCAN_COLOUT0_PA1 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x1)
1246 0 : #define KEYSCAN_COLOUT0_PA2 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x2)
1247 0 : #define KEYSCAN_COLOUT0_PA3 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x3)
1248 0 : #define KEYSCAN_COLOUT0_PA4 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x4)
1249 0 : #define KEYSCAN_COLOUT0_PA5 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x5)
1250 0 : #define KEYSCAN_COLOUT0_PA6 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x6)
1251 0 : #define KEYSCAN_COLOUT0_PA7 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x7)
1252 0 : #define KEYSCAN_COLOUT0_PA8 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x8)
1253 0 : #define KEYSCAN_COLOUT0_PA9 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x9)
1254 0 : #define KEYSCAN_COLOUT0_PA10 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xa)
1255 0 : #define KEYSCAN_COLOUT0_PA11 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xb)
1256 0 : #define KEYSCAN_COLOUT0_PA12 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xc)
1257 0 : #define KEYSCAN_COLOUT0_PA13 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xd)
1258 0 : #define KEYSCAN_COLOUT0_PA14 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xe)
1259 0 : #define KEYSCAN_COLOUT0_PB0 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x0)
1260 0 : #define KEYSCAN_COLOUT0_PB1 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x1)
1261 0 : #define KEYSCAN_COLOUT0_PB2 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x2)
1262 0 : #define KEYSCAN_COLOUT0_PB3 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x3)
1263 0 : #define KEYSCAN_COLOUT0_PB4 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x4)
1264 0 : #define KEYSCAN_COLOUT0_PB5 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x5)
1265 0 : #define KEYSCAN_COLOUT0_PB6 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x6)
1266 0 : #define KEYSCAN_COLOUT0_PB7 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x7)
1267 0 : #define KEYSCAN_COLOUT0_PC0 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x0)
1268 0 : #define KEYSCAN_COLOUT0_PC1 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x1)
1269 0 : #define KEYSCAN_COLOUT0_PC2 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x2)
1270 0 : #define KEYSCAN_COLOUT0_PC3 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x3)
1271 0 : #define KEYSCAN_COLOUT0_PC4 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x4)
1272 0 : #define KEYSCAN_COLOUT0_PC5 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x5)
1273 0 : #define KEYSCAN_COLOUT0_PC6 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x6)
1274 0 : #define KEYSCAN_COLOUT0_PC7 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x7)
1275 0 : #define KEYSCAN_COLOUT0_PC8 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x8)
1276 0 : #define KEYSCAN_COLOUT0_PC9 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x9)
1277 0 : #define KEYSCAN_COLOUT0_PC10 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xa)
1278 0 : #define KEYSCAN_COLOUT0_PC11 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xb)
1279 0 : #define KEYSCAN_COLOUT0_PD0 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x0)
1280 0 : #define KEYSCAN_COLOUT0_PD1 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x1)
1281 0 : #define KEYSCAN_COLOUT0_PD2 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x2)
1282 0 : #define KEYSCAN_COLOUT0_PD3 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x3)
1283 0 : #define KEYSCAN_COLOUT0_PD4 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x4)
1284 0 : #define KEYSCAN_COLOUT0_PD5 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x5)
1285 0 : #define KEYSCAN_COLOUT0_PD6 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x6)
1286 0 : #define KEYSCAN_COLOUT0_PD7 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x7)
1287 0 : #define KEYSCAN_COLOUT0_PD8 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x8)
1288 0 : #define KEYSCAN_COLOUT0_PD9 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x9)
1289 0 : #define KEYSCAN_COLOUT0_PD10 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xa)
1290 0 : #define KEYSCAN_COLOUT0_PD11 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xb)
1291 0 : #define KEYSCAN_COLOUT0_PD12 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xc)
1292 0 : #define KEYSCAN_COLOUT0_PD13 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xd)
1293 0 : #define KEYSCAN_COLOUT0_PD14 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xe)
1294 0 : #define KEYSCAN_COLOUT0_PD15 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xf)
1295 0 : #define KEYSCAN_COLOUT1_PA0 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x0)
1296 0 : #define KEYSCAN_COLOUT1_PA1 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x1)
1297 0 : #define KEYSCAN_COLOUT1_PA2 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x2)
1298 0 : #define KEYSCAN_COLOUT1_PA3 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x3)
1299 0 : #define KEYSCAN_COLOUT1_PA4 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x4)
1300 0 : #define KEYSCAN_COLOUT1_PA5 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x5)
1301 0 : #define KEYSCAN_COLOUT1_PA6 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x6)
1302 0 : #define KEYSCAN_COLOUT1_PA7 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x7)
1303 0 : #define KEYSCAN_COLOUT1_PA8 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x8)
1304 0 : #define KEYSCAN_COLOUT1_PA9 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x9)
1305 0 : #define KEYSCAN_COLOUT1_PA10 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xa)
1306 0 : #define KEYSCAN_COLOUT1_PA11 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xb)
1307 0 : #define KEYSCAN_COLOUT1_PA12 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xc)
1308 0 : #define KEYSCAN_COLOUT1_PA13 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xd)
1309 0 : #define KEYSCAN_COLOUT1_PA14 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xe)
1310 0 : #define KEYSCAN_COLOUT1_PB0 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x0)
1311 0 : #define KEYSCAN_COLOUT1_PB1 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x1)
1312 0 : #define KEYSCAN_COLOUT1_PB2 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x2)
1313 0 : #define KEYSCAN_COLOUT1_PB3 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x3)
1314 0 : #define KEYSCAN_COLOUT1_PB4 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x4)
1315 0 : #define KEYSCAN_COLOUT1_PB5 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x5)
1316 0 : #define KEYSCAN_COLOUT1_PB6 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x6)
1317 0 : #define KEYSCAN_COLOUT1_PB7 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x7)
1318 0 : #define KEYSCAN_COLOUT1_PC0 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x0)
1319 0 : #define KEYSCAN_COLOUT1_PC1 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x1)
1320 0 : #define KEYSCAN_COLOUT1_PC2 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x2)
1321 0 : #define KEYSCAN_COLOUT1_PC3 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x3)
1322 0 : #define KEYSCAN_COLOUT1_PC4 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x4)
1323 0 : #define KEYSCAN_COLOUT1_PC5 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x5)
1324 0 : #define KEYSCAN_COLOUT1_PC6 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x6)
1325 0 : #define KEYSCAN_COLOUT1_PC7 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x7)
1326 0 : #define KEYSCAN_COLOUT1_PC8 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x8)
1327 0 : #define KEYSCAN_COLOUT1_PC9 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x9)
1328 0 : #define KEYSCAN_COLOUT1_PC10 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xa)
1329 0 : #define KEYSCAN_COLOUT1_PC11 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xb)
1330 0 : #define KEYSCAN_COLOUT1_PD0 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x0)
1331 0 : #define KEYSCAN_COLOUT1_PD1 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x1)
1332 0 : #define KEYSCAN_COLOUT1_PD2 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x2)
1333 0 : #define KEYSCAN_COLOUT1_PD3 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x3)
1334 0 : #define KEYSCAN_COLOUT1_PD4 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x4)
1335 0 : #define KEYSCAN_COLOUT1_PD5 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x5)
1336 0 : #define KEYSCAN_COLOUT1_PD6 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x6)
1337 0 : #define KEYSCAN_COLOUT1_PD7 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x7)
1338 0 : #define KEYSCAN_COLOUT1_PD8 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x8)
1339 0 : #define KEYSCAN_COLOUT1_PD9 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x9)
1340 0 : #define KEYSCAN_COLOUT1_PD10 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xa)
1341 0 : #define KEYSCAN_COLOUT1_PD11 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xb)
1342 0 : #define KEYSCAN_COLOUT1_PD12 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xc)
1343 0 : #define KEYSCAN_COLOUT1_PD13 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xd)
1344 0 : #define KEYSCAN_COLOUT1_PD14 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xe)
1345 0 : #define KEYSCAN_COLOUT1_PD15 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xf)
1346 0 : #define KEYSCAN_COLOUT2_PA0 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x0)
1347 0 : #define KEYSCAN_COLOUT2_PA1 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x1)
1348 0 : #define KEYSCAN_COLOUT2_PA2 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x2)
1349 0 : #define KEYSCAN_COLOUT2_PA3 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x3)
1350 0 : #define KEYSCAN_COLOUT2_PA4 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x4)
1351 0 : #define KEYSCAN_COLOUT2_PA5 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x5)
1352 0 : #define KEYSCAN_COLOUT2_PA6 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x6)
1353 0 : #define KEYSCAN_COLOUT2_PA7 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x7)
1354 0 : #define KEYSCAN_COLOUT2_PA8 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x8)
1355 0 : #define KEYSCAN_COLOUT2_PA9 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x9)
1356 0 : #define KEYSCAN_COLOUT2_PA10 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xa)
1357 0 : #define KEYSCAN_COLOUT2_PA11 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xb)
1358 0 : #define KEYSCAN_COLOUT2_PA12 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xc)
1359 0 : #define KEYSCAN_COLOUT2_PA13 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xd)
1360 0 : #define KEYSCAN_COLOUT2_PA14 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xe)
1361 0 : #define KEYSCAN_COLOUT2_PB0 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x0)
1362 0 : #define KEYSCAN_COLOUT2_PB1 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x1)
1363 0 : #define KEYSCAN_COLOUT2_PB2 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x2)
1364 0 : #define KEYSCAN_COLOUT2_PB3 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x3)
1365 0 : #define KEYSCAN_COLOUT2_PB4 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x4)
1366 0 : #define KEYSCAN_COLOUT2_PB5 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x5)
1367 0 : #define KEYSCAN_COLOUT2_PB6 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x6)
1368 0 : #define KEYSCAN_COLOUT2_PB7 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x7)
1369 0 : #define KEYSCAN_COLOUT2_PC0 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x0)
1370 0 : #define KEYSCAN_COLOUT2_PC1 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x1)
1371 0 : #define KEYSCAN_COLOUT2_PC2 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x2)
1372 0 : #define KEYSCAN_COLOUT2_PC3 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x3)
1373 0 : #define KEYSCAN_COLOUT2_PC4 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x4)
1374 0 : #define KEYSCAN_COLOUT2_PC5 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x5)
1375 0 : #define KEYSCAN_COLOUT2_PC6 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x6)
1376 0 : #define KEYSCAN_COLOUT2_PC7 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x7)
1377 0 : #define KEYSCAN_COLOUT2_PC8 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x8)
1378 0 : #define KEYSCAN_COLOUT2_PC9 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x9)
1379 0 : #define KEYSCAN_COLOUT2_PC10 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xa)
1380 0 : #define KEYSCAN_COLOUT2_PC11 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xb)
1381 0 : #define KEYSCAN_COLOUT2_PD0 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x0)
1382 0 : #define KEYSCAN_COLOUT2_PD1 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x1)
1383 0 : #define KEYSCAN_COLOUT2_PD2 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x2)
1384 0 : #define KEYSCAN_COLOUT2_PD3 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x3)
1385 0 : #define KEYSCAN_COLOUT2_PD4 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x4)
1386 0 : #define KEYSCAN_COLOUT2_PD5 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x5)
1387 0 : #define KEYSCAN_COLOUT2_PD6 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x6)
1388 0 : #define KEYSCAN_COLOUT2_PD7 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x7)
1389 0 : #define KEYSCAN_COLOUT2_PD8 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x8)
1390 0 : #define KEYSCAN_COLOUT2_PD9 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x9)
1391 0 : #define KEYSCAN_COLOUT2_PD10 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xa)
1392 0 : #define KEYSCAN_COLOUT2_PD11 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xb)
1393 0 : #define KEYSCAN_COLOUT2_PD12 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xc)
1394 0 : #define KEYSCAN_COLOUT2_PD13 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xd)
1395 0 : #define KEYSCAN_COLOUT2_PD14 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xe)
1396 0 : #define KEYSCAN_COLOUT2_PD15 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xf)
1397 0 : #define KEYSCAN_COLOUT3_PA0 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x0)
1398 0 : #define KEYSCAN_COLOUT3_PA1 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x1)
1399 0 : #define KEYSCAN_COLOUT3_PA2 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x2)
1400 0 : #define KEYSCAN_COLOUT3_PA3 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x3)
1401 0 : #define KEYSCAN_COLOUT3_PA4 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x4)
1402 0 : #define KEYSCAN_COLOUT3_PA5 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x5)
1403 0 : #define KEYSCAN_COLOUT3_PA6 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x6)
1404 0 : #define KEYSCAN_COLOUT3_PA7 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x7)
1405 0 : #define KEYSCAN_COLOUT3_PA8 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x8)
1406 0 : #define KEYSCAN_COLOUT3_PA9 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x9)
1407 0 : #define KEYSCAN_COLOUT3_PA10 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xa)
1408 0 : #define KEYSCAN_COLOUT3_PA11 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xb)
1409 0 : #define KEYSCAN_COLOUT3_PA12 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xc)
1410 0 : #define KEYSCAN_COLOUT3_PA13 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xd)
1411 0 : #define KEYSCAN_COLOUT3_PA14 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xe)
1412 0 : #define KEYSCAN_COLOUT3_PB0 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x0)
1413 0 : #define KEYSCAN_COLOUT3_PB1 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x1)
1414 0 : #define KEYSCAN_COLOUT3_PB2 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x2)
1415 0 : #define KEYSCAN_COLOUT3_PB3 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x3)
1416 0 : #define KEYSCAN_COLOUT3_PB4 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x4)
1417 0 : #define KEYSCAN_COLOUT3_PB5 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x5)
1418 0 : #define KEYSCAN_COLOUT3_PB6 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x6)
1419 0 : #define KEYSCAN_COLOUT3_PB7 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x7)
1420 0 : #define KEYSCAN_COLOUT3_PC0 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x0)
1421 0 : #define KEYSCAN_COLOUT3_PC1 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x1)
1422 0 : #define KEYSCAN_COLOUT3_PC2 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x2)
1423 0 : #define KEYSCAN_COLOUT3_PC3 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x3)
1424 0 : #define KEYSCAN_COLOUT3_PC4 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x4)
1425 0 : #define KEYSCAN_COLOUT3_PC5 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x5)
1426 0 : #define KEYSCAN_COLOUT3_PC6 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x6)
1427 0 : #define KEYSCAN_COLOUT3_PC7 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x7)
1428 0 : #define KEYSCAN_COLOUT3_PC8 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x8)
1429 0 : #define KEYSCAN_COLOUT3_PC9 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x9)
1430 0 : #define KEYSCAN_COLOUT3_PC10 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xa)
1431 0 : #define KEYSCAN_COLOUT3_PC11 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xb)
1432 0 : #define KEYSCAN_COLOUT3_PD0 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x0)
1433 0 : #define KEYSCAN_COLOUT3_PD1 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x1)
1434 0 : #define KEYSCAN_COLOUT3_PD2 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x2)
1435 0 : #define KEYSCAN_COLOUT3_PD3 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x3)
1436 0 : #define KEYSCAN_COLOUT3_PD4 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x4)
1437 0 : #define KEYSCAN_COLOUT3_PD5 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x5)
1438 0 : #define KEYSCAN_COLOUT3_PD6 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x6)
1439 0 : #define KEYSCAN_COLOUT3_PD7 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x7)
1440 0 : #define KEYSCAN_COLOUT3_PD8 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x8)
1441 0 : #define KEYSCAN_COLOUT3_PD9 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x9)
1442 0 : #define KEYSCAN_COLOUT3_PD10 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xa)
1443 0 : #define KEYSCAN_COLOUT3_PD11 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xb)
1444 0 : #define KEYSCAN_COLOUT3_PD12 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xc)
1445 0 : #define KEYSCAN_COLOUT3_PD13 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xd)
1446 0 : #define KEYSCAN_COLOUT3_PD14 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xe)
1447 0 : #define KEYSCAN_COLOUT3_PD15 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xf)
1448 0 : #define KEYSCAN_COLOUT4_PA0 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x0)
1449 0 : #define KEYSCAN_COLOUT4_PA1 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x1)
1450 0 : #define KEYSCAN_COLOUT4_PA2 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x2)
1451 0 : #define KEYSCAN_COLOUT4_PA3 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x3)
1452 0 : #define KEYSCAN_COLOUT4_PA4 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x4)
1453 0 : #define KEYSCAN_COLOUT4_PA5 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x5)
1454 0 : #define KEYSCAN_COLOUT4_PA6 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x6)
1455 0 : #define KEYSCAN_COLOUT4_PA7 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x7)
1456 0 : #define KEYSCAN_COLOUT4_PA8 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x8)
1457 0 : #define KEYSCAN_COLOUT4_PA9 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x9)
1458 0 : #define KEYSCAN_COLOUT4_PA10 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xa)
1459 0 : #define KEYSCAN_COLOUT4_PA11 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xb)
1460 0 : #define KEYSCAN_COLOUT4_PA12 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xc)
1461 0 : #define KEYSCAN_COLOUT4_PA13 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xd)
1462 0 : #define KEYSCAN_COLOUT4_PA14 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xe)
1463 0 : #define KEYSCAN_COLOUT4_PB0 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x0)
1464 0 : #define KEYSCAN_COLOUT4_PB1 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x1)
1465 0 : #define KEYSCAN_COLOUT4_PB2 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x2)
1466 0 : #define KEYSCAN_COLOUT4_PB3 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x3)
1467 0 : #define KEYSCAN_COLOUT4_PB4 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x4)
1468 0 : #define KEYSCAN_COLOUT4_PB5 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x5)
1469 0 : #define KEYSCAN_COLOUT4_PB6 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x6)
1470 0 : #define KEYSCAN_COLOUT4_PB7 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x7)
1471 0 : #define KEYSCAN_COLOUT4_PC0 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x0)
1472 0 : #define KEYSCAN_COLOUT4_PC1 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x1)
1473 0 : #define KEYSCAN_COLOUT4_PC2 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x2)
1474 0 : #define KEYSCAN_COLOUT4_PC3 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x3)
1475 0 : #define KEYSCAN_COLOUT4_PC4 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x4)
1476 0 : #define KEYSCAN_COLOUT4_PC5 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x5)
1477 0 : #define KEYSCAN_COLOUT4_PC6 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x6)
1478 0 : #define KEYSCAN_COLOUT4_PC7 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x7)
1479 0 : #define KEYSCAN_COLOUT4_PC8 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x8)
1480 0 : #define KEYSCAN_COLOUT4_PC9 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x9)
1481 0 : #define KEYSCAN_COLOUT4_PC10 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xa)
1482 0 : #define KEYSCAN_COLOUT4_PC11 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xb)
1483 0 : #define KEYSCAN_COLOUT4_PD0 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x0)
1484 0 : #define KEYSCAN_COLOUT4_PD1 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x1)
1485 0 : #define KEYSCAN_COLOUT4_PD2 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x2)
1486 0 : #define KEYSCAN_COLOUT4_PD3 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x3)
1487 0 : #define KEYSCAN_COLOUT4_PD4 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x4)
1488 0 : #define KEYSCAN_COLOUT4_PD5 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x5)
1489 0 : #define KEYSCAN_COLOUT4_PD6 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x6)
1490 0 : #define KEYSCAN_COLOUT4_PD7 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x7)
1491 0 : #define KEYSCAN_COLOUT4_PD8 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x8)
1492 0 : #define KEYSCAN_COLOUT4_PD9 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x9)
1493 0 : #define KEYSCAN_COLOUT4_PD10 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xa)
1494 0 : #define KEYSCAN_COLOUT4_PD11 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xb)
1495 0 : #define KEYSCAN_COLOUT4_PD12 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xc)
1496 0 : #define KEYSCAN_COLOUT4_PD13 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xd)
1497 0 : #define KEYSCAN_COLOUT4_PD14 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xe)
1498 0 : #define KEYSCAN_COLOUT4_PD15 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xf)
1499 0 : #define KEYSCAN_COLOUT5_PA0 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x0)
1500 0 : #define KEYSCAN_COLOUT5_PA1 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x1)
1501 0 : #define KEYSCAN_COLOUT5_PA2 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x2)
1502 0 : #define KEYSCAN_COLOUT5_PA3 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x3)
1503 0 : #define KEYSCAN_COLOUT5_PA4 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x4)
1504 0 : #define KEYSCAN_COLOUT5_PA5 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x5)
1505 0 : #define KEYSCAN_COLOUT5_PA6 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x6)
1506 0 : #define KEYSCAN_COLOUT5_PA7 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x7)
1507 0 : #define KEYSCAN_COLOUT5_PA8 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x8)
1508 0 : #define KEYSCAN_COLOUT5_PA9 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x9)
1509 0 : #define KEYSCAN_COLOUT5_PA10 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xa)
1510 0 : #define KEYSCAN_COLOUT5_PA11 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xb)
1511 0 : #define KEYSCAN_COLOUT5_PA12 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xc)
1512 0 : #define KEYSCAN_COLOUT5_PA13 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xd)
1513 0 : #define KEYSCAN_COLOUT5_PA14 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xe)
1514 0 : #define KEYSCAN_COLOUT5_PB0 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x0)
1515 0 : #define KEYSCAN_COLOUT5_PB1 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x1)
1516 0 : #define KEYSCAN_COLOUT5_PB2 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x2)
1517 0 : #define KEYSCAN_COLOUT5_PB3 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x3)
1518 0 : #define KEYSCAN_COLOUT5_PB4 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x4)
1519 0 : #define KEYSCAN_COLOUT5_PB5 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x5)
1520 0 : #define KEYSCAN_COLOUT5_PB6 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x6)
1521 0 : #define KEYSCAN_COLOUT5_PB7 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x7)
1522 0 : #define KEYSCAN_COLOUT5_PC0 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x0)
1523 0 : #define KEYSCAN_COLOUT5_PC1 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x1)
1524 0 : #define KEYSCAN_COLOUT5_PC2 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x2)
1525 0 : #define KEYSCAN_COLOUT5_PC3 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x3)
1526 0 : #define KEYSCAN_COLOUT5_PC4 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x4)
1527 0 : #define KEYSCAN_COLOUT5_PC5 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x5)
1528 0 : #define KEYSCAN_COLOUT5_PC6 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x6)
1529 0 : #define KEYSCAN_COLOUT5_PC7 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x7)
1530 0 : #define KEYSCAN_COLOUT5_PC8 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x8)
1531 0 : #define KEYSCAN_COLOUT5_PC9 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x9)
1532 0 : #define KEYSCAN_COLOUT5_PC10 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xa)
1533 0 : #define KEYSCAN_COLOUT5_PC11 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xb)
1534 0 : #define KEYSCAN_COLOUT5_PD0 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x0)
1535 0 : #define KEYSCAN_COLOUT5_PD1 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x1)
1536 0 : #define KEYSCAN_COLOUT5_PD2 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x2)
1537 0 : #define KEYSCAN_COLOUT5_PD3 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x3)
1538 0 : #define KEYSCAN_COLOUT5_PD4 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x4)
1539 0 : #define KEYSCAN_COLOUT5_PD5 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x5)
1540 0 : #define KEYSCAN_COLOUT5_PD6 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x6)
1541 0 : #define KEYSCAN_COLOUT5_PD7 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x7)
1542 0 : #define KEYSCAN_COLOUT5_PD8 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x8)
1543 0 : #define KEYSCAN_COLOUT5_PD9 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x9)
1544 0 : #define KEYSCAN_COLOUT5_PD10 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xa)
1545 0 : #define KEYSCAN_COLOUT5_PD11 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xb)
1546 0 : #define KEYSCAN_COLOUT5_PD12 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xc)
1547 0 : #define KEYSCAN_COLOUT5_PD13 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xd)
1548 0 : #define KEYSCAN_COLOUT5_PD14 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xe)
1549 0 : #define KEYSCAN_COLOUT5_PD15 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xf)
1550 0 : #define KEYSCAN_COLOUT6_PA0 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x0)
1551 0 : #define KEYSCAN_COLOUT6_PA1 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x1)
1552 0 : #define KEYSCAN_COLOUT6_PA2 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x2)
1553 0 : #define KEYSCAN_COLOUT6_PA3 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x3)
1554 0 : #define KEYSCAN_COLOUT6_PA4 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x4)
1555 0 : #define KEYSCAN_COLOUT6_PA5 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x5)
1556 0 : #define KEYSCAN_COLOUT6_PA6 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x6)
1557 0 : #define KEYSCAN_COLOUT6_PA7 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x7)
1558 0 : #define KEYSCAN_COLOUT6_PA8 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x8)
1559 0 : #define KEYSCAN_COLOUT6_PA9 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x9)
1560 0 : #define KEYSCAN_COLOUT6_PA10 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xa)
1561 0 : #define KEYSCAN_COLOUT6_PA11 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xb)
1562 0 : #define KEYSCAN_COLOUT6_PA12 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xc)
1563 0 : #define KEYSCAN_COLOUT6_PA13 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xd)
1564 0 : #define KEYSCAN_COLOUT6_PA14 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xe)
1565 0 : #define KEYSCAN_COLOUT6_PB0 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x0)
1566 0 : #define KEYSCAN_COLOUT6_PB1 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x1)
1567 0 : #define KEYSCAN_COLOUT6_PB2 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x2)
1568 0 : #define KEYSCAN_COLOUT6_PB3 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x3)
1569 0 : #define KEYSCAN_COLOUT6_PB4 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x4)
1570 0 : #define KEYSCAN_COLOUT6_PB5 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x5)
1571 0 : #define KEYSCAN_COLOUT6_PB6 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x6)
1572 0 : #define KEYSCAN_COLOUT6_PB7 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x7)
1573 0 : #define KEYSCAN_COLOUT6_PC0 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x0)
1574 0 : #define KEYSCAN_COLOUT6_PC1 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x1)
1575 0 : #define KEYSCAN_COLOUT6_PC2 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x2)
1576 0 : #define KEYSCAN_COLOUT6_PC3 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x3)
1577 0 : #define KEYSCAN_COLOUT6_PC4 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x4)
1578 0 : #define KEYSCAN_COLOUT6_PC5 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x5)
1579 0 : #define KEYSCAN_COLOUT6_PC6 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x6)
1580 0 : #define KEYSCAN_COLOUT6_PC7 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x7)
1581 0 : #define KEYSCAN_COLOUT6_PC8 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x8)
1582 0 : #define KEYSCAN_COLOUT6_PC9 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x9)
1583 0 : #define KEYSCAN_COLOUT6_PC10 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xa)
1584 0 : #define KEYSCAN_COLOUT6_PC11 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xb)
1585 0 : #define KEYSCAN_COLOUT6_PD0 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x0)
1586 0 : #define KEYSCAN_COLOUT6_PD1 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x1)
1587 0 : #define KEYSCAN_COLOUT6_PD2 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x2)
1588 0 : #define KEYSCAN_COLOUT6_PD3 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x3)
1589 0 : #define KEYSCAN_COLOUT6_PD4 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x4)
1590 0 : #define KEYSCAN_COLOUT6_PD5 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x5)
1591 0 : #define KEYSCAN_COLOUT6_PD6 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x6)
1592 0 : #define KEYSCAN_COLOUT6_PD7 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x7)
1593 0 : #define KEYSCAN_COLOUT6_PD8 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x8)
1594 0 : #define KEYSCAN_COLOUT6_PD9 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x9)
1595 0 : #define KEYSCAN_COLOUT6_PD10 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xa)
1596 0 : #define KEYSCAN_COLOUT6_PD11 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xb)
1597 0 : #define KEYSCAN_COLOUT6_PD12 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xc)
1598 0 : #define KEYSCAN_COLOUT6_PD13 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xd)
1599 0 : #define KEYSCAN_COLOUT6_PD14 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xe)
1600 0 : #define KEYSCAN_COLOUT6_PD15 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xf)
1601 0 : #define KEYSCAN_COLOUT7_PA0 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x0)
1602 0 : #define KEYSCAN_COLOUT7_PA1 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x1)
1603 0 : #define KEYSCAN_COLOUT7_PA2 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x2)
1604 0 : #define KEYSCAN_COLOUT7_PA3 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x3)
1605 0 : #define KEYSCAN_COLOUT7_PA4 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x4)
1606 0 : #define KEYSCAN_COLOUT7_PA5 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x5)
1607 0 : #define KEYSCAN_COLOUT7_PA6 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x6)
1608 0 : #define KEYSCAN_COLOUT7_PA7 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x7)
1609 0 : #define KEYSCAN_COLOUT7_PA8 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x8)
1610 0 : #define KEYSCAN_COLOUT7_PA9 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x9)
1611 0 : #define KEYSCAN_COLOUT7_PA10 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xa)
1612 0 : #define KEYSCAN_COLOUT7_PA11 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xb)
1613 0 : #define KEYSCAN_COLOUT7_PA12 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xc)
1614 0 : #define KEYSCAN_COLOUT7_PA13 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xd)
1615 0 : #define KEYSCAN_COLOUT7_PA14 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xe)
1616 0 : #define KEYSCAN_COLOUT7_PB0 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x0)
1617 0 : #define KEYSCAN_COLOUT7_PB1 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x1)
1618 0 : #define KEYSCAN_COLOUT7_PB2 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x2)
1619 0 : #define KEYSCAN_COLOUT7_PB3 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x3)
1620 0 : #define KEYSCAN_COLOUT7_PB4 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x4)
1621 0 : #define KEYSCAN_COLOUT7_PB5 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x5)
1622 0 : #define KEYSCAN_COLOUT7_PB6 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x6)
1623 0 : #define KEYSCAN_COLOUT7_PB7 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x7)
1624 0 : #define KEYSCAN_COLOUT7_PC0 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x0)
1625 0 : #define KEYSCAN_COLOUT7_PC1 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x1)
1626 0 : #define KEYSCAN_COLOUT7_PC2 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x2)
1627 0 : #define KEYSCAN_COLOUT7_PC3 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x3)
1628 0 : #define KEYSCAN_COLOUT7_PC4 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x4)
1629 0 : #define KEYSCAN_COLOUT7_PC5 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x5)
1630 0 : #define KEYSCAN_COLOUT7_PC6 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x6)
1631 0 : #define KEYSCAN_COLOUT7_PC7 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x7)
1632 0 : #define KEYSCAN_COLOUT7_PC8 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x8)
1633 0 : #define KEYSCAN_COLOUT7_PC9 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x9)
1634 0 : #define KEYSCAN_COLOUT7_PC10 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xa)
1635 0 : #define KEYSCAN_COLOUT7_PC11 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xb)
1636 0 : #define KEYSCAN_COLOUT7_PD0 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x0)
1637 0 : #define KEYSCAN_COLOUT7_PD1 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x1)
1638 0 : #define KEYSCAN_COLOUT7_PD2 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x2)
1639 0 : #define KEYSCAN_COLOUT7_PD3 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x3)
1640 0 : #define KEYSCAN_COLOUT7_PD4 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x4)
1641 0 : #define KEYSCAN_COLOUT7_PD5 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x5)
1642 0 : #define KEYSCAN_COLOUT7_PD6 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x6)
1643 0 : #define KEYSCAN_COLOUT7_PD7 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x7)
1644 0 : #define KEYSCAN_COLOUT7_PD8 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x8)
1645 0 : #define KEYSCAN_COLOUT7_PD9 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x9)
1646 0 : #define KEYSCAN_COLOUT7_PD10 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xa)
1647 0 : #define KEYSCAN_COLOUT7_PD11 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xb)
1648 0 : #define KEYSCAN_COLOUT7_PD12 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xc)
1649 0 : #define KEYSCAN_COLOUT7_PD13 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xd)
1650 0 : #define KEYSCAN_COLOUT7_PD14 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xe)
1651 0 : #define KEYSCAN_COLOUT7_PD15 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xf)
1652 0 : #define KEYSCAN_ROWSENSE0_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x0)
1653 0 : #define KEYSCAN_ROWSENSE0_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x1)
1654 0 : #define KEYSCAN_ROWSENSE0_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x2)
1655 0 : #define KEYSCAN_ROWSENSE0_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x3)
1656 0 : #define KEYSCAN_ROWSENSE0_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x4)
1657 0 : #define KEYSCAN_ROWSENSE0_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x5)
1658 0 : #define KEYSCAN_ROWSENSE0_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x6)
1659 0 : #define KEYSCAN_ROWSENSE0_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x7)
1660 0 : #define KEYSCAN_ROWSENSE0_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x8)
1661 0 : #define KEYSCAN_ROWSENSE0_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x9)
1662 0 : #define KEYSCAN_ROWSENSE0_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xa)
1663 0 : #define KEYSCAN_ROWSENSE0_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xb)
1664 0 : #define KEYSCAN_ROWSENSE0_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xc)
1665 0 : #define KEYSCAN_ROWSENSE0_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xd)
1666 0 : #define KEYSCAN_ROWSENSE0_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xe)
1667 0 : #define KEYSCAN_ROWSENSE0_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x0)
1668 0 : #define KEYSCAN_ROWSENSE0_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x1)
1669 0 : #define KEYSCAN_ROWSENSE0_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x2)
1670 0 : #define KEYSCAN_ROWSENSE0_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x3)
1671 0 : #define KEYSCAN_ROWSENSE0_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x4)
1672 0 : #define KEYSCAN_ROWSENSE0_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x5)
1673 0 : #define KEYSCAN_ROWSENSE0_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x6)
1674 0 : #define KEYSCAN_ROWSENSE0_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x7)
1675 0 : #define KEYSCAN_ROWSENSE1_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x0)
1676 0 : #define KEYSCAN_ROWSENSE1_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x1)
1677 0 : #define KEYSCAN_ROWSENSE1_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x2)
1678 0 : #define KEYSCAN_ROWSENSE1_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x3)
1679 0 : #define KEYSCAN_ROWSENSE1_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x4)
1680 0 : #define KEYSCAN_ROWSENSE1_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x5)
1681 0 : #define KEYSCAN_ROWSENSE1_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x6)
1682 0 : #define KEYSCAN_ROWSENSE1_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x7)
1683 0 : #define KEYSCAN_ROWSENSE1_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x8)
1684 0 : #define KEYSCAN_ROWSENSE1_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x9)
1685 0 : #define KEYSCAN_ROWSENSE1_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xa)
1686 0 : #define KEYSCAN_ROWSENSE1_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xb)
1687 0 : #define KEYSCAN_ROWSENSE1_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xc)
1688 0 : #define KEYSCAN_ROWSENSE1_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xd)
1689 0 : #define KEYSCAN_ROWSENSE1_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xe)
1690 0 : #define KEYSCAN_ROWSENSE1_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x0)
1691 0 : #define KEYSCAN_ROWSENSE1_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x1)
1692 0 : #define KEYSCAN_ROWSENSE1_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x2)
1693 0 : #define KEYSCAN_ROWSENSE1_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x3)
1694 0 : #define KEYSCAN_ROWSENSE1_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x4)
1695 0 : #define KEYSCAN_ROWSENSE1_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x5)
1696 0 : #define KEYSCAN_ROWSENSE1_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x6)
1697 0 : #define KEYSCAN_ROWSENSE1_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x7)
1698 0 : #define KEYSCAN_ROWSENSE2_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x0)
1699 0 : #define KEYSCAN_ROWSENSE2_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x1)
1700 0 : #define KEYSCAN_ROWSENSE2_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x2)
1701 0 : #define KEYSCAN_ROWSENSE2_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x3)
1702 0 : #define KEYSCAN_ROWSENSE2_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x4)
1703 0 : #define KEYSCAN_ROWSENSE2_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x5)
1704 0 : #define KEYSCAN_ROWSENSE2_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x6)
1705 0 : #define KEYSCAN_ROWSENSE2_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x7)
1706 0 : #define KEYSCAN_ROWSENSE2_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x8)
1707 0 : #define KEYSCAN_ROWSENSE2_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x9)
1708 0 : #define KEYSCAN_ROWSENSE2_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xa)
1709 0 : #define KEYSCAN_ROWSENSE2_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xb)
1710 0 : #define KEYSCAN_ROWSENSE2_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xc)
1711 0 : #define KEYSCAN_ROWSENSE2_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xd)
1712 0 : #define KEYSCAN_ROWSENSE2_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xe)
1713 0 : #define KEYSCAN_ROWSENSE2_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x0)
1714 0 : #define KEYSCAN_ROWSENSE2_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x1)
1715 0 : #define KEYSCAN_ROWSENSE2_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x2)
1716 0 : #define KEYSCAN_ROWSENSE2_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x3)
1717 0 : #define KEYSCAN_ROWSENSE2_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x4)
1718 0 : #define KEYSCAN_ROWSENSE2_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x5)
1719 0 : #define KEYSCAN_ROWSENSE2_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x6)
1720 0 : #define KEYSCAN_ROWSENSE2_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x7)
1721 0 : #define KEYSCAN_ROWSENSE3_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x0)
1722 0 : #define KEYSCAN_ROWSENSE3_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x1)
1723 0 : #define KEYSCAN_ROWSENSE3_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x2)
1724 0 : #define KEYSCAN_ROWSENSE3_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x3)
1725 0 : #define KEYSCAN_ROWSENSE3_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x4)
1726 0 : #define KEYSCAN_ROWSENSE3_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x5)
1727 0 : #define KEYSCAN_ROWSENSE3_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x6)
1728 0 : #define KEYSCAN_ROWSENSE3_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x7)
1729 0 : #define KEYSCAN_ROWSENSE3_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x8)
1730 0 : #define KEYSCAN_ROWSENSE3_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x9)
1731 0 : #define KEYSCAN_ROWSENSE3_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xa)
1732 0 : #define KEYSCAN_ROWSENSE3_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xb)
1733 0 : #define KEYSCAN_ROWSENSE3_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xc)
1734 0 : #define KEYSCAN_ROWSENSE3_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xd)
1735 0 : #define KEYSCAN_ROWSENSE3_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xe)
1736 0 : #define KEYSCAN_ROWSENSE3_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x0)
1737 0 : #define KEYSCAN_ROWSENSE3_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x1)
1738 0 : #define KEYSCAN_ROWSENSE3_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x2)
1739 0 : #define KEYSCAN_ROWSENSE3_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x3)
1740 0 : #define KEYSCAN_ROWSENSE3_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x4)
1741 0 : #define KEYSCAN_ROWSENSE3_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x5)
1742 0 : #define KEYSCAN_ROWSENSE3_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x6)
1743 0 : #define KEYSCAN_ROWSENSE3_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x7)
1744 0 : #define KEYSCAN_ROWSENSE4_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x0)
1745 0 : #define KEYSCAN_ROWSENSE4_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x1)
1746 0 : #define KEYSCAN_ROWSENSE4_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x2)
1747 0 : #define KEYSCAN_ROWSENSE4_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x3)
1748 0 : #define KEYSCAN_ROWSENSE4_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x4)
1749 0 : #define KEYSCAN_ROWSENSE4_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x5)
1750 0 : #define KEYSCAN_ROWSENSE4_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x6)
1751 0 : #define KEYSCAN_ROWSENSE4_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x7)
1752 0 : #define KEYSCAN_ROWSENSE4_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x8)
1753 0 : #define KEYSCAN_ROWSENSE4_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x9)
1754 0 : #define KEYSCAN_ROWSENSE4_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xa)
1755 0 : #define KEYSCAN_ROWSENSE4_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xb)
1756 0 : #define KEYSCAN_ROWSENSE4_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xc)
1757 0 : #define KEYSCAN_ROWSENSE4_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xd)
1758 0 : #define KEYSCAN_ROWSENSE4_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xe)
1759 0 : #define KEYSCAN_ROWSENSE4_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x0)
1760 0 : #define KEYSCAN_ROWSENSE4_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x1)
1761 0 : #define KEYSCAN_ROWSENSE4_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x2)
1762 0 : #define KEYSCAN_ROWSENSE4_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x3)
1763 0 : #define KEYSCAN_ROWSENSE4_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x4)
1764 0 : #define KEYSCAN_ROWSENSE4_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x5)
1765 0 : #define KEYSCAN_ROWSENSE4_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x6)
1766 0 : #define KEYSCAN_ROWSENSE4_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x7)
1767 0 : #define KEYSCAN_ROWSENSE5_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x0)
1768 0 : #define KEYSCAN_ROWSENSE5_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x1)
1769 0 : #define KEYSCAN_ROWSENSE5_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x2)
1770 0 : #define KEYSCAN_ROWSENSE5_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x3)
1771 0 : #define KEYSCAN_ROWSENSE5_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x4)
1772 0 : #define KEYSCAN_ROWSENSE5_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x5)
1773 0 : #define KEYSCAN_ROWSENSE5_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x6)
1774 0 : #define KEYSCAN_ROWSENSE5_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x7)
1775 0 : #define KEYSCAN_ROWSENSE5_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x8)
1776 0 : #define KEYSCAN_ROWSENSE5_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x9)
1777 0 : #define KEYSCAN_ROWSENSE5_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xa)
1778 0 : #define KEYSCAN_ROWSENSE5_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xb)
1779 0 : #define KEYSCAN_ROWSENSE5_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xc)
1780 0 : #define KEYSCAN_ROWSENSE5_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xd)
1781 0 : #define KEYSCAN_ROWSENSE5_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xe)
1782 0 : #define KEYSCAN_ROWSENSE5_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x0)
1783 0 : #define KEYSCAN_ROWSENSE5_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x1)
1784 0 : #define KEYSCAN_ROWSENSE5_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x2)
1785 0 : #define KEYSCAN_ROWSENSE5_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x3)
1786 0 : #define KEYSCAN_ROWSENSE5_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x4)
1787 0 : #define KEYSCAN_ROWSENSE5_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x5)
1788 0 : #define KEYSCAN_ROWSENSE5_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x6)
1789 0 : #define KEYSCAN_ROWSENSE5_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x7)
1790 :
1791 0 : #define LESENSE_CH0OUT_PA0 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x0)
1792 0 : #define LESENSE_CH0OUT_PA1 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x1)
1793 0 : #define LESENSE_CH0OUT_PA2 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x2)
1794 0 : #define LESENSE_CH0OUT_PA3 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x3)
1795 0 : #define LESENSE_CH0OUT_PA4 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x4)
1796 0 : #define LESENSE_CH0OUT_PA5 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x5)
1797 0 : #define LESENSE_CH0OUT_PA6 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x6)
1798 0 : #define LESENSE_CH0OUT_PA7 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x7)
1799 0 : #define LESENSE_CH0OUT_PA8 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x8)
1800 0 : #define LESENSE_CH0OUT_PA9 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x9)
1801 0 : #define LESENSE_CH0OUT_PA10 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xa)
1802 0 : #define LESENSE_CH0OUT_PA11 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xb)
1803 0 : #define LESENSE_CH0OUT_PA12 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xc)
1804 0 : #define LESENSE_CH0OUT_PA13 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xd)
1805 0 : #define LESENSE_CH0OUT_PA14 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xe)
1806 0 : #define LESENSE_CH0OUT_PB0 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x0)
1807 0 : #define LESENSE_CH0OUT_PB1 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x1)
1808 0 : #define LESENSE_CH0OUT_PB2 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x2)
1809 0 : #define LESENSE_CH0OUT_PB3 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x3)
1810 0 : #define LESENSE_CH0OUT_PB4 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x4)
1811 0 : #define LESENSE_CH0OUT_PB5 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x5)
1812 0 : #define LESENSE_CH0OUT_PB6 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x6)
1813 0 : #define LESENSE_CH0OUT_PB7 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x7)
1814 0 : #define LESENSE_CH1OUT_PA0 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x0)
1815 0 : #define LESENSE_CH1OUT_PA1 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x1)
1816 0 : #define LESENSE_CH1OUT_PA2 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x2)
1817 0 : #define LESENSE_CH1OUT_PA3 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x3)
1818 0 : #define LESENSE_CH1OUT_PA4 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x4)
1819 0 : #define LESENSE_CH1OUT_PA5 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x5)
1820 0 : #define LESENSE_CH1OUT_PA6 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x6)
1821 0 : #define LESENSE_CH1OUT_PA7 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x7)
1822 0 : #define LESENSE_CH1OUT_PA8 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x8)
1823 0 : #define LESENSE_CH1OUT_PA9 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x9)
1824 0 : #define LESENSE_CH1OUT_PA10 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xa)
1825 0 : #define LESENSE_CH1OUT_PA11 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xb)
1826 0 : #define LESENSE_CH1OUT_PA12 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xc)
1827 0 : #define LESENSE_CH1OUT_PA13 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xd)
1828 0 : #define LESENSE_CH1OUT_PA14 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xe)
1829 0 : #define LESENSE_CH1OUT_PB0 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x0)
1830 0 : #define LESENSE_CH1OUT_PB1 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x1)
1831 0 : #define LESENSE_CH1OUT_PB2 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x2)
1832 0 : #define LESENSE_CH1OUT_PB3 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x3)
1833 0 : #define LESENSE_CH1OUT_PB4 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x4)
1834 0 : #define LESENSE_CH1OUT_PB5 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x5)
1835 0 : #define LESENSE_CH1OUT_PB6 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x6)
1836 0 : #define LESENSE_CH1OUT_PB7 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x7)
1837 0 : #define LESENSE_CH2OUT_PA0 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x0)
1838 0 : #define LESENSE_CH2OUT_PA1 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x1)
1839 0 : #define LESENSE_CH2OUT_PA2 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x2)
1840 0 : #define LESENSE_CH2OUT_PA3 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x3)
1841 0 : #define LESENSE_CH2OUT_PA4 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x4)
1842 0 : #define LESENSE_CH2OUT_PA5 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x5)
1843 0 : #define LESENSE_CH2OUT_PA6 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x6)
1844 0 : #define LESENSE_CH2OUT_PA7 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x7)
1845 0 : #define LESENSE_CH2OUT_PA8 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x8)
1846 0 : #define LESENSE_CH2OUT_PA9 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x9)
1847 0 : #define LESENSE_CH2OUT_PA10 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xa)
1848 0 : #define LESENSE_CH2OUT_PA11 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xb)
1849 0 : #define LESENSE_CH2OUT_PA12 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xc)
1850 0 : #define LESENSE_CH2OUT_PA13 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xd)
1851 0 : #define LESENSE_CH2OUT_PA14 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xe)
1852 0 : #define LESENSE_CH2OUT_PB0 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x0)
1853 0 : #define LESENSE_CH2OUT_PB1 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x1)
1854 0 : #define LESENSE_CH2OUT_PB2 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x2)
1855 0 : #define LESENSE_CH2OUT_PB3 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x3)
1856 0 : #define LESENSE_CH2OUT_PB4 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x4)
1857 0 : #define LESENSE_CH2OUT_PB5 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x5)
1858 0 : #define LESENSE_CH2OUT_PB6 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x6)
1859 0 : #define LESENSE_CH2OUT_PB7 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x7)
1860 0 : #define LESENSE_CH3OUT_PA0 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x0)
1861 0 : #define LESENSE_CH3OUT_PA1 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x1)
1862 0 : #define LESENSE_CH3OUT_PA2 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x2)
1863 0 : #define LESENSE_CH3OUT_PA3 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x3)
1864 0 : #define LESENSE_CH3OUT_PA4 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x4)
1865 0 : #define LESENSE_CH3OUT_PA5 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x5)
1866 0 : #define LESENSE_CH3OUT_PA6 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x6)
1867 0 : #define LESENSE_CH3OUT_PA7 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x7)
1868 0 : #define LESENSE_CH3OUT_PA8 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x8)
1869 0 : #define LESENSE_CH3OUT_PA9 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x9)
1870 0 : #define LESENSE_CH3OUT_PA10 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xa)
1871 0 : #define LESENSE_CH3OUT_PA11 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xb)
1872 0 : #define LESENSE_CH3OUT_PA12 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xc)
1873 0 : #define LESENSE_CH3OUT_PA13 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xd)
1874 0 : #define LESENSE_CH3OUT_PA14 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xe)
1875 0 : #define LESENSE_CH3OUT_PB0 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x0)
1876 0 : #define LESENSE_CH3OUT_PB1 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x1)
1877 0 : #define LESENSE_CH3OUT_PB2 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x2)
1878 0 : #define LESENSE_CH3OUT_PB3 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x3)
1879 0 : #define LESENSE_CH3OUT_PB4 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x4)
1880 0 : #define LESENSE_CH3OUT_PB5 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x5)
1881 0 : #define LESENSE_CH3OUT_PB6 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x6)
1882 0 : #define LESENSE_CH3OUT_PB7 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x7)
1883 0 : #define LESENSE_CH4OUT_PA0 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x0)
1884 0 : #define LESENSE_CH4OUT_PA1 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x1)
1885 0 : #define LESENSE_CH4OUT_PA2 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x2)
1886 0 : #define LESENSE_CH4OUT_PA3 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x3)
1887 0 : #define LESENSE_CH4OUT_PA4 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x4)
1888 0 : #define LESENSE_CH4OUT_PA5 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x5)
1889 0 : #define LESENSE_CH4OUT_PA6 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x6)
1890 0 : #define LESENSE_CH4OUT_PA7 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x7)
1891 0 : #define LESENSE_CH4OUT_PA8 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x8)
1892 0 : #define LESENSE_CH4OUT_PA9 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x9)
1893 0 : #define LESENSE_CH4OUT_PA10 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xa)
1894 0 : #define LESENSE_CH4OUT_PA11 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xb)
1895 0 : #define LESENSE_CH4OUT_PA12 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xc)
1896 0 : #define LESENSE_CH4OUT_PA13 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xd)
1897 0 : #define LESENSE_CH4OUT_PA14 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xe)
1898 0 : #define LESENSE_CH4OUT_PB0 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x0)
1899 0 : #define LESENSE_CH4OUT_PB1 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x1)
1900 0 : #define LESENSE_CH4OUT_PB2 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x2)
1901 0 : #define LESENSE_CH4OUT_PB3 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x3)
1902 0 : #define LESENSE_CH4OUT_PB4 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x4)
1903 0 : #define LESENSE_CH4OUT_PB5 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x5)
1904 0 : #define LESENSE_CH4OUT_PB6 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x6)
1905 0 : #define LESENSE_CH4OUT_PB7 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x7)
1906 0 : #define LESENSE_CH5OUT_PA0 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x0)
1907 0 : #define LESENSE_CH5OUT_PA1 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x1)
1908 0 : #define LESENSE_CH5OUT_PA2 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x2)
1909 0 : #define LESENSE_CH5OUT_PA3 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x3)
1910 0 : #define LESENSE_CH5OUT_PA4 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x4)
1911 0 : #define LESENSE_CH5OUT_PA5 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x5)
1912 0 : #define LESENSE_CH5OUT_PA6 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x6)
1913 0 : #define LESENSE_CH5OUT_PA7 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x7)
1914 0 : #define LESENSE_CH5OUT_PA8 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x8)
1915 0 : #define LESENSE_CH5OUT_PA9 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x9)
1916 0 : #define LESENSE_CH5OUT_PA10 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xa)
1917 0 : #define LESENSE_CH5OUT_PA11 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xb)
1918 0 : #define LESENSE_CH5OUT_PA12 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xc)
1919 0 : #define LESENSE_CH5OUT_PA13 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xd)
1920 0 : #define LESENSE_CH5OUT_PA14 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xe)
1921 0 : #define LESENSE_CH5OUT_PB0 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x0)
1922 0 : #define LESENSE_CH5OUT_PB1 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x1)
1923 0 : #define LESENSE_CH5OUT_PB2 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x2)
1924 0 : #define LESENSE_CH5OUT_PB3 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x3)
1925 0 : #define LESENSE_CH5OUT_PB4 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x4)
1926 0 : #define LESENSE_CH5OUT_PB5 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x5)
1927 0 : #define LESENSE_CH5OUT_PB6 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x6)
1928 0 : #define LESENSE_CH5OUT_PB7 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x7)
1929 0 : #define LESENSE_CH6OUT_PA0 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x0)
1930 0 : #define LESENSE_CH6OUT_PA1 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x1)
1931 0 : #define LESENSE_CH6OUT_PA2 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x2)
1932 0 : #define LESENSE_CH6OUT_PA3 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x3)
1933 0 : #define LESENSE_CH6OUT_PA4 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x4)
1934 0 : #define LESENSE_CH6OUT_PA5 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x5)
1935 0 : #define LESENSE_CH6OUT_PA6 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x6)
1936 0 : #define LESENSE_CH6OUT_PA7 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x7)
1937 0 : #define LESENSE_CH6OUT_PA8 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x8)
1938 0 : #define LESENSE_CH6OUT_PA9 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x9)
1939 0 : #define LESENSE_CH6OUT_PA10 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xa)
1940 0 : #define LESENSE_CH6OUT_PA11 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xb)
1941 0 : #define LESENSE_CH6OUT_PA12 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xc)
1942 0 : #define LESENSE_CH6OUT_PA13 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xd)
1943 0 : #define LESENSE_CH6OUT_PA14 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xe)
1944 0 : #define LESENSE_CH6OUT_PB0 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x0)
1945 0 : #define LESENSE_CH6OUT_PB1 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x1)
1946 0 : #define LESENSE_CH6OUT_PB2 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x2)
1947 0 : #define LESENSE_CH6OUT_PB3 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x3)
1948 0 : #define LESENSE_CH6OUT_PB4 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x4)
1949 0 : #define LESENSE_CH6OUT_PB5 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x5)
1950 0 : #define LESENSE_CH6OUT_PB6 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x6)
1951 0 : #define LESENSE_CH6OUT_PB7 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x7)
1952 0 : #define LESENSE_CH7OUT_PA0 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x0)
1953 0 : #define LESENSE_CH7OUT_PA1 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x1)
1954 0 : #define LESENSE_CH7OUT_PA2 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x2)
1955 0 : #define LESENSE_CH7OUT_PA3 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x3)
1956 0 : #define LESENSE_CH7OUT_PA4 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x4)
1957 0 : #define LESENSE_CH7OUT_PA5 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x5)
1958 0 : #define LESENSE_CH7OUT_PA6 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x6)
1959 0 : #define LESENSE_CH7OUT_PA7 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x7)
1960 0 : #define LESENSE_CH7OUT_PA8 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x8)
1961 0 : #define LESENSE_CH7OUT_PA9 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x9)
1962 0 : #define LESENSE_CH7OUT_PA10 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xa)
1963 0 : #define LESENSE_CH7OUT_PA11 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xb)
1964 0 : #define LESENSE_CH7OUT_PA12 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xc)
1965 0 : #define LESENSE_CH7OUT_PA13 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xd)
1966 0 : #define LESENSE_CH7OUT_PA14 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xe)
1967 0 : #define LESENSE_CH7OUT_PB0 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x0)
1968 0 : #define LESENSE_CH7OUT_PB1 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x1)
1969 0 : #define LESENSE_CH7OUT_PB2 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x2)
1970 0 : #define LESENSE_CH7OUT_PB3 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x3)
1971 0 : #define LESENSE_CH7OUT_PB4 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x4)
1972 0 : #define LESENSE_CH7OUT_PB5 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x5)
1973 0 : #define LESENSE_CH7OUT_PB6 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x6)
1974 0 : #define LESENSE_CH7OUT_PB7 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x7)
1975 0 : #define LESENSE_CH8OUT_PA0 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x0)
1976 0 : #define LESENSE_CH8OUT_PA1 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x1)
1977 0 : #define LESENSE_CH8OUT_PA2 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x2)
1978 0 : #define LESENSE_CH8OUT_PA3 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x3)
1979 0 : #define LESENSE_CH8OUT_PA4 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x4)
1980 0 : #define LESENSE_CH8OUT_PA5 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x5)
1981 0 : #define LESENSE_CH8OUT_PA6 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x6)
1982 0 : #define LESENSE_CH8OUT_PA7 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x7)
1983 0 : #define LESENSE_CH8OUT_PA8 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x8)
1984 0 : #define LESENSE_CH8OUT_PA9 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x9)
1985 0 : #define LESENSE_CH8OUT_PA10 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xa)
1986 0 : #define LESENSE_CH8OUT_PA11 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xb)
1987 0 : #define LESENSE_CH8OUT_PA12 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xc)
1988 0 : #define LESENSE_CH8OUT_PA13 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xd)
1989 0 : #define LESENSE_CH8OUT_PA14 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xe)
1990 0 : #define LESENSE_CH8OUT_PB0 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x0)
1991 0 : #define LESENSE_CH8OUT_PB1 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x1)
1992 0 : #define LESENSE_CH8OUT_PB2 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x2)
1993 0 : #define LESENSE_CH8OUT_PB3 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x3)
1994 0 : #define LESENSE_CH8OUT_PB4 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x4)
1995 0 : #define LESENSE_CH8OUT_PB5 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x5)
1996 0 : #define LESENSE_CH8OUT_PB6 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x6)
1997 0 : #define LESENSE_CH8OUT_PB7 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x7)
1998 0 : #define LESENSE_CH9OUT_PA0 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x0)
1999 0 : #define LESENSE_CH9OUT_PA1 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x1)
2000 0 : #define LESENSE_CH9OUT_PA2 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x2)
2001 0 : #define LESENSE_CH9OUT_PA3 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x3)
2002 0 : #define LESENSE_CH9OUT_PA4 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x4)
2003 0 : #define LESENSE_CH9OUT_PA5 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x5)
2004 0 : #define LESENSE_CH9OUT_PA6 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x6)
2005 0 : #define LESENSE_CH9OUT_PA7 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x7)
2006 0 : #define LESENSE_CH9OUT_PA8 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x8)
2007 0 : #define LESENSE_CH9OUT_PA9 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x9)
2008 0 : #define LESENSE_CH9OUT_PA10 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xa)
2009 0 : #define LESENSE_CH9OUT_PA11 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xb)
2010 0 : #define LESENSE_CH9OUT_PA12 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xc)
2011 0 : #define LESENSE_CH9OUT_PA13 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xd)
2012 0 : #define LESENSE_CH9OUT_PA14 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xe)
2013 0 : #define LESENSE_CH9OUT_PB0 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x0)
2014 0 : #define LESENSE_CH9OUT_PB1 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x1)
2015 0 : #define LESENSE_CH9OUT_PB2 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x2)
2016 0 : #define LESENSE_CH9OUT_PB3 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x3)
2017 0 : #define LESENSE_CH9OUT_PB4 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x4)
2018 0 : #define LESENSE_CH9OUT_PB5 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x5)
2019 0 : #define LESENSE_CH9OUT_PB6 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x6)
2020 0 : #define LESENSE_CH9OUT_PB7 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x7)
2021 0 : #define LESENSE_CH10OUT_PA0 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x0)
2022 0 : #define LESENSE_CH10OUT_PA1 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x1)
2023 0 : #define LESENSE_CH10OUT_PA2 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x2)
2024 0 : #define LESENSE_CH10OUT_PA3 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x3)
2025 0 : #define LESENSE_CH10OUT_PA4 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x4)
2026 0 : #define LESENSE_CH10OUT_PA5 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x5)
2027 0 : #define LESENSE_CH10OUT_PA6 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x6)
2028 0 : #define LESENSE_CH10OUT_PA7 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x7)
2029 0 : #define LESENSE_CH10OUT_PA8 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x8)
2030 0 : #define LESENSE_CH10OUT_PA9 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x9)
2031 0 : #define LESENSE_CH10OUT_PA10 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xa)
2032 0 : #define LESENSE_CH10OUT_PA11 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xb)
2033 0 : #define LESENSE_CH10OUT_PA12 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xc)
2034 0 : #define LESENSE_CH10OUT_PA13 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xd)
2035 0 : #define LESENSE_CH10OUT_PA14 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xe)
2036 0 : #define LESENSE_CH10OUT_PB0 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x0)
2037 0 : #define LESENSE_CH10OUT_PB1 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x1)
2038 0 : #define LESENSE_CH10OUT_PB2 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x2)
2039 0 : #define LESENSE_CH10OUT_PB3 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x3)
2040 0 : #define LESENSE_CH10OUT_PB4 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x4)
2041 0 : #define LESENSE_CH10OUT_PB5 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x5)
2042 0 : #define LESENSE_CH10OUT_PB6 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x6)
2043 0 : #define LESENSE_CH10OUT_PB7 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x7)
2044 0 : #define LESENSE_CH11OUT_PA0 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x0)
2045 0 : #define LESENSE_CH11OUT_PA1 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x1)
2046 0 : #define LESENSE_CH11OUT_PA2 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x2)
2047 0 : #define LESENSE_CH11OUT_PA3 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x3)
2048 0 : #define LESENSE_CH11OUT_PA4 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x4)
2049 0 : #define LESENSE_CH11OUT_PA5 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x5)
2050 0 : #define LESENSE_CH11OUT_PA6 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x6)
2051 0 : #define LESENSE_CH11OUT_PA7 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x7)
2052 0 : #define LESENSE_CH11OUT_PA8 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x8)
2053 0 : #define LESENSE_CH11OUT_PA9 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x9)
2054 0 : #define LESENSE_CH11OUT_PA10 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xa)
2055 0 : #define LESENSE_CH11OUT_PA11 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xb)
2056 0 : #define LESENSE_CH11OUT_PA12 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xc)
2057 0 : #define LESENSE_CH11OUT_PA13 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xd)
2058 0 : #define LESENSE_CH11OUT_PA14 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xe)
2059 0 : #define LESENSE_CH11OUT_PB0 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x0)
2060 0 : #define LESENSE_CH11OUT_PB1 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x1)
2061 0 : #define LESENSE_CH11OUT_PB2 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x2)
2062 0 : #define LESENSE_CH11OUT_PB3 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x3)
2063 0 : #define LESENSE_CH11OUT_PB4 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x4)
2064 0 : #define LESENSE_CH11OUT_PB5 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x5)
2065 0 : #define LESENSE_CH11OUT_PB6 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x6)
2066 0 : #define LESENSE_CH11OUT_PB7 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x7)
2067 0 : #define LESENSE_CH12OUT_PA0 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x0)
2068 0 : #define LESENSE_CH12OUT_PA1 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x1)
2069 0 : #define LESENSE_CH12OUT_PA2 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x2)
2070 0 : #define LESENSE_CH12OUT_PA3 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x3)
2071 0 : #define LESENSE_CH12OUT_PA4 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x4)
2072 0 : #define LESENSE_CH12OUT_PA5 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x5)
2073 0 : #define LESENSE_CH12OUT_PA6 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x6)
2074 0 : #define LESENSE_CH12OUT_PA7 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x7)
2075 0 : #define LESENSE_CH12OUT_PA8 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x8)
2076 0 : #define LESENSE_CH12OUT_PA9 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x9)
2077 0 : #define LESENSE_CH12OUT_PA10 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xa)
2078 0 : #define LESENSE_CH12OUT_PA11 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xb)
2079 0 : #define LESENSE_CH12OUT_PA12 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xc)
2080 0 : #define LESENSE_CH12OUT_PA13 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xd)
2081 0 : #define LESENSE_CH12OUT_PA14 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xe)
2082 0 : #define LESENSE_CH12OUT_PB0 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x0)
2083 0 : #define LESENSE_CH12OUT_PB1 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x1)
2084 0 : #define LESENSE_CH12OUT_PB2 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x2)
2085 0 : #define LESENSE_CH12OUT_PB3 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x3)
2086 0 : #define LESENSE_CH12OUT_PB4 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x4)
2087 0 : #define LESENSE_CH12OUT_PB5 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x5)
2088 0 : #define LESENSE_CH12OUT_PB6 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x6)
2089 0 : #define LESENSE_CH12OUT_PB7 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x7)
2090 0 : #define LESENSE_CH13OUT_PA0 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x0)
2091 0 : #define LESENSE_CH13OUT_PA1 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x1)
2092 0 : #define LESENSE_CH13OUT_PA2 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x2)
2093 0 : #define LESENSE_CH13OUT_PA3 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x3)
2094 0 : #define LESENSE_CH13OUT_PA4 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x4)
2095 0 : #define LESENSE_CH13OUT_PA5 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x5)
2096 0 : #define LESENSE_CH13OUT_PA6 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x6)
2097 0 : #define LESENSE_CH13OUT_PA7 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x7)
2098 0 : #define LESENSE_CH13OUT_PA8 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x8)
2099 0 : #define LESENSE_CH13OUT_PA9 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x9)
2100 0 : #define LESENSE_CH13OUT_PA10 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xa)
2101 0 : #define LESENSE_CH13OUT_PA11 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xb)
2102 0 : #define LESENSE_CH13OUT_PA12 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xc)
2103 0 : #define LESENSE_CH13OUT_PA13 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xd)
2104 0 : #define LESENSE_CH13OUT_PA14 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xe)
2105 0 : #define LESENSE_CH13OUT_PB0 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x0)
2106 0 : #define LESENSE_CH13OUT_PB1 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x1)
2107 0 : #define LESENSE_CH13OUT_PB2 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x2)
2108 0 : #define LESENSE_CH13OUT_PB3 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x3)
2109 0 : #define LESENSE_CH13OUT_PB4 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x4)
2110 0 : #define LESENSE_CH13OUT_PB5 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x5)
2111 0 : #define LESENSE_CH13OUT_PB6 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x6)
2112 0 : #define LESENSE_CH13OUT_PB7 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x7)
2113 0 : #define LESENSE_CH14OUT_PA0 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x0)
2114 0 : #define LESENSE_CH14OUT_PA1 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x1)
2115 0 : #define LESENSE_CH14OUT_PA2 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x2)
2116 0 : #define LESENSE_CH14OUT_PA3 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x3)
2117 0 : #define LESENSE_CH14OUT_PA4 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x4)
2118 0 : #define LESENSE_CH14OUT_PA5 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x5)
2119 0 : #define LESENSE_CH14OUT_PA6 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x6)
2120 0 : #define LESENSE_CH14OUT_PA7 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x7)
2121 0 : #define LESENSE_CH14OUT_PA8 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x8)
2122 0 : #define LESENSE_CH14OUT_PA9 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x9)
2123 0 : #define LESENSE_CH14OUT_PA10 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xa)
2124 0 : #define LESENSE_CH14OUT_PA11 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xb)
2125 0 : #define LESENSE_CH14OUT_PA12 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xc)
2126 0 : #define LESENSE_CH14OUT_PA13 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xd)
2127 0 : #define LESENSE_CH14OUT_PA14 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xe)
2128 0 : #define LESENSE_CH14OUT_PB0 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x0)
2129 0 : #define LESENSE_CH14OUT_PB1 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x1)
2130 0 : #define LESENSE_CH14OUT_PB2 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x2)
2131 0 : #define LESENSE_CH14OUT_PB3 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x3)
2132 0 : #define LESENSE_CH14OUT_PB4 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x4)
2133 0 : #define LESENSE_CH14OUT_PB5 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x5)
2134 0 : #define LESENSE_CH14OUT_PB6 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x6)
2135 0 : #define LESENSE_CH14OUT_PB7 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x7)
2136 0 : #define LESENSE_CH15OUT_PA0 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x0)
2137 0 : #define LESENSE_CH15OUT_PA1 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x1)
2138 0 : #define LESENSE_CH15OUT_PA2 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x2)
2139 0 : #define LESENSE_CH15OUT_PA3 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x3)
2140 0 : #define LESENSE_CH15OUT_PA4 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x4)
2141 0 : #define LESENSE_CH15OUT_PA5 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x5)
2142 0 : #define LESENSE_CH15OUT_PA6 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x6)
2143 0 : #define LESENSE_CH15OUT_PA7 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x7)
2144 0 : #define LESENSE_CH15OUT_PA8 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x8)
2145 0 : #define LESENSE_CH15OUT_PA9 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x9)
2146 0 : #define LESENSE_CH15OUT_PA10 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xa)
2147 0 : #define LESENSE_CH15OUT_PA11 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xb)
2148 0 : #define LESENSE_CH15OUT_PA12 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xc)
2149 0 : #define LESENSE_CH15OUT_PA13 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xd)
2150 0 : #define LESENSE_CH15OUT_PA14 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xe)
2151 0 : #define LESENSE_CH15OUT_PB0 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x0)
2152 0 : #define LESENSE_CH15OUT_PB1 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x1)
2153 0 : #define LESENSE_CH15OUT_PB2 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x2)
2154 0 : #define LESENSE_CH15OUT_PB3 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x3)
2155 0 : #define LESENSE_CH15OUT_PB4 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x4)
2156 0 : #define LESENSE_CH15OUT_PB5 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x5)
2157 0 : #define LESENSE_CH15OUT_PB6 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x6)
2158 0 : #define LESENSE_CH15OUT_PB7 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x7)
2159 :
2160 0 : #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
2161 0 : #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
2162 0 : #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
2163 0 : #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
2164 0 : #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
2165 0 : #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
2166 0 : #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
2167 0 : #define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
2168 0 : #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
2169 0 : #define LETIMER0_OUT0_PA9 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x9)
2170 0 : #define LETIMER0_OUT0_PA10 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xa)
2171 0 : #define LETIMER0_OUT0_PA11 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xb)
2172 0 : #define LETIMER0_OUT0_PA12 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xc)
2173 0 : #define LETIMER0_OUT0_PA13 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xd)
2174 0 : #define LETIMER0_OUT0_PA14 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xe)
2175 0 : #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
2176 0 : #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
2177 0 : #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
2178 0 : #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
2179 0 : #define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
2180 0 : #define LETIMER0_OUT0_PB5 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x5)
2181 0 : #define LETIMER0_OUT0_PB6 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x6)
2182 0 : #define LETIMER0_OUT0_PB7 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x7)
2183 0 : #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
2184 0 : #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
2185 0 : #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
2186 0 : #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
2187 0 : #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
2188 0 : #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
2189 0 : #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
2190 0 : #define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
2191 0 : #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
2192 0 : #define LETIMER0_OUT1_PA9 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x9)
2193 0 : #define LETIMER0_OUT1_PA10 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xa)
2194 0 : #define LETIMER0_OUT1_PA11 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xb)
2195 0 : #define LETIMER0_OUT1_PA12 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xc)
2196 0 : #define LETIMER0_OUT1_PA13 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xd)
2197 0 : #define LETIMER0_OUT1_PA14 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xe)
2198 0 : #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
2199 0 : #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
2200 0 : #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
2201 0 : #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
2202 0 : #define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
2203 0 : #define LETIMER0_OUT1_PB5 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x5)
2204 0 : #define LETIMER0_OUT1_PB6 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x6)
2205 0 : #define LETIMER0_OUT1_PB7 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x7)
2206 :
2207 0 : #define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
2208 0 : #define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
2209 0 : #define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
2210 0 : #define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
2211 0 : #define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
2212 0 : #define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
2213 0 : #define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
2214 0 : #define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
2215 0 : #define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
2216 0 : #define MODEM_ANT0_PA9 SILABS_DBUS_MODEM_ANT0(0x0, 0x9)
2217 0 : #define MODEM_ANT0_PA10 SILABS_DBUS_MODEM_ANT0(0x0, 0xa)
2218 0 : #define MODEM_ANT0_PA11 SILABS_DBUS_MODEM_ANT0(0x0, 0xb)
2219 0 : #define MODEM_ANT0_PA12 SILABS_DBUS_MODEM_ANT0(0x0, 0xc)
2220 0 : #define MODEM_ANT0_PA13 SILABS_DBUS_MODEM_ANT0(0x0, 0xd)
2221 0 : #define MODEM_ANT0_PA14 SILABS_DBUS_MODEM_ANT0(0x0, 0xe)
2222 0 : #define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
2223 0 : #define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
2224 0 : #define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
2225 0 : #define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
2226 0 : #define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
2227 0 : #define MODEM_ANT0_PB5 SILABS_DBUS_MODEM_ANT0(0x1, 0x5)
2228 0 : #define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
2229 0 : #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
2230 0 : #define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
2231 0 : #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
2232 0 : #define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
2233 0 : #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
2234 0 : #define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
2235 0 : #define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
2236 0 : #define MODEM_ANT0_PC8 SILABS_DBUS_MODEM_ANT0(0x2, 0x8)
2237 0 : #define MODEM_ANT0_PC9 SILABS_DBUS_MODEM_ANT0(0x2, 0x9)
2238 0 : #define MODEM_ANT0_PC10 SILABS_DBUS_MODEM_ANT0(0x2, 0xa)
2239 0 : #define MODEM_ANT0_PC11 SILABS_DBUS_MODEM_ANT0(0x2, 0xb)
2240 0 : #define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
2241 0 : #define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
2242 0 : #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
2243 0 : #define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
2244 0 : #define MODEM_ANT0_PD4 SILABS_DBUS_MODEM_ANT0(0x3, 0x4)
2245 0 : #define MODEM_ANT0_PD5 SILABS_DBUS_MODEM_ANT0(0x3, 0x5)
2246 0 : #define MODEM_ANT0_PD6 SILABS_DBUS_MODEM_ANT0(0x3, 0x6)
2247 0 : #define MODEM_ANT0_PD7 SILABS_DBUS_MODEM_ANT0(0x3, 0x7)
2248 0 : #define MODEM_ANT0_PD8 SILABS_DBUS_MODEM_ANT0(0x3, 0x8)
2249 0 : #define MODEM_ANT0_PD9 SILABS_DBUS_MODEM_ANT0(0x3, 0x9)
2250 0 : #define MODEM_ANT0_PD10 SILABS_DBUS_MODEM_ANT0(0x3, 0xa)
2251 0 : #define MODEM_ANT0_PD11 SILABS_DBUS_MODEM_ANT0(0x3, 0xb)
2252 0 : #define MODEM_ANT0_PD12 SILABS_DBUS_MODEM_ANT0(0x3, 0xc)
2253 0 : #define MODEM_ANT0_PD13 SILABS_DBUS_MODEM_ANT0(0x3, 0xd)
2254 0 : #define MODEM_ANT0_PD14 SILABS_DBUS_MODEM_ANT0(0x3, 0xe)
2255 0 : #define MODEM_ANT0_PD15 SILABS_DBUS_MODEM_ANT0(0x3, 0xf)
2256 0 : #define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
2257 0 : #define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
2258 0 : #define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
2259 0 : #define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
2260 0 : #define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
2261 0 : #define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
2262 0 : #define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
2263 0 : #define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
2264 0 : #define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
2265 0 : #define MODEM_ANT1_PA9 SILABS_DBUS_MODEM_ANT1(0x0, 0x9)
2266 0 : #define MODEM_ANT1_PA10 SILABS_DBUS_MODEM_ANT1(0x0, 0xa)
2267 0 : #define MODEM_ANT1_PA11 SILABS_DBUS_MODEM_ANT1(0x0, 0xb)
2268 0 : #define MODEM_ANT1_PA12 SILABS_DBUS_MODEM_ANT1(0x0, 0xc)
2269 0 : #define MODEM_ANT1_PA13 SILABS_DBUS_MODEM_ANT1(0x0, 0xd)
2270 0 : #define MODEM_ANT1_PA14 SILABS_DBUS_MODEM_ANT1(0x0, 0xe)
2271 0 : #define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
2272 0 : #define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
2273 0 : #define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
2274 0 : #define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
2275 0 : #define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
2276 0 : #define MODEM_ANT1_PB5 SILABS_DBUS_MODEM_ANT1(0x1, 0x5)
2277 0 : #define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
2278 0 : #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
2279 0 : #define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
2280 0 : #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
2281 0 : #define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
2282 0 : #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
2283 0 : #define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
2284 0 : #define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
2285 0 : #define MODEM_ANT1_PC8 SILABS_DBUS_MODEM_ANT1(0x2, 0x8)
2286 0 : #define MODEM_ANT1_PC9 SILABS_DBUS_MODEM_ANT1(0x2, 0x9)
2287 0 : #define MODEM_ANT1_PC10 SILABS_DBUS_MODEM_ANT1(0x2, 0xa)
2288 0 : #define MODEM_ANT1_PC11 SILABS_DBUS_MODEM_ANT1(0x2, 0xb)
2289 0 : #define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
2290 0 : #define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
2291 0 : #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
2292 0 : #define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
2293 0 : #define MODEM_ANT1_PD4 SILABS_DBUS_MODEM_ANT1(0x3, 0x4)
2294 0 : #define MODEM_ANT1_PD5 SILABS_DBUS_MODEM_ANT1(0x3, 0x5)
2295 0 : #define MODEM_ANT1_PD6 SILABS_DBUS_MODEM_ANT1(0x3, 0x6)
2296 0 : #define MODEM_ANT1_PD7 SILABS_DBUS_MODEM_ANT1(0x3, 0x7)
2297 0 : #define MODEM_ANT1_PD8 SILABS_DBUS_MODEM_ANT1(0x3, 0x8)
2298 0 : #define MODEM_ANT1_PD9 SILABS_DBUS_MODEM_ANT1(0x3, 0x9)
2299 0 : #define MODEM_ANT1_PD10 SILABS_DBUS_MODEM_ANT1(0x3, 0xa)
2300 0 : #define MODEM_ANT1_PD11 SILABS_DBUS_MODEM_ANT1(0x3, 0xb)
2301 0 : #define MODEM_ANT1_PD12 SILABS_DBUS_MODEM_ANT1(0x3, 0xc)
2302 0 : #define MODEM_ANT1_PD13 SILABS_DBUS_MODEM_ANT1(0x3, 0xd)
2303 0 : #define MODEM_ANT1_PD14 SILABS_DBUS_MODEM_ANT1(0x3, 0xe)
2304 0 : #define MODEM_ANT1_PD15 SILABS_DBUS_MODEM_ANT1(0x3, 0xf)
2305 0 : #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
2306 0 : #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
2307 0 : #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
2308 0 : #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
2309 0 : #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
2310 0 : #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
2311 0 : #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
2312 0 : #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
2313 0 : #define MODEM_ANTROLLOVER_PC8 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x8)
2314 0 : #define MODEM_ANTROLLOVER_PC9 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x9)
2315 0 : #define MODEM_ANTROLLOVER_PC10 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xa)
2316 0 : #define MODEM_ANTROLLOVER_PC11 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0xb)
2317 0 : #define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
2318 0 : #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
2319 0 : #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
2320 0 : #define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
2321 0 : #define MODEM_ANTROLLOVER_PD4 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x4)
2322 0 : #define MODEM_ANTROLLOVER_PD5 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x5)
2323 0 : #define MODEM_ANTROLLOVER_PD6 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x6)
2324 0 : #define MODEM_ANTROLLOVER_PD7 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x7)
2325 0 : #define MODEM_ANTROLLOVER_PD8 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x8)
2326 0 : #define MODEM_ANTROLLOVER_PD9 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x9)
2327 0 : #define MODEM_ANTROLLOVER_PD10 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xa)
2328 0 : #define MODEM_ANTROLLOVER_PD11 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xb)
2329 0 : #define MODEM_ANTROLLOVER_PD12 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xc)
2330 0 : #define MODEM_ANTROLLOVER_PD13 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xd)
2331 0 : #define MODEM_ANTROLLOVER_PD14 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xe)
2332 0 : #define MODEM_ANTROLLOVER_PD15 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0xf)
2333 0 : #define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
2334 0 : #define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
2335 0 : #define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
2336 0 : #define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
2337 0 : #define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
2338 0 : #define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
2339 0 : #define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
2340 0 : #define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
2341 0 : #define MODEM_ANTRR0_PC8 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x8)
2342 0 : #define MODEM_ANTRR0_PC9 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x9)
2343 0 : #define MODEM_ANTRR0_PC10 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xa)
2344 0 : #define MODEM_ANTRR0_PC11 SILABS_DBUS_MODEM_ANTRR0(0x2, 0xb)
2345 0 : #define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
2346 0 : #define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
2347 0 : #define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
2348 0 : #define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
2349 0 : #define MODEM_ANTRR0_PD4 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x4)
2350 0 : #define MODEM_ANTRR0_PD5 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x5)
2351 0 : #define MODEM_ANTRR0_PD6 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x6)
2352 0 : #define MODEM_ANTRR0_PD7 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x7)
2353 0 : #define MODEM_ANTRR0_PD8 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x8)
2354 0 : #define MODEM_ANTRR0_PD9 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x9)
2355 0 : #define MODEM_ANTRR0_PD10 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xa)
2356 0 : #define MODEM_ANTRR0_PD11 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xb)
2357 0 : #define MODEM_ANTRR0_PD12 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xc)
2358 0 : #define MODEM_ANTRR0_PD13 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xd)
2359 0 : #define MODEM_ANTRR0_PD14 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xe)
2360 0 : #define MODEM_ANTRR0_PD15 SILABS_DBUS_MODEM_ANTRR0(0x3, 0xf)
2361 0 : #define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
2362 0 : #define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
2363 0 : #define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
2364 0 : #define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
2365 0 : #define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
2366 0 : #define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
2367 0 : #define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
2368 0 : #define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
2369 0 : #define MODEM_ANTRR1_PC8 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x8)
2370 0 : #define MODEM_ANTRR1_PC9 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x9)
2371 0 : #define MODEM_ANTRR1_PC10 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xa)
2372 0 : #define MODEM_ANTRR1_PC11 SILABS_DBUS_MODEM_ANTRR1(0x2, 0xb)
2373 0 : #define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
2374 0 : #define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
2375 0 : #define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
2376 0 : #define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
2377 0 : #define MODEM_ANTRR1_PD4 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x4)
2378 0 : #define MODEM_ANTRR1_PD5 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x5)
2379 0 : #define MODEM_ANTRR1_PD6 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x6)
2380 0 : #define MODEM_ANTRR1_PD7 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x7)
2381 0 : #define MODEM_ANTRR1_PD8 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x8)
2382 0 : #define MODEM_ANTRR1_PD9 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x9)
2383 0 : #define MODEM_ANTRR1_PD10 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xa)
2384 0 : #define MODEM_ANTRR1_PD11 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xb)
2385 0 : #define MODEM_ANTRR1_PD12 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xc)
2386 0 : #define MODEM_ANTRR1_PD13 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xd)
2387 0 : #define MODEM_ANTRR1_PD14 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xe)
2388 0 : #define MODEM_ANTRR1_PD15 SILABS_DBUS_MODEM_ANTRR1(0x3, 0xf)
2389 0 : #define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
2390 0 : #define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
2391 0 : #define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
2392 0 : #define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
2393 0 : #define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
2394 0 : #define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
2395 0 : #define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
2396 0 : #define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
2397 0 : #define MODEM_ANTRR2_PC8 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x8)
2398 0 : #define MODEM_ANTRR2_PC9 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x9)
2399 0 : #define MODEM_ANTRR2_PC10 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xa)
2400 0 : #define MODEM_ANTRR2_PC11 SILABS_DBUS_MODEM_ANTRR2(0x2, 0xb)
2401 0 : #define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
2402 0 : #define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
2403 0 : #define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
2404 0 : #define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
2405 0 : #define MODEM_ANTRR2_PD4 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x4)
2406 0 : #define MODEM_ANTRR2_PD5 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x5)
2407 0 : #define MODEM_ANTRR2_PD6 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x6)
2408 0 : #define MODEM_ANTRR2_PD7 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x7)
2409 0 : #define MODEM_ANTRR2_PD8 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x8)
2410 0 : #define MODEM_ANTRR2_PD9 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x9)
2411 0 : #define MODEM_ANTRR2_PD10 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xa)
2412 0 : #define MODEM_ANTRR2_PD11 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xb)
2413 0 : #define MODEM_ANTRR2_PD12 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xc)
2414 0 : #define MODEM_ANTRR2_PD13 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xd)
2415 0 : #define MODEM_ANTRR2_PD14 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xe)
2416 0 : #define MODEM_ANTRR2_PD15 SILABS_DBUS_MODEM_ANTRR2(0x3, 0xf)
2417 0 : #define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
2418 0 : #define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
2419 0 : #define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
2420 0 : #define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
2421 0 : #define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
2422 0 : #define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
2423 0 : #define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
2424 0 : #define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
2425 0 : #define MODEM_ANTRR3_PC8 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x8)
2426 0 : #define MODEM_ANTRR3_PC9 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x9)
2427 0 : #define MODEM_ANTRR3_PC10 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xa)
2428 0 : #define MODEM_ANTRR3_PC11 SILABS_DBUS_MODEM_ANTRR3(0x2, 0xb)
2429 0 : #define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
2430 0 : #define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
2431 0 : #define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
2432 0 : #define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
2433 0 : #define MODEM_ANTRR3_PD4 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x4)
2434 0 : #define MODEM_ANTRR3_PD5 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x5)
2435 0 : #define MODEM_ANTRR3_PD6 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x6)
2436 0 : #define MODEM_ANTRR3_PD7 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x7)
2437 0 : #define MODEM_ANTRR3_PD8 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x8)
2438 0 : #define MODEM_ANTRR3_PD9 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x9)
2439 0 : #define MODEM_ANTRR3_PD10 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xa)
2440 0 : #define MODEM_ANTRR3_PD11 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xb)
2441 0 : #define MODEM_ANTRR3_PD12 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xc)
2442 0 : #define MODEM_ANTRR3_PD13 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xd)
2443 0 : #define MODEM_ANTRR3_PD14 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xe)
2444 0 : #define MODEM_ANTRR3_PD15 SILABS_DBUS_MODEM_ANTRR3(0x3, 0xf)
2445 0 : #define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
2446 0 : #define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
2447 0 : #define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
2448 0 : #define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
2449 0 : #define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
2450 0 : #define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
2451 0 : #define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
2452 0 : #define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
2453 0 : #define MODEM_ANTRR4_PC8 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x8)
2454 0 : #define MODEM_ANTRR4_PC9 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x9)
2455 0 : #define MODEM_ANTRR4_PC10 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xa)
2456 0 : #define MODEM_ANTRR4_PC11 SILABS_DBUS_MODEM_ANTRR4(0x2, 0xb)
2457 0 : #define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
2458 0 : #define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
2459 0 : #define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
2460 0 : #define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
2461 0 : #define MODEM_ANTRR4_PD4 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x4)
2462 0 : #define MODEM_ANTRR4_PD5 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x5)
2463 0 : #define MODEM_ANTRR4_PD6 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x6)
2464 0 : #define MODEM_ANTRR4_PD7 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x7)
2465 0 : #define MODEM_ANTRR4_PD8 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x8)
2466 0 : #define MODEM_ANTRR4_PD9 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x9)
2467 0 : #define MODEM_ANTRR4_PD10 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xa)
2468 0 : #define MODEM_ANTRR4_PD11 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xb)
2469 0 : #define MODEM_ANTRR4_PD12 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xc)
2470 0 : #define MODEM_ANTRR4_PD13 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xd)
2471 0 : #define MODEM_ANTRR4_PD14 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xe)
2472 0 : #define MODEM_ANTRR4_PD15 SILABS_DBUS_MODEM_ANTRR4(0x3, 0xf)
2473 0 : #define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
2474 0 : #define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
2475 0 : #define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
2476 0 : #define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
2477 0 : #define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
2478 0 : #define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
2479 0 : #define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
2480 0 : #define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
2481 0 : #define MODEM_ANTRR5_PC8 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x8)
2482 0 : #define MODEM_ANTRR5_PC9 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x9)
2483 0 : #define MODEM_ANTRR5_PC10 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xa)
2484 0 : #define MODEM_ANTRR5_PC11 SILABS_DBUS_MODEM_ANTRR5(0x2, 0xb)
2485 0 : #define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
2486 0 : #define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
2487 0 : #define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
2488 0 : #define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
2489 0 : #define MODEM_ANTRR5_PD4 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x4)
2490 0 : #define MODEM_ANTRR5_PD5 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x5)
2491 0 : #define MODEM_ANTRR5_PD6 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x6)
2492 0 : #define MODEM_ANTRR5_PD7 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x7)
2493 0 : #define MODEM_ANTRR5_PD8 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x8)
2494 0 : #define MODEM_ANTRR5_PD9 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x9)
2495 0 : #define MODEM_ANTRR5_PD10 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xa)
2496 0 : #define MODEM_ANTRR5_PD11 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xb)
2497 0 : #define MODEM_ANTRR5_PD12 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xc)
2498 0 : #define MODEM_ANTRR5_PD13 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xd)
2499 0 : #define MODEM_ANTRR5_PD14 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xe)
2500 0 : #define MODEM_ANTRR5_PD15 SILABS_DBUS_MODEM_ANTRR5(0x3, 0xf)
2501 0 : #define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
2502 0 : #define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
2503 0 : #define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
2504 0 : #define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
2505 0 : #define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
2506 0 : #define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
2507 0 : #define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
2508 0 : #define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
2509 0 : #define MODEM_ANTSWEN_PC8 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x8)
2510 0 : #define MODEM_ANTSWEN_PC9 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x9)
2511 0 : #define MODEM_ANTSWEN_PC10 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xa)
2512 0 : #define MODEM_ANTSWEN_PC11 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0xb)
2513 0 : #define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
2514 0 : #define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
2515 0 : #define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
2516 0 : #define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
2517 0 : #define MODEM_ANTSWEN_PD4 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x4)
2518 0 : #define MODEM_ANTSWEN_PD5 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x5)
2519 0 : #define MODEM_ANTSWEN_PD6 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x6)
2520 0 : #define MODEM_ANTSWEN_PD7 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x7)
2521 0 : #define MODEM_ANTSWEN_PD8 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x8)
2522 0 : #define MODEM_ANTSWEN_PD9 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x9)
2523 0 : #define MODEM_ANTSWEN_PD10 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xa)
2524 0 : #define MODEM_ANTSWEN_PD11 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xb)
2525 0 : #define MODEM_ANTSWEN_PD12 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xc)
2526 0 : #define MODEM_ANTSWEN_PD13 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xd)
2527 0 : #define MODEM_ANTSWEN_PD14 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xe)
2528 0 : #define MODEM_ANTSWEN_PD15 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0xf)
2529 0 : #define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
2530 0 : #define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
2531 0 : #define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
2532 0 : #define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
2533 0 : #define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
2534 0 : #define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
2535 0 : #define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
2536 0 : #define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
2537 0 : #define MODEM_ANTSWUS_PC8 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x8)
2538 0 : #define MODEM_ANTSWUS_PC9 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x9)
2539 0 : #define MODEM_ANTSWUS_PC10 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xa)
2540 0 : #define MODEM_ANTSWUS_PC11 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0xb)
2541 0 : #define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
2542 0 : #define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
2543 0 : #define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
2544 0 : #define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
2545 0 : #define MODEM_ANTSWUS_PD4 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x4)
2546 0 : #define MODEM_ANTSWUS_PD5 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x5)
2547 0 : #define MODEM_ANTSWUS_PD6 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x6)
2548 0 : #define MODEM_ANTSWUS_PD7 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x7)
2549 0 : #define MODEM_ANTSWUS_PD8 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x8)
2550 0 : #define MODEM_ANTSWUS_PD9 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x9)
2551 0 : #define MODEM_ANTSWUS_PD10 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xa)
2552 0 : #define MODEM_ANTSWUS_PD11 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xb)
2553 0 : #define MODEM_ANTSWUS_PD12 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xc)
2554 0 : #define MODEM_ANTSWUS_PD13 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xd)
2555 0 : #define MODEM_ANTSWUS_PD14 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xe)
2556 0 : #define MODEM_ANTSWUS_PD15 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0xf)
2557 0 : #define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
2558 0 : #define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
2559 0 : #define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
2560 0 : #define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
2561 0 : #define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
2562 0 : #define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
2563 0 : #define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
2564 0 : #define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
2565 0 : #define MODEM_ANTTRIG_PC8 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x8)
2566 0 : #define MODEM_ANTTRIG_PC9 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x9)
2567 0 : #define MODEM_ANTTRIG_PC10 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xa)
2568 0 : #define MODEM_ANTTRIG_PC11 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0xb)
2569 0 : #define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
2570 0 : #define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
2571 0 : #define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
2572 0 : #define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
2573 0 : #define MODEM_ANTTRIG_PD4 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x4)
2574 0 : #define MODEM_ANTTRIG_PD5 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x5)
2575 0 : #define MODEM_ANTTRIG_PD6 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x6)
2576 0 : #define MODEM_ANTTRIG_PD7 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x7)
2577 0 : #define MODEM_ANTTRIG_PD8 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x8)
2578 0 : #define MODEM_ANTTRIG_PD9 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x9)
2579 0 : #define MODEM_ANTTRIG_PD10 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xa)
2580 0 : #define MODEM_ANTTRIG_PD11 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xb)
2581 0 : #define MODEM_ANTTRIG_PD12 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xc)
2582 0 : #define MODEM_ANTTRIG_PD13 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xd)
2583 0 : #define MODEM_ANTTRIG_PD14 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xe)
2584 0 : #define MODEM_ANTTRIG_PD15 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0xf)
2585 0 : #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
2586 0 : #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
2587 0 : #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
2588 0 : #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
2589 0 : #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
2590 0 : #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
2591 0 : #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
2592 0 : #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
2593 0 : #define MODEM_ANTTRIGSTOP_PC8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x8)
2594 0 : #define MODEM_ANTTRIGSTOP_PC9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x9)
2595 0 : #define MODEM_ANTTRIGSTOP_PC10 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xa)
2596 0 : #define MODEM_ANTTRIGSTOP_PC11 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0xb)
2597 0 : #define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
2598 0 : #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
2599 0 : #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
2600 0 : #define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
2601 0 : #define MODEM_ANTTRIGSTOP_PD4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x4)
2602 0 : #define MODEM_ANTTRIGSTOP_PD5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x5)
2603 0 : #define MODEM_ANTTRIGSTOP_PD6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x6)
2604 0 : #define MODEM_ANTTRIGSTOP_PD7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x7)
2605 0 : #define MODEM_ANTTRIGSTOP_PD8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x8)
2606 0 : #define MODEM_ANTTRIGSTOP_PD9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x9)
2607 0 : #define MODEM_ANTTRIGSTOP_PD10 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xa)
2608 0 : #define MODEM_ANTTRIGSTOP_PD11 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xb)
2609 0 : #define MODEM_ANTTRIGSTOP_PD12 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xc)
2610 0 : #define MODEM_ANTTRIGSTOP_PD13 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xd)
2611 0 : #define MODEM_ANTTRIGSTOP_PD14 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xe)
2612 0 : #define MODEM_ANTTRIGSTOP_PD15 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0xf)
2613 0 : #define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
2614 0 : #define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
2615 0 : #define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
2616 0 : #define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
2617 0 : #define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
2618 0 : #define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
2619 0 : #define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
2620 0 : #define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
2621 0 : #define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
2622 0 : #define MODEM_DCLK_PA9 SILABS_DBUS_MODEM_DCLK(0x0, 0x9)
2623 0 : #define MODEM_DCLK_PA10 SILABS_DBUS_MODEM_DCLK(0x0, 0xa)
2624 0 : #define MODEM_DCLK_PA11 SILABS_DBUS_MODEM_DCLK(0x0, 0xb)
2625 0 : #define MODEM_DCLK_PA12 SILABS_DBUS_MODEM_DCLK(0x0, 0xc)
2626 0 : #define MODEM_DCLK_PA13 SILABS_DBUS_MODEM_DCLK(0x0, 0xd)
2627 0 : #define MODEM_DCLK_PA14 SILABS_DBUS_MODEM_DCLK(0x0, 0xe)
2628 0 : #define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
2629 0 : #define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
2630 0 : #define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
2631 0 : #define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
2632 0 : #define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
2633 0 : #define MODEM_DCLK_PB5 SILABS_DBUS_MODEM_DCLK(0x1, 0x5)
2634 0 : #define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
2635 0 : #define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
2636 0 : #define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
2637 0 : #define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
2638 0 : #define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
2639 0 : #define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
2640 0 : #define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
2641 0 : #define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
2642 0 : #define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
2643 0 : #define MODEM_DOUT_PA9 SILABS_DBUS_MODEM_DOUT(0x0, 0x9)
2644 0 : #define MODEM_DOUT_PA10 SILABS_DBUS_MODEM_DOUT(0x0, 0xa)
2645 0 : #define MODEM_DOUT_PA11 SILABS_DBUS_MODEM_DOUT(0x0, 0xb)
2646 0 : #define MODEM_DOUT_PA12 SILABS_DBUS_MODEM_DOUT(0x0, 0xc)
2647 0 : #define MODEM_DOUT_PA13 SILABS_DBUS_MODEM_DOUT(0x0, 0xd)
2648 0 : #define MODEM_DOUT_PA14 SILABS_DBUS_MODEM_DOUT(0x0, 0xe)
2649 0 : #define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
2650 0 : #define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
2651 0 : #define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
2652 0 : #define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
2653 0 : #define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
2654 0 : #define MODEM_DOUT_PB5 SILABS_DBUS_MODEM_DOUT(0x1, 0x5)
2655 0 : #define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0)
2656 0 : #define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1)
2657 0 : #define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2)
2658 0 : #define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3)
2659 0 : #define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4)
2660 0 : #define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5)
2661 0 : #define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6)
2662 0 : #define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7)
2663 0 : #define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8)
2664 0 : #define MODEM_DIN_PA9 SILABS_DBUS_MODEM_DIN(0x0, 0x9)
2665 0 : #define MODEM_DIN_PA10 SILABS_DBUS_MODEM_DIN(0x0, 0xa)
2666 0 : #define MODEM_DIN_PA11 SILABS_DBUS_MODEM_DIN(0x0, 0xb)
2667 0 : #define MODEM_DIN_PA12 SILABS_DBUS_MODEM_DIN(0x0, 0xc)
2668 0 : #define MODEM_DIN_PA13 SILABS_DBUS_MODEM_DIN(0x0, 0xd)
2669 0 : #define MODEM_DIN_PA14 SILABS_DBUS_MODEM_DIN(0x0, 0xe)
2670 0 : #define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0)
2671 0 : #define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1)
2672 0 : #define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2)
2673 0 : #define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3)
2674 0 : #define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4)
2675 0 : #define MODEM_DIN_PB5 SILABS_DBUS_MODEM_DIN(0x1, 0x5)
2676 :
2677 0 : #define PCNT0_S0IN_PA0 SILABS_DBUS_PCNT0_S0IN(0x0, 0x0)
2678 0 : #define PCNT0_S0IN_PA1 SILABS_DBUS_PCNT0_S0IN(0x0, 0x1)
2679 0 : #define PCNT0_S0IN_PA2 SILABS_DBUS_PCNT0_S0IN(0x0, 0x2)
2680 0 : #define PCNT0_S0IN_PA3 SILABS_DBUS_PCNT0_S0IN(0x0, 0x3)
2681 0 : #define PCNT0_S0IN_PA4 SILABS_DBUS_PCNT0_S0IN(0x0, 0x4)
2682 0 : #define PCNT0_S0IN_PA5 SILABS_DBUS_PCNT0_S0IN(0x0, 0x5)
2683 0 : #define PCNT0_S0IN_PA6 SILABS_DBUS_PCNT0_S0IN(0x0, 0x6)
2684 0 : #define PCNT0_S0IN_PA7 SILABS_DBUS_PCNT0_S0IN(0x0, 0x7)
2685 0 : #define PCNT0_S0IN_PA8 SILABS_DBUS_PCNT0_S0IN(0x0, 0x8)
2686 0 : #define PCNT0_S0IN_PA9 SILABS_DBUS_PCNT0_S0IN(0x0, 0x9)
2687 0 : #define PCNT0_S0IN_PA10 SILABS_DBUS_PCNT0_S0IN(0x0, 0xa)
2688 0 : #define PCNT0_S0IN_PA11 SILABS_DBUS_PCNT0_S0IN(0x0, 0xb)
2689 0 : #define PCNT0_S0IN_PA12 SILABS_DBUS_PCNT0_S0IN(0x0, 0xc)
2690 0 : #define PCNT0_S0IN_PA13 SILABS_DBUS_PCNT0_S0IN(0x0, 0xd)
2691 0 : #define PCNT0_S0IN_PA14 SILABS_DBUS_PCNT0_S0IN(0x0, 0xe)
2692 0 : #define PCNT0_S0IN_PB0 SILABS_DBUS_PCNT0_S0IN(0x1, 0x0)
2693 0 : #define PCNT0_S0IN_PB1 SILABS_DBUS_PCNT0_S0IN(0x1, 0x1)
2694 0 : #define PCNT0_S0IN_PB2 SILABS_DBUS_PCNT0_S0IN(0x1, 0x2)
2695 0 : #define PCNT0_S0IN_PB3 SILABS_DBUS_PCNT0_S0IN(0x1, 0x3)
2696 0 : #define PCNT0_S0IN_PB4 SILABS_DBUS_PCNT0_S0IN(0x1, 0x4)
2697 0 : #define PCNT0_S0IN_PB5 SILABS_DBUS_PCNT0_S0IN(0x1, 0x5)
2698 0 : #define PCNT0_S0IN_PB6 SILABS_DBUS_PCNT0_S0IN(0x1, 0x6)
2699 0 : #define PCNT0_S0IN_PB7 SILABS_DBUS_PCNT0_S0IN(0x1, 0x7)
2700 0 : #define PCNT0_S1IN_PA0 SILABS_DBUS_PCNT0_S1IN(0x0, 0x0)
2701 0 : #define PCNT0_S1IN_PA1 SILABS_DBUS_PCNT0_S1IN(0x0, 0x1)
2702 0 : #define PCNT0_S1IN_PA2 SILABS_DBUS_PCNT0_S1IN(0x0, 0x2)
2703 0 : #define PCNT0_S1IN_PA3 SILABS_DBUS_PCNT0_S1IN(0x0, 0x3)
2704 0 : #define PCNT0_S1IN_PA4 SILABS_DBUS_PCNT0_S1IN(0x0, 0x4)
2705 0 : #define PCNT0_S1IN_PA5 SILABS_DBUS_PCNT0_S1IN(0x0, 0x5)
2706 0 : #define PCNT0_S1IN_PA6 SILABS_DBUS_PCNT0_S1IN(0x0, 0x6)
2707 0 : #define PCNT0_S1IN_PA7 SILABS_DBUS_PCNT0_S1IN(0x0, 0x7)
2708 0 : #define PCNT0_S1IN_PA8 SILABS_DBUS_PCNT0_S1IN(0x0, 0x8)
2709 0 : #define PCNT0_S1IN_PA9 SILABS_DBUS_PCNT0_S1IN(0x0, 0x9)
2710 0 : #define PCNT0_S1IN_PA10 SILABS_DBUS_PCNT0_S1IN(0x0, 0xa)
2711 0 : #define PCNT0_S1IN_PA11 SILABS_DBUS_PCNT0_S1IN(0x0, 0xb)
2712 0 : #define PCNT0_S1IN_PA12 SILABS_DBUS_PCNT0_S1IN(0x0, 0xc)
2713 0 : #define PCNT0_S1IN_PA13 SILABS_DBUS_PCNT0_S1IN(0x0, 0xd)
2714 0 : #define PCNT0_S1IN_PA14 SILABS_DBUS_PCNT0_S1IN(0x0, 0xe)
2715 0 : #define PCNT0_S1IN_PB0 SILABS_DBUS_PCNT0_S1IN(0x1, 0x0)
2716 0 : #define PCNT0_S1IN_PB1 SILABS_DBUS_PCNT0_S1IN(0x1, 0x1)
2717 0 : #define PCNT0_S1IN_PB2 SILABS_DBUS_PCNT0_S1IN(0x1, 0x2)
2718 0 : #define PCNT0_S1IN_PB3 SILABS_DBUS_PCNT0_S1IN(0x1, 0x3)
2719 0 : #define PCNT0_S1IN_PB4 SILABS_DBUS_PCNT0_S1IN(0x1, 0x4)
2720 0 : #define PCNT0_S1IN_PB5 SILABS_DBUS_PCNT0_S1IN(0x1, 0x5)
2721 0 : #define PCNT0_S1IN_PB6 SILABS_DBUS_PCNT0_S1IN(0x1, 0x6)
2722 0 : #define PCNT0_S1IN_PB7 SILABS_DBUS_PCNT0_S1IN(0x1, 0x7)
2723 :
2724 0 : #define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
2725 0 : #define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
2726 0 : #define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
2727 0 : #define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
2728 0 : #define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
2729 0 : #define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
2730 0 : #define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
2731 0 : #define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
2732 0 : #define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
2733 0 : #define PRS0_ASYNCH0_PA9 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x9)
2734 0 : #define PRS0_ASYNCH0_PA10 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xa)
2735 0 : #define PRS0_ASYNCH0_PA11 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xb)
2736 0 : #define PRS0_ASYNCH0_PA12 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xc)
2737 0 : #define PRS0_ASYNCH0_PA13 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xd)
2738 0 : #define PRS0_ASYNCH0_PA14 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xe)
2739 0 : #define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
2740 0 : #define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
2741 0 : #define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
2742 0 : #define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
2743 0 : #define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
2744 0 : #define PRS0_ASYNCH0_PB5 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x5)
2745 0 : #define PRS0_ASYNCH0_PB6 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x6)
2746 0 : #define PRS0_ASYNCH0_PB7 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x7)
2747 0 : #define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
2748 0 : #define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
2749 0 : #define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
2750 0 : #define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
2751 0 : #define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
2752 0 : #define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
2753 0 : #define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
2754 0 : #define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
2755 0 : #define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
2756 0 : #define PRS0_ASYNCH1_PA9 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x9)
2757 0 : #define PRS0_ASYNCH1_PA10 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xa)
2758 0 : #define PRS0_ASYNCH1_PA11 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xb)
2759 0 : #define PRS0_ASYNCH1_PA12 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xc)
2760 0 : #define PRS0_ASYNCH1_PA13 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xd)
2761 0 : #define PRS0_ASYNCH1_PA14 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xe)
2762 0 : #define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
2763 0 : #define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
2764 0 : #define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
2765 0 : #define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
2766 0 : #define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
2767 0 : #define PRS0_ASYNCH1_PB5 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x5)
2768 0 : #define PRS0_ASYNCH1_PB6 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x6)
2769 0 : #define PRS0_ASYNCH1_PB7 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x7)
2770 0 : #define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
2771 0 : #define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
2772 0 : #define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
2773 0 : #define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
2774 0 : #define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
2775 0 : #define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
2776 0 : #define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
2777 0 : #define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
2778 0 : #define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
2779 0 : #define PRS0_ASYNCH2_PA9 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x9)
2780 0 : #define PRS0_ASYNCH2_PA10 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xa)
2781 0 : #define PRS0_ASYNCH2_PA11 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xb)
2782 0 : #define PRS0_ASYNCH2_PA12 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xc)
2783 0 : #define PRS0_ASYNCH2_PA13 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xd)
2784 0 : #define PRS0_ASYNCH2_PA14 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xe)
2785 0 : #define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
2786 0 : #define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
2787 0 : #define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
2788 0 : #define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
2789 0 : #define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
2790 0 : #define PRS0_ASYNCH2_PB5 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x5)
2791 0 : #define PRS0_ASYNCH2_PB6 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x6)
2792 0 : #define PRS0_ASYNCH2_PB7 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x7)
2793 0 : #define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
2794 0 : #define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
2795 0 : #define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
2796 0 : #define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
2797 0 : #define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
2798 0 : #define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
2799 0 : #define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
2800 0 : #define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
2801 0 : #define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
2802 0 : #define PRS0_ASYNCH3_PA9 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x9)
2803 0 : #define PRS0_ASYNCH3_PA10 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xa)
2804 0 : #define PRS0_ASYNCH3_PA11 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xb)
2805 0 : #define PRS0_ASYNCH3_PA12 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xc)
2806 0 : #define PRS0_ASYNCH3_PA13 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xd)
2807 0 : #define PRS0_ASYNCH3_PA14 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xe)
2808 0 : #define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
2809 0 : #define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
2810 0 : #define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
2811 0 : #define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
2812 0 : #define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
2813 0 : #define PRS0_ASYNCH3_PB5 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x5)
2814 0 : #define PRS0_ASYNCH3_PB6 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x6)
2815 0 : #define PRS0_ASYNCH3_PB7 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x7)
2816 0 : #define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
2817 0 : #define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
2818 0 : #define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
2819 0 : #define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
2820 0 : #define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
2821 0 : #define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
2822 0 : #define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
2823 0 : #define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
2824 0 : #define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
2825 0 : #define PRS0_ASYNCH4_PA9 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x9)
2826 0 : #define PRS0_ASYNCH4_PA10 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xa)
2827 0 : #define PRS0_ASYNCH4_PA11 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xb)
2828 0 : #define PRS0_ASYNCH4_PA12 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xc)
2829 0 : #define PRS0_ASYNCH4_PA13 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xd)
2830 0 : #define PRS0_ASYNCH4_PA14 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xe)
2831 0 : #define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
2832 0 : #define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
2833 0 : #define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
2834 0 : #define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
2835 0 : #define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
2836 0 : #define PRS0_ASYNCH4_PB5 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x5)
2837 0 : #define PRS0_ASYNCH4_PB6 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x6)
2838 0 : #define PRS0_ASYNCH4_PB7 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x7)
2839 0 : #define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
2840 0 : #define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
2841 0 : #define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
2842 0 : #define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
2843 0 : #define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
2844 0 : #define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
2845 0 : #define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
2846 0 : #define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
2847 0 : #define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
2848 0 : #define PRS0_ASYNCH5_PA9 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x9)
2849 0 : #define PRS0_ASYNCH5_PA10 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xa)
2850 0 : #define PRS0_ASYNCH5_PA11 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xb)
2851 0 : #define PRS0_ASYNCH5_PA12 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xc)
2852 0 : #define PRS0_ASYNCH5_PA13 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xd)
2853 0 : #define PRS0_ASYNCH5_PA14 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xe)
2854 0 : #define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
2855 0 : #define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
2856 0 : #define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
2857 0 : #define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
2858 0 : #define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
2859 0 : #define PRS0_ASYNCH5_PB5 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x5)
2860 0 : #define PRS0_ASYNCH5_PB6 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x6)
2861 0 : #define PRS0_ASYNCH5_PB7 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x7)
2862 0 : #define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
2863 0 : #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
2864 0 : #define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
2865 0 : #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
2866 0 : #define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
2867 0 : #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
2868 0 : #define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
2869 0 : #define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
2870 0 : #define PRS0_ASYNCH6_PC8 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x8)
2871 0 : #define PRS0_ASYNCH6_PC9 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x9)
2872 0 : #define PRS0_ASYNCH6_PC10 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xa)
2873 0 : #define PRS0_ASYNCH6_PC11 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xb)
2874 0 : #define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
2875 0 : #define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
2876 0 : #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
2877 0 : #define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
2878 0 : #define PRS0_ASYNCH6_PD4 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x4)
2879 0 : #define PRS0_ASYNCH6_PD5 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x5)
2880 0 : #define PRS0_ASYNCH6_PD6 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x6)
2881 0 : #define PRS0_ASYNCH6_PD7 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x7)
2882 0 : #define PRS0_ASYNCH6_PD8 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x8)
2883 0 : #define PRS0_ASYNCH6_PD9 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x9)
2884 0 : #define PRS0_ASYNCH6_PD10 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xa)
2885 0 : #define PRS0_ASYNCH6_PD11 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xb)
2886 0 : #define PRS0_ASYNCH6_PD12 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xc)
2887 0 : #define PRS0_ASYNCH6_PD13 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xd)
2888 0 : #define PRS0_ASYNCH6_PD14 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xe)
2889 0 : #define PRS0_ASYNCH6_PD15 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xf)
2890 0 : #define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
2891 0 : #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
2892 0 : #define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
2893 0 : #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
2894 0 : #define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
2895 0 : #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
2896 0 : #define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
2897 0 : #define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
2898 0 : #define PRS0_ASYNCH7_PC8 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x8)
2899 0 : #define PRS0_ASYNCH7_PC9 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x9)
2900 0 : #define PRS0_ASYNCH7_PC10 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xa)
2901 0 : #define PRS0_ASYNCH7_PC11 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xb)
2902 0 : #define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
2903 0 : #define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
2904 0 : #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
2905 0 : #define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
2906 0 : #define PRS0_ASYNCH7_PD4 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x4)
2907 0 : #define PRS0_ASYNCH7_PD5 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x5)
2908 0 : #define PRS0_ASYNCH7_PD6 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x6)
2909 0 : #define PRS0_ASYNCH7_PD7 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x7)
2910 0 : #define PRS0_ASYNCH7_PD8 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x8)
2911 0 : #define PRS0_ASYNCH7_PD9 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x9)
2912 0 : #define PRS0_ASYNCH7_PD10 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xa)
2913 0 : #define PRS0_ASYNCH7_PD11 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xb)
2914 0 : #define PRS0_ASYNCH7_PD12 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xc)
2915 0 : #define PRS0_ASYNCH7_PD13 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xd)
2916 0 : #define PRS0_ASYNCH7_PD14 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xe)
2917 0 : #define PRS0_ASYNCH7_PD15 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xf)
2918 0 : #define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
2919 0 : #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
2920 0 : #define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
2921 0 : #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
2922 0 : #define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
2923 0 : #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
2924 0 : #define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
2925 0 : #define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
2926 0 : #define PRS0_ASYNCH8_PC8 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x8)
2927 0 : #define PRS0_ASYNCH8_PC9 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x9)
2928 0 : #define PRS0_ASYNCH8_PC10 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xa)
2929 0 : #define PRS0_ASYNCH8_PC11 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xb)
2930 0 : #define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
2931 0 : #define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
2932 0 : #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
2933 0 : #define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
2934 0 : #define PRS0_ASYNCH8_PD4 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x4)
2935 0 : #define PRS0_ASYNCH8_PD5 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x5)
2936 0 : #define PRS0_ASYNCH8_PD6 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x6)
2937 0 : #define PRS0_ASYNCH8_PD7 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x7)
2938 0 : #define PRS0_ASYNCH8_PD8 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x8)
2939 0 : #define PRS0_ASYNCH8_PD9 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x9)
2940 0 : #define PRS0_ASYNCH8_PD10 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xa)
2941 0 : #define PRS0_ASYNCH8_PD11 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xb)
2942 0 : #define PRS0_ASYNCH8_PD12 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xc)
2943 0 : #define PRS0_ASYNCH8_PD13 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xd)
2944 0 : #define PRS0_ASYNCH8_PD14 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xe)
2945 0 : #define PRS0_ASYNCH8_PD15 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xf)
2946 0 : #define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
2947 0 : #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
2948 0 : #define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
2949 0 : #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
2950 0 : #define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
2951 0 : #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
2952 0 : #define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
2953 0 : #define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
2954 0 : #define PRS0_ASYNCH9_PC8 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x8)
2955 0 : #define PRS0_ASYNCH9_PC9 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x9)
2956 0 : #define PRS0_ASYNCH9_PC10 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xa)
2957 0 : #define PRS0_ASYNCH9_PC11 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xb)
2958 0 : #define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
2959 0 : #define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
2960 0 : #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
2961 0 : #define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
2962 0 : #define PRS0_ASYNCH9_PD4 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x4)
2963 0 : #define PRS0_ASYNCH9_PD5 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x5)
2964 0 : #define PRS0_ASYNCH9_PD6 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x6)
2965 0 : #define PRS0_ASYNCH9_PD7 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x7)
2966 0 : #define PRS0_ASYNCH9_PD8 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x8)
2967 0 : #define PRS0_ASYNCH9_PD9 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x9)
2968 0 : #define PRS0_ASYNCH9_PD10 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xa)
2969 0 : #define PRS0_ASYNCH9_PD11 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xb)
2970 0 : #define PRS0_ASYNCH9_PD12 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xc)
2971 0 : #define PRS0_ASYNCH9_PD13 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xd)
2972 0 : #define PRS0_ASYNCH9_PD14 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xe)
2973 0 : #define PRS0_ASYNCH9_PD15 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xf)
2974 0 : #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
2975 0 : #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
2976 0 : #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
2977 0 : #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
2978 0 : #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
2979 0 : #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
2980 0 : #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
2981 0 : #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
2982 0 : #define PRS0_ASYNCH10_PC8 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x8)
2983 0 : #define PRS0_ASYNCH10_PC9 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x9)
2984 0 : #define PRS0_ASYNCH10_PC10 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xa)
2985 0 : #define PRS0_ASYNCH10_PC11 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xb)
2986 0 : #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
2987 0 : #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
2988 0 : #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
2989 0 : #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
2990 0 : #define PRS0_ASYNCH10_PD4 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x4)
2991 0 : #define PRS0_ASYNCH10_PD5 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x5)
2992 0 : #define PRS0_ASYNCH10_PD6 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x6)
2993 0 : #define PRS0_ASYNCH10_PD7 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x7)
2994 0 : #define PRS0_ASYNCH10_PD8 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x8)
2995 0 : #define PRS0_ASYNCH10_PD9 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x9)
2996 0 : #define PRS0_ASYNCH10_PD10 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xa)
2997 0 : #define PRS0_ASYNCH10_PD11 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xb)
2998 0 : #define PRS0_ASYNCH10_PD12 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xc)
2999 0 : #define PRS0_ASYNCH10_PD13 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xd)
3000 0 : #define PRS0_ASYNCH10_PD14 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xe)
3001 0 : #define PRS0_ASYNCH10_PD15 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xf)
3002 0 : #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
3003 0 : #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
3004 0 : #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
3005 0 : #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
3006 0 : #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
3007 0 : #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
3008 0 : #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
3009 0 : #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
3010 0 : #define PRS0_ASYNCH11_PC8 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x8)
3011 0 : #define PRS0_ASYNCH11_PC9 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x9)
3012 0 : #define PRS0_ASYNCH11_PC10 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xa)
3013 0 : #define PRS0_ASYNCH11_PC11 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xb)
3014 0 : #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
3015 0 : #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
3016 0 : #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
3017 0 : #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
3018 0 : #define PRS0_ASYNCH11_PD4 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x4)
3019 0 : #define PRS0_ASYNCH11_PD5 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x5)
3020 0 : #define PRS0_ASYNCH11_PD6 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x6)
3021 0 : #define PRS0_ASYNCH11_PD7 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x7)
3022 0 : #define PRS0_ASYNCH11_PD8 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x8)
3023 0 : #define PRS0_ASYNCH11_PD9 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x9)
3024 0 : #define PRS0_ASYNCH11_PD10 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xa)
3025 0 : #define PRS0_ASYNCH11_PD11 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xb)
3026 0 : #define PRS0_ASYNCH11_PD12 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xc)
3027 0 : #define PRS0_ASYNCH11_PD13 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xd)
3028 0 : #define PRS0_ASYNCH11_PD14 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xe)
3029 0 : #define PRS0_ASYNCH11_PD15 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xf)
3030 0 : #define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
3031 0 : #define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
3032 0 : #define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
3033 0 : #define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
3034 0 : #define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
3035 0 : #define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
3036 0 : #define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
3037 0 : #define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
3038 0 : #define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
3039 0 : #define PRS0_SYNCH0_PA9 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x9)
3040 0 : #define PRS0_SYNCH0_PA10 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xa)
3041 0 : #define PRS0_SYNCH0_PA11 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xb)
3042 0 : #define PRS0_SYNCH0_PA12 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xc)
3043 0 : #define PRS0_SYNCH0_PA13 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xd)
3044 0 : #define PRS0_SYNCH0_PA14 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xe)
3045 0 : #define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
3046 0 : #define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
3047 0 : #define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
3048 0 : #define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
3049 0 : #define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
3050 0 : #define PRS0_SYNCH0_PB5 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x5)
3051 0 : #define PRS0_SYNCH0_PB6 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x6)
3052 0 : #define PRS0_SYNCH0_PB7 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x7)
3053 0 : #define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
3054 0 : #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
3055 0 : #define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
3056 0 : #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
3057 0 : #define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
3058 0 : #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
3059 0 : #define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
3060 0 : #define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
3061 0 : #define PRS0_SYNCH0_PC8 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x8)
3062 0 : #define PRS0_SYNCH0_PC9 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x9)
3063 0 : #define PRS0_SYNCH0_PC10 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xa)
3064 0 : #define PRS0_SYNCH0_PC11 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xb)
3065 0 : #define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
3066 0 : #define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
3067 0 : #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
3068 0 : #define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
3069 0 : #define PRS0_SYNCH0_PD4 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x4)
3070 0 : #define PRS0_SYNCH0_PD5 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x5)
3071 0 : #define PRS0_SYNCH0_PD6 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x6)
3072 0 : #define PRS0_SYNCH0_PD7 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x7)
3073 0 : #define PRS0_SYNCH0_PD8 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x8)
3074 0 : #define PRS0_SYNCH0_PD9 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x9)
3075 0 : #define PRS0_SYNCH0_PD10 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xa)
3076 0 : #define PRS0_SYNCH0_PD11 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xb)
3077 0 : #define PRS0_SYNCH0_PD12 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xc)
3078 0 : #define PRS0_SYNCH0_PD13 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xd)
3079 0 : #define PRS0_SYNCH0_PD14 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xe)
3080 0 : #define PRS0_SYNCH0_PD15 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xf)
3081 0 : #define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
3082 0 : #define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
3083 0 : #define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
3084 0 : #define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
3085 0 : #define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
3086 0 : #define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
3087 0 : #define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
3088 0 : #define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
3089 0 : #define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
3090 0 : #define PRS0_SYNCH1_PA9 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x9)
3091 0 : #define PRS0_SYNCH1_PA10 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xa)
3092 0 : #define PRS0_SYNCH1_PA11 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xb)
3093 0 : #define PRS0_SYNCH1_PA12 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xc)
3094 0 : #define PRS0_SYNCH1_PA13 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xd)
3095 0 : #define PRS0_SYNCH1_PA14 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xe)
3096 0 : #define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
3097 0 : #define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
3098 0 : #define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
3099 0 : #define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
3100 0 : #define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
3101 0 : #define PRS0_SYNCH1_PB5 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x5)
3102 0 : #define PRS0_SYNCH1_PB6 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x6)
3103 0 : #define PRS0_SYNCH1_PB7 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x7)
3104 0 : #define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
3105 0 : #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
3106 0 : #define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
3107 0 : #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
3108 0 : #define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
3109 0 : #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
3110 0 : #define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
3111 0 : #define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
3112 0 : #define PRS0_SYNCH1_PC8 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x8)
3113 0 : #define PRS0_SYNCH1_PC9 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x9)
3114 0 : #define PRS0_SYNCH1_PC10 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xa)
3115 0 : #define PRS0_SYNCH1_PC11 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xb)
3116 0 : #define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
3117 0 : #define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
3118 0 : #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
3119 0 : #define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
3120 0 : #define PRS0_SYNCH1_PD4 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x4)
3121 0 : #define PRS0_SYNCH1_PD5 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x5)
3122 0 : #define PRS0_SYNCH1_PD6 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x6)
3123 0 : #define PRS0_SYNCH1_PD7 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x7)
3124 0 : #define PRS0_SYNCH1_PD8 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x8)
3125 0 : #define PRS0_SYNCH1_PD9 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x9)
3126 0 : #define PRS0_SYNCH1_PD10 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xa)
3127 0 : #define PRS0_SYNCH1_PD11 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xb)
3128 0 : #define PRS0_SYNCH1_PD12 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xc)
3129 0 : #define PRS0_SYNCH1_PD13 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xd)
3130 0 : #define PRS0_SYNCH1_PD14 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xe)
3131 0 : #define PRS0_SYNCH1_PD15 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xf)
3132 0 : #define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
3133 0 : #define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
3134 0 : #define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
3135 0 : #define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
3136 0 : #define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
3137 0 : #define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
3138 0 : #define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
3139 0 : #define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
3140 0 : #define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
3141 0 : #define PRS0_SYNCH2_PA9 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x9)
3142 0 : #define PRS0_SYNCH2_PA10 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xa)
3143 0 : #define PRS0_SYNCH2_PA11 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xb)
3144 0 : #define PRS0_SYNCH2_PA12 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xc)
3145 0 : #define PRS0_SYNCH2_PA13 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xd)
3146 0 : #define PRS0_SYNCH2_PA14 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xe)
3147 0 : #define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
3148 0 : #define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
3149 0 : #define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
3150 0 : #define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
3151 0 : #define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
3152 0 : #define PRS0_SYNCH2_PB5 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x5)
3153 0 : #define PRS0_SYNCH2_PB6 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x6)
3154 0 : #define PRS0_SYNCH2_PB7 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x7)
3155 0 : #define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
3156 0 : #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
3157 0 : #define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
3158 0 : #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
3159 0 : #define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
3160 0 : #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
3161 0 : #define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
3162 0 : #define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
3163 0 : #define PRS0_SYNCH2_PC8 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x8)
3164 0 : #define PRS0_SYNCH2_PC9 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x9)
3165 0 : #define PRS0_SYNCH2_PC10 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xa)
3166 0 : #define PRS0_SYNCH2_PC11 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xb)
3167 0 : #define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
3168 0 : #define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
3169 0 : #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
3170 0 : #define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
3171 0 : #define PRS0_SYNCH2_PD4 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x4)
3172 0 : #define PRS0_SYNCH2_PD5 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x5)
3173 0 : #define PRS0_SYNCH2_PD6 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x6)
3174 0 : #define PRS0_SYNCH2_PD7 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x7)
3175 0 : #define PRS0_SYNCH2_PD8 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x8)
3176 0 : #define PRS0_SYNCH2_PD9 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x9)
3177 0 : #define PRS0_SYNCH2_PD10 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xa)
3178 0 : #define PRS0_SYNCH2_PD11 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xb)
3179 0 : #define PRS0_SYNCH2_PD12 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xc)
3180 0 : #define PRS0_SYNCH2_PD13 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xd)
3181 0 : #define PRS0_SYNCH2_PD14 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xe)
3182 0 : #define PRS0_SYNCH2_PD15 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xf)
3183 0 : #define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
3184 0 : #define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
3185 0 : #define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
3186 0 : #define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
3187 0 : #define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
3188 0 : #define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
3189 0 : #define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
3190 0 : #define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
3191 0 : #define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
3192 0 : #define PRS0_SYNCH3_PA9 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x9)
3193 0 : #define PRS0_SYNCH3_PA10 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xa)
3194 0 : #define PRS0_SYNCH3_PA11 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xb)
3195 0 : #define PRS0_SYNCH3_PA12 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xc)
3196 0 : #define PRS0_SYNCH3_PA13 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xd)
3197 0 : #define PRS0_SYNCH3_PA14 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xe)
3198 0 : #define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
3199 0 : #define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
3200 0 : #define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
3201 0 : #define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
3202 0 : #define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
3203 0 : #define PRS0_SYNCH3_PB5 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x5)
3204 0 : #define PRS0_SYNCH3_PB6 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x6)
3205 0 : #define PRS0_SYNCH3_PB7 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x7)
3206 0 : #define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
3207 0 : #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
3208 0 : #define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
3209 0 : #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
3210 0 : #define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
3211 0 : #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
3212 0 : #define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
3213 0 : #define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
3214 0 : #define PRS0_SYNCH3_PC8 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x8)
3215 0 : #define PRS0_SYNCH3_PC9 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x9)
3216 0 : #define PRS0_SYNCH3_PC10 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xa)
3217 0 : #define PRS0_SYNCH3_PC11 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xb)
3218 0 : #define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
3219 0 : #define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
3220 0 : #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
3221 0 : #define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
3222 0 : #define PRS0_SYNCH3_PD4 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x4)
3223 0 : #define PRS0_SYNCH3_PD5 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x5)
3224 0 : #define PRS0_SYNCH3_PD6 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x6)
3225 0 : #define PRS0_SYNCH3_PD7 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x7)
3226 0 : #define PRS0_SYNCH3_PD8 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x8)
3227 0 : #define PRS0_SYNCH3_PD9 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x9)
3228 0 : #define PRS0_SYNCH3_PD10 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xa)
3229 0 : #define PRS0_SYNCH3_PD11 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xb)
3230 0 : #define PRS0_SYNCH3_PD12 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xc)
3231 0 : #define PRS0_SYNCH3_PD13 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xd)
3232 0 : #define PRS0_SYNCH3_PD14 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xe)
3233 0 : #define PRS0_SYNCH3_PD15 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xf)
3234 :
3235 0 : #define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
3236 0 : #define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
3237 0 : #define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
3238 0 : #define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
3239 0 : #define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
3240 0 : #define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
3241 0 : #define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
3242 0 : #define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
3243 0 : #define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
3244 0 : #define TIMER0_CC0_PA9 SILABS_DBUS_TIMER0_CC0(0x0, 0x9)
3245 0 : #define TIMER0_CC0_PA10 SILABS_DBUS_TIMER0_CC0(0x0, 0xa)
3246 0 : #define TIMER0_CC0_PA11 SILABS_DBUS_TIMER0_CC0(0x0, 0xb)
3247 0 : #define TIMER0_CC0_PA12 SILABS_DBUS_TIMER0_CC0(0x0, 0xc)
3248 0 : #define TIMER0_CC0_PA13 SILABS_DBUS_TIMER0_CC0(0x0, 0xd)
3249 0 : #define TIMER0_CC0_PA14 SILABS_DBUS_TIMER0_CC0(0x0, 0xe)
3250 0 : #define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
3251 0 : #define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
3252 0 : #define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
3253 0 : #define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
3254 0 : #define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
3255 0 : #define TIMER0_CC0_PB5 SILABS_DBUS_TIMER0_CC0(0x1, 0x5)
3256 0 : #define TIMER0_CC0_PB6 SILABS_DBUS_TIMER0_CC0(0x1, 0x6)
3257 0 : #define TIMER0_CC0_PB7 SILABS_DBUS_TIMER0_CC0(0x1, 0x7)
3258 0 : #define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
3259 0 : #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
3260 0 : #define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
3261 0 : #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
3262 0 : #define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
3263 0 : #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
3264 0 : #define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
3265 0 : #define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
3266 0 : #define TIMER0_CC0_PC8 SILABS_DBUS_TIMER0_CC0(0x2, 0x8)
3267 0 : #define TIMER0_CC0_PC9 SILABS_DBUS_TIMER0_CC0(0x2, 0x9)
3268 0 : #define TIMER0_CC0_PC10 SILABS_DBUS_TIMER0_CC0(0x2, 0xa)
3269 0 : #define TIMER0_CC0_PC11 SILABS_DBUS_TIMER0_CC0(0x2, 0xb)
3270 0 : #define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
3271 0 : #define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
3272 0 : #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
3273 0 : #define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
3274 0 : #define TIMER0_CC0_PD4 SILABS_DBUS_TIMER0_CC0(0x3, 0x4)
3275 0 : #define TIMER0_CC0_PD5 SILABS_DBUS_TIMER0_CC0(0x3, 0x5)
3276 0 : #define TIMER0_CC0_PD6 SILABS_DBUS_TIMER0_CC0(0x3, 0x6)
3277 0 : #define TIMER0_CC0_PD7 SILABS_DBUS_TIMER0_CC0(0x3, 0x7)
3278 0 : #define TIMER0_CC0_PD8 SILABS_DBUS_TIMER0_CC0(0x3, 0x8)
3279 0 : #define TIMER0_CC0_PD9 SILABS_DBUS_TIMER0_CC0(0x3, 0x9)
3280 0 : #define TIMER0_CC0_PD10 SILABS_DBUS_TIMER0_CC0(0x3, 0xa)
3281 0 : #define TIMER0_CC0_PD11 SILABS_DBUS_TIMER0_CC0(0x3, 0xb)
3282 0 : #define TIMER0_CC0_PD12 SILABS_DBUS_TIMER0_CC0(0x3, 0xc)
3283 0 : #define TIMER0_CC0_PD13 SILABS_DBUS_TIMER0_CC0(0x3, 0xd)
3284 0 : #define TIMER0_CC0_PD14 SILABS_DBUS_TIMER0_CC0(0x3, 0xe)
3285 0 : #define TIMER0_CC0_PD15 SILABS_DBUS_TIMER0_CC0(0x3, 0xf)
3286 0 : #define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
3287 0 : #define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
3288 0 : #define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
3289 0 : #define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
3290 0 : #define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
3291 0 : #define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
3292 0 : #define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
3293 0 : #define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
3294 0 : #define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
3295 0 : #define TIMER0_CC1_PA9 SILABS_DBUS_TIMER0_CC1(0x0, 0x9)
3296 0 : #define TIMER0_CC1_PA10 SILABS_DBUS_TIMER0_CC1(0x0, 0xa)
3297 0 : #define TIMER0_CC1_PA11 SILABS_DBUS_TIMER0_CC1(0x0, 0xb)
3298 0 : #define TIMER0_CC1_PA12 SILABS_DBUS_TIMER0_CC1(0x0, 0xc)
3299 0 : #define TIMER0_CC1_PA13 SILABS_DBUS_TIMER0_CC1(0x0, 0xd)
3300 0 : #define TIMER0_CC1_PA14 SILABS_DBUS_TIMER0_CC1(0x0, 0xe)
3301 0 : #define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
3302 0 : #define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
3303 0 : #define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
3304 0 : #define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
3305 0 : #define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
3306 0 : #define TIMER0_CC1_PB5 SILABS_DBUS_TIMER0_CC1(0x1, 0x5)
3307 0 : #define TIMER0_CC1_PB6 SILABS_DBUS_TIMER0_CC1(0x1, 0x6)
3308 0 : #define TIMER0_CC1_PB7 SILABS_DBUS_TIMER0_CC1(0x1, 0x7)
3309 0 : #define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
3310 0 : #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
3311 0 : #define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
3312 0 : #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
3313 0 : #define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
3314 0 : #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
3315 0 : #define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
3316 0 : #define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
3317 0 : #define TIMER0_CC1_PC8 SILABS_DBUS_TIMER0_CC1(0x2, 0x8)
3318 0 : #define TIMER0_CC1_PC9 SILABS_DBUS_TIMER0_CC1(0x2, 0x9)
3319 0 : #define TIMER0_CC1_PC10 SILABS_DBUS_TIMER0_CC1(0x2, 0xa)
3320 0 : #define TIMER0_CC1_PC11 SILABS_DBUS_TIMER0_CC1(0x2, 0xb)
3321 0 : #define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
3322 0 : #define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
3323 0 : #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
3324 0 : #define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
3325 0 : #define TIMER0_CC1_PD4 SILABS_DBUS_TIMER0_CC1(0x3, 0x4)
3326 0 : #define TIMER0_CC1_PD5 SILABS_DBUS_TIMER0_CC1(0x3, 0x5)
3327 0 : #define TIMER0_CC1_PD6 SILABS_DBUS_TIMER0_CC1(0x3, 0x6)
3328 0 : #define TIMER0_CC1_PD7 SILABS_DBUS_TIMER0_CC1(0x3, 0x7)
3329 0 : #define TIMER0_CC1_PD8 SILABS_DBUS_TIMER0_CC1(0x3, 0x8)
3330 0 : #define TIMER0_CC1_PD9 SILABS_DBUS_TIMER0_CC1(0x3, 0x9)
3331 0 : #define TIMER0_CC1_PD10 SILABS_DBUS_TIMER0_CC1(0x3, 0xa)
3332 0 : #define TIMER0_CC1_PD11 SILABS_DBUS_TIMER0_CC1(0x3, 0xb)
3333 0 : #define TIMER0_CC1_PD12 SILABS_DBUS_TIMER0_CC1(0x3, 0xc)
3334 0 : #define TIMER0_CC1_PD13 SILABS_DBUS_TIMER0_CC1(0x3, 0xd)
3335 0 : #define TIMER0_CC1_PD14 SILABS_DBUS_TIMER0_CC1(0x3, 0xe)
3336 0 : #define TIMER0_CC1_PD15 SILABS_DBUS_TIMER0_CC1(0x3, 0xf)
3337 0 : #define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
3338 0 : #define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
3339 0 : #define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
3340 0 : #define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
3341 0 : #define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
3342 0 : #define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
3343 0 : #define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
3344 0 : #define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
3345 0 : #define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
3346 0 : #define TIMER0_CC2_PA9 SILABS_DBUS_TIMER0_CC2(0x0, 0x9)
3347 0 : #define TIMER0_CC2_PA10 SILABS_DBUS_TIMER0_CC2(0x0, 0xa)
3348 0 : #define TIMER0_CC2_PA11 SILABS_DBUS_TIMER0_CC2(0x0, 0xb)
3349 0 : #define TIMER0_CC2_PA12 SILABS_DBUS_TIMER0_CC2(0x0, 0xc)
3350 0 : #define TIMER0_CC2_PA13 SILABS_DBUS_TIMER0_CC2(0x0, 0xd)
3351 0 : #define TIMER0_CC2_PA14 SILABS_DBUS_TIMER0_CC2(0x0, 0xe)
3352 0 : #define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
3353 0 : #define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
3354 0 : #define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
3355 0 : #define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
3356 0 : #define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
3357 0 : #define TIMER0_CC2_PB5 SILABS_DBUS_TIMER0_CC2(0x1, 0x5)
3358 0 : #define TIMER0_CC2_PB6 SILABS_DBUS_TIMER0_CC2(0x1, 0x6)
3359 0 : #define TIMER0_CC2_PB7 SILABS_DBUS_TIMER0_CC2(0x1, 0x7)
3360 0 : #define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
3361 0 : #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
3362 0 : #define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
3363 0 : #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
3364 0 : #define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
3365 0 : #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
3366 0 : #define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
3367 0 : #define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
3368 0 : #define TIMER0_CC2_PC8 SILABS_DBUS_TIMER0_CC2(0x2, 0x8)
3369 0 : #define TIMER0_CC2_PC9 SILABS_DBUS_TIMER0_CC2(0x2, 0x9)
3370 0 : #define TIMER0_CC2_PC10 SILABS_DBUS_TIMER0_CC2(0x2, 0xa)
3371 0 : #define TIMER0_CC2_PC11 SILABS_DBUS_TIMER0_CC2(0x2, 0xb)
3372 0 : #define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
3373 0 : #define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
3374 0 : #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
3375 0 : #define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
3376 0 : #define TIMER0_CC2_PD4 SILABS_DBUS_TIMER0_CC2(0x3, 0x4)
3377 0 : #define TIMER0_CC2_PD5 SILABS_DBUS_TIMER0_CC2(0x3, 0x5)
3378 0 : #define TIMER0_CC2_PD6 SILABS_DBUS_TIMER0_CC2(0x3, 0x6)
3379 0 : #define TIMER0_CC2_PD7 SILABS_DBUS_TIMER0_CC2(0x3, 0x7)
3380 0 : #define TIMER0_CC2_PD8 SILABS_DBUS_TIMER0_CC2(0x3, 0x8)
3381 0 : #define TIMER0_CC2_PD9 SILABS_DBUS_TIMER0_CC2(0x3, 0x9)
3382 0 : #define TIMER0_CC2_PD10 SILABS_DBUS_TIMER0_CC2(0x3, 0xa)
3383 0 : #define TIMER0_CC2_PD11 SILABS_DBUS_TIMER0_CC2(0x3, 0xb)
3384 0 : #define TIMER0_CC2_PD12 SILABS_DBUS_TIMER0_CC2(0x3, 0xc)
3385 0 : #define TIMER0_CC2_PD13 SILABS_DBUS_TIMER0_CC2(0x3, 0xd)
3386 0 : #define TIMER0_CC2_PD14 SILABS_DBUS_TIMER0_CC2(0x3, 0xe)
3387 0 : #define TIMER0_CC2_PD15 SILABS_DBUS_TIMER0_CC2(0x3, 0xf)
3388 0 : #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
3389 0 : #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
3390 0 : #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
3391 0 : #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
3392 0 : #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
3393 0 : #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
3394 0 : #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
3395 0 : #define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
3396 0 : #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
3397 0 : #define TIMER0_CDTI0_PA9 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x9)
3398 0 : #define TIMER0_CDTI0_PA10 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xa)
3399 0 : #define TIMER0_CDTI0_PA11 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xb)
3400 0 : #define TIMER0_CDTI0_PA12 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xc)
3401 0 : #define TIMER0_CDTI0_PA13 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xd)
3402 0 : #define TIMER0_CDTI0_PA14 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xe)
3403 0 : #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
3404 0 : #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
3405 0 : #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
3406 0 : #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
3407 0 : #define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
3408 0 : #define TIMER0_CDTI0_PB5 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x5)
3409 0 : #define TIMER0_CDTI0_PB6 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x6)
3410 0 : #define TIMER0_CDTI0_PB7 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x7)
3411 0 : #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
3412 0 : #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
3413 0 : #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
3414 0 : #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
3415 0 : #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
3416 0 : #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
3417 0 : #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
3418 0 : #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
3419 0 : #define TIMER0_CDTI0_PC8 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x8)
3420 0 : #define TIMER0_CDTI0_PC9 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x9)
3421 0 : #define TIMER0_CDTI0_PC10 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xa)
3422 0 : #define TIMER0_CDTI0_PC11 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xb)
3423 0 : #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
3424 0 : #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
3425 0 : #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
3426 0 : #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
3427 0 : #define TIMER0_CDTI0_PD4 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x4)
3428 0 : #define TIMER0_CDTI0_PD5 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x5)
3429 0 : #define TIMER0_CDTI0_PD6 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x6)
3430 0 : #define TIMER0_CDTI0_PD7 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x7)
3431 0 : #define TIMER0_CDTI0_PD8 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x8)
3432 0 : #define TIMER0_CDTI0_PD9 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x9)
3433 0 : #define TIMER0_CDTI0_PD10 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xa)
3434 0 : #define TIMER0_CDTI0_PD11 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xb)
3435 0 : #define TIMER0_CDTI0_PD12 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xc)
3436 0 : #define TIMER0_CDTI0_PD13 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xd)
3437 0 : #define TIMER0_CDTI0_PD14 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xe)
3438 0 : #define TIMER0_CDTI0_PD15 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xf)
3439 0 : #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
3440 0 : #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
3441 0 : #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
3442 0 : #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
3443 0 : #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
3444 0 : #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
3445 0 : #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
3446 0 : #define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
3447 0 : #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
3448 0 : #define TIMER0_CDTI1_PA9 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x9)
3449 0 : #define TIMER0_CDTI1_PA10 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xa)
3450 0 : #define TIMER0_CDTI1_PA11 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xb)
3451 0 : #define TIMER0_CDTI1_PA12 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xc)
3452 0 : #define TIMER0_CDTI1_PA13 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xd)
3453 0 : #define TIMER0_CDTI1_PA14 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xe)
3454 0 : #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
3455 0 : #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
3456 0 : #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
3457 0 : #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
3458 0 : #define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
3459 0 : #define TIMER0_CDTI1_PB5 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x5)
3460 0 : #define TIMER0_CDTI1_PB6 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x6)
3461 0 : #define TIMER0_CDTI1_PB7 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x7)
3462 0 : #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
3463 0 : #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
3464 0 : #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
3465 0 : #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
3466 0 : #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
3467 0 : #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
3468 0 : #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
3469 0 : #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
3470 0 : #define TIMER0_CDTI1_PC8 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x8)
3471 0 : #define TIMER0_CDTI1_PC9 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x9)
3472 0 : #define TIMER0_CDTI1_PC10 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xa)
3473 0 : #define TIMER0_CDTI1_PC11 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xb)
3474 0 : #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
3475 0 : #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
3476 0 : #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
3477 0 : #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
3478 0 : #define TIMER0_CDTI1_PD4 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x4)
3479 0 : #define TIMER0_CDTI1_PD5 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x5)
3480 0 : #define TIMER0_CDTI1_PD6 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x6)
3481 0 : #define TIMER0_CDTI1_PD7 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x7)
3482 0 : #define TIMER0_CDTI1_PD8 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x8)
3483 0 : #define TIMER0_CDTI1_PD9 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x9)
3484 0 : #define TIMER0_CDTI1_PD10 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xa)
3485 0 : #define TIMER0_CDTI1_PD11 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xb)
3486 0 : #define TIMER0_CDTI1_PD12 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xc)
3487 0 : #define TIMER0_CDTI1_PD13 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xd)
3488 0 : #define TIMER0_CDTI1_PD14 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xe)
3489 0 : #define TIMER0_CDTI1_PD15 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xf)
3490 0 : #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
3491 0 : #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
3492 0 : #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
3493 0 : #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
3494 0 : #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
3495 0 : #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
3496 0 : #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
3497 0 : #define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
3498 0 : #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
3499 0 : #define TIMER0_CDTI2_PA9 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x9)
3500 0 : #define TIMER0_CDTI2_PA10 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xa)
3501 0 : #define TIMER0_CDTI2_PA11 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xb)
3502 0 : #define TIMER0_CDTI2_PA12 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xc)
3503 0 : #define TIMER0_CDTI2_PA13 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xd)
3504 0 : #define TIMER0_CDTI2_PA14 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xe)
3505 0 : #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
3506 0 : #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
3507 0 : #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
3508 0 : #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
3509 0 : #define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
3510 0 : #define TIMER0_CDTI2_PB5 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x5)
3511 0 : #define TIMER0_CDTI2_PB6 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x6)
3512 0 : #define TIMER0_CDTI2_PB7 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x7)
3513 0 : #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
3514 0 : #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
3515 0 : #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
3516 0 : #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
3517 0 : #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
3518 0 : #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
3519 0 : #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
3520 0 : #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
3521 0 : #define TIMER0_CDTI2_PC8 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x8)
3522 0 : #define TIMER0_CDTI2_PC9 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x9)
3523 0 : #define TIMER0_CDTI2_PC10 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xa)
3524 0 : #define TIMER0_CDTI2_PC11 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xb)
3525 0 : #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
3526 0 : #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
3527 0 : #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
3528 0 : #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
3529 0 : #define TIMER0_CDTI2_PD4 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x4)
3530 0 : #define TIMER0_CDTI2_PD5 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x5)
3531 0 : #define TIMER0_CDTI2_PD6 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x6)
3532 0 : #define TIMER0_CDTI2_PD7 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x7)
3533 0 : #define TIMER0_CDTI2_PD8 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x8)
3534 0 : #define TIMER0_CDTI2_PD9 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x9)
3535 0 : #define TIMER0_CDTI2_PD10 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xa)
3536 0 : #define TIMER0_CDTI2_PD11 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xb)
3537 0 : #define TIMER0_CDTI2_PD12 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xc)
3538 0 : #define TIMER0_CDTI2_PD13 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xd)
3539 0 : #define TIMER0_CDTI2_PD14 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xe)
3540 0 : #define TIMER0_CDTI2_PD15 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xf)
3541 :
3542 0 : #define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
3543 0 : #define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
3544 0 : #define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
3545 0 : #define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
3546 0 : #define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
3547 0 : #define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
3548 0 : #define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
3549 0 : #define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
3550 0 : #define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
3551 0 : #define TIMER1_CC0_PA9 SILABS_DBUS_TIMER1_CC0(0x0, 0x9)
3552 0 : #define TIMER1_CC0_PA10 SILABS_DBUS_TIMER1_CC0(0x0, 0xa)
3553 0 : #define TIMER1_CC0_PA11 SILABS_DBUS_TIMER1_CC0(0x0, 0xb)
3554 0 : #define TIMER1_CC0_PA12 SILABS_DBUS_TIMER1_CC0(0x0, 0xc)
3555 0 : #define TIMER1_CC0_PA13 SILABS_DBUS_TIMER1_CC0(0x0, 0xd)
3556 0 : #define TIMER1_CC0_PA14 SILABS_DBUS_TIMER1_CC0(0x0, 0xe)
3557 0 : #define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
3558 0 : #define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
3559 0 : #define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
3560 0 : #define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
3561 0 : #define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
3562 0 : #define TIMER1_CC0_PB5 SILABS_DBUS_TIMER1_CC0(0x1, 0x5)
3563 0 : #define TIMER1_CC0_PB6 SILABS_DBUS_TIMER1_CC0(0x1, 0x6)
3564 0 : #define TIMER1_CC0_PB7 SILABS_DBUS_TIMER1_CC0(0x1, 0x7)
3565 0 : #define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
3566 0 : #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
3567 0 : #define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
3568 0 : #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
3569 0 : #define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
3570 0 : #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
3571 0 : #define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
3572 0 : #define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
3573 0 : #define TIMER1_CC0_PC8 SILABS_DBUS_TIMER1_CC0(0x2, 0x8)
3574 0 : #define TIMER1_CC0_PC9 SILABS_DBUS_TIMER1_CC0(0x2, 0x9)
3575 0 : #define TIMER1_CC0_PC10 SILABS_DBUS_TIMER1_CC0(0x2, 0xa)
3576 0 : #define TIMER1_CC0_PC11 SILABS_DBUS_TIMER1_CC0(0x2, 0xb)
3577 0 : #define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
3578 0 : #define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
3579 0 : #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
3580 0 : #define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
3581 0 : #define TIMER1_CC0_PD4 SILABS_DBUS_TIMER1_CC0(0x3, 0x4)
3582 0 : #define TIMER1_CC0_PD5 SILABS_DBUS_TIMER1_CC0(0x3, 0x5)
3583 0 : #define TIMER1_CC0_PD6 SILABS_DBUS_TIMER1_CC0(0x3, 0x6)
3584 0 : #define TIMER1_CC0_PD7 SILABS_DBUS_TIMER1_CC0(0x3, 0x7)
3585 0 : #define TIMER1_CC0_PD8 SILABS_DBUS_TIMER1_CC0(0x3, 0x8)
3586 0 : #define TIMER1_CC0_PD9 SILABS_DBUS_TIMER1_CC0(0x3, 0x9)
3587 0 : #define TIMER1_CC0_PD10 SILABS_DBUS_TIMER1_CC0(0x3, 0xa)
3588 0 : #define TIMER1_CC0_PD11 SILABS_DBUS_TIMER1_CC0(0x3, 0xb)
3589 0 : #define TIMER1_CC0_PD12 SILABS_DBUS_TIMER1_CC0(0x3, 0xc)
3590 0 : #define TIMER1_CC0_PD13 SILABS_DBUS_TIMER1_CC0(0x3, 0xd)
3591 0 : #define TIMER1_CC0_PD14 SILABS_DBUS_TIMER1_CC0(0x3, 0xe)
3592 0 : #define TIMER1_CC0_PD15 SILABS_DBUS_TIMER1_CC0(0x3, 0xf)
3593 0 : #define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
3594 0 : #define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
3595 0 : #define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
3596 0 : #define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
3597 0 : #define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
3598 0 : #define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
3599 0 : #define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
3600 0 : #define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
3601 0 : #define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
3602 0 : #define TIMER1_CC1_PA9 SILABS_DBUS_TIMER1_CC1(0x0, 0x9)
3603 0 : #define TIMER1_CC1_PA10 SILABS_DBUS_TIMER1_CC1(0x0, 0xa)
3604 0 : #define TIMER1_CC1_PA11 SILABS_DBUS_TIMER1_CC1(0x0, 0xb)
3605 0 : #define TIMER1_CC1_PA12 SILABS_DBUS_TIMER1_CC1(0x0, 0xc)
3606 0 : #define TIMER1_CC1_PA13 SILABS_DBUS_TIMER1_CC1(0x0, 0xd)
3607 0 : #define TIMER1_CC1_PA14 SILABS_DBUS_TIMER1_CC1(0x0, 0xe)
3608 0 : #define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
3609 0 : #define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
3610 0 : #define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
3611 0 : #define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
3612 0 : #define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
3613 0 : #define TIMER1_CC1_PB5 SILABS_DBUS_TIMER1_CC1(0x1, 0x5)
3614 0 : #define TIMER1_CC1_PB6 SILABS_DBUS_TIMER1_CC1(0x1, 0x6)
3615 0 : #define TIMER1_CC1_PB7 SILABS_DBUS_TIMER1_CC1(0x1, 0x7)
3616 0 : #define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
3617 0 : #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
3618 0 : #define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
3619 0 : #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
3620 0 : #define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
3621 0 : #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
3622 0 : #define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
3623 0 : #define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
3624 0 : #define TIMER1_CC1_PC8 SILABS_DBUS_TIMER1_CC1(0x2, 0x8)
3625 0 : #define TIMER1_CC1_PC9 SILABS_DBUS_TIMER1_CC1(0x2, 0x9)
3626 0 : #define TIMER1_CC1_PC10 SILABS_DBUS_TIMER1_CC1(0x2, 0xa)
3627 0 : #define TIMER1_CC1_PC11 SILABS_DBUS_TIMER1_CC1(0x2, 0xb)
3628 0 : #define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
3629 0 : #define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
3630 0 : #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
3631 0 : #define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
3632 0 : #define TIMER1_CC1_PD4 SILABS_DBUS_TIMER1_CC1(0x3, 0x4)
3633 0 : #define TIMER1_CC1_PD5 SILABS_DBUS_TIMER1_CC1(0x3, 0x5)
3634 0 : #define TIMER1_CC1_PD6 SILABS_DBUS_TIMER1_CC1(0x3, 0x6)
3635 0 : #define TIMER1_CC1_PD7 SILABS_DBUS_TIMER1_CC1(0x3, 0x7)
3636 0 : #define TIMER1_CC1_PD8 SILABS_DBUS_TIMER1_CC1(0x3, 0x8)
3637 0 : #define TIMER1_CC1_PD9 SILABS_DBUS_TIMER1_CC1(0x3, 0x9)
3638 0 : #define TIMER1_CC1_PD10 SILABS_DBUS_TIMER1_CC1(0x3, 0xa)
3639 0 : #define TIMER1_CC1_PD11 SILABS_DBUS_TIMER1_CC1(0x3, 0xb)
3640 0 : #define TIMER1_CC1_PD12 SILABS_DBUS_TIMER1_CC1(0x3, 0xc)
3641 0 : #define TIMER1_CC1_PD13 SILABS_DBUS_TIMER1_CC1(0x3, 0xd)
3642 0 : #define TIMER1_CC1_PD14 SILABS_DBUS_TIMER1_CC1(0x3, 0xe)
3643 0 : #define TIMER1_CC1_PD15 SILABS_DBUS_TIMER1_CC1(0x3, 0xf)
3644 0 : #define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
3645 0 : #define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
3646 0 : #define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
3647 0 : #define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
3648 0 : #define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
3649 0 : #define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
3650 0 : #define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
3651 0 : #define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
3652 0 : #define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
3653 0 : #define TIMER1_CC2_PA9 SILABS_DBUS_TIMER1_CC2(0x0, 0x9)
3654 0 : #define TIMER1_CC2_PA10 SILABS_DBUS_TIMER1_CC2(0x0, 0xa)
3655 0 : #define TIMER1_CC2_PA11 SILABS_DBUS_TIMER1_CC2(0x0, 0xb)
3656 0 : #define TIMER1_CC2_PA12 SILABS_DBUS_TIMER1_CC2(0x0, 0xc)
3657 0 : #define TIMER1_CC2_PA13 SILABS_DBUS_TIMER1_CC2(0x0, 0xd)
3658 0 : #define TIMER1_CC2_PA14 SILABS_DBUS_TIMER1_CC2(0x0, 0xe)
3659 0 : #define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
3660 0 : #define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
3661 0 : #define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
3662 0 : #define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
3663 0 : #define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
3664 0 : #define TIMER1_CC2_PB5 SILABS_DBUS_TIMER1_CC2(0x1, 0x5)
3665 0 : #define TIMER1_CC2_PB6 SILABS_DBUS_TIMER1_CC2(0x1, 0x6)
3666 0 : #define TIMER1_CC2_PB7 SILABS_DBUS_TIMER1_CC2(0x1, 0x7)
3667 0 : #define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
3668 0 : #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
3669 0 : #define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
3670 0 : #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
3671 0 : #define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
3672 0 : #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
3673 0 : #define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
3674 0 : #define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
3675 0 : #define TIMER1_CC2_PC8 SILABS_DBUS_TIMER1_CC2(0x2, 0x8)
3676 0 : #define TIMER1_CC2_PC9 SILABS_DBUS_TIMER1_CC2(0x2, 0x9)
3677 0 : #define TIMER1_CC2_PC10 SILABS_DBUS_TIMER1_CC2(0x2, 0xa)
3678 0 : #define TIMER1_CC2_PC11 SILABS_DBUS_TIMER1_CC2(0x2, 0xb)
3679 0 : #define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
3680 0 : #define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
3681 0 : #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
3682 0 : #define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
3683 0 : #define TIMER1_CC2_PD4 SILABS_DBUS_TIMER1_CC2(0x3, 0x4)
3684 0 : #define TIMER1_CC2_PD5 SILABS_DBUS_TIMER1_CC2(0x3, 0x5)
3685 0 : #define TIMER1_CC2_PD6 SILABS_DBUS_TIMER1_CC2(0x3, 0x6)
3686 0 : #define TIMER1_CC2_PD7 SILABS_DBUS_TIMER1_CC2(0x3, 0x7)
3687 0 : #define TIMER1_CC2_PD8 SILABS_DBUS_TIMER1_CC2(0x3, 0x8)
3688 0 : #define TIMER1_CC2_PD9 SILABS_DBUS_TIMER1_CC2(0x3, 0x9)
3689 0 : #define TIMER1_CC2_PD10 SILABS_DBUS_TIMER1_CC2(0x3, 0xa)
3690 0 : #define TIMER1_CC2_PD11 SILABS_DBUS_TIMER1_CC2(0x3, 0xb)
3691 0 : #define TIMER1_CC2_PD12 SILABS_DBUS_TIMER1_CC2(0x3, 0xc)
3692 0 : #define TIMER1_CC2_PD13 SILABS_DBUS_TIMER1_CC2(0x3, 0xd)
3693 0 : #define TIMER1_CC2_PD14 SILABS_DBUS_TIMER1_CC2(0x3, 0xe)
3694 0 : #define TIMER1_CC2_PD15 SILABS_DBUS_TIMER1_CC2(0x3, 0xf)
3695 0 : #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
3696 0 : #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
3697 0 : #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
3698 0 : #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
3699 0 : #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
3700 0 : #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
3701 0 : #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
3702 0 : #define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
3703 0 : #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
3704 0 : #define TIMER1_CDTI0_PA9 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x9)
3705 0 : #define TIMER1_CDTI0_PA10 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xa)
3706 0 : #define TIMER1_CDTI0_PA11 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xb)
3707 0 : #define TIMER1_CDTI0_PA12 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xc)
3708 0 : #define TIMER1_CDTI0_PA13 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xd)
3709 0 : #define TIMER1_CDTI0_PA14 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xe)
3710 0 : #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
3711 0 : #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
3712 0 : #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
3713 0 : #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
3714 0 : #define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
3715 0 : #define TIMER1_CDTI0_PB5 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x5)
3716 0 : #define TIMER1_CDTI0_PB6 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x6)
3717 0 : #define TIMER1_CDTI0_PB7 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x7)
3718 0 : #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
3719 0 : #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
3720 0 : #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
3721 0 : #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
3722 0 : #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
3723 0 : #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
3724 0 : #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
3725 0 : #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
3726 0 : #define TIMER1_CDTI0_PC8 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x8)
3727 0 : #define TIMER1_CDTI0_PC9 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x9)
3728 0 : #define TIMER1_CDTI0_PC10 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xa)
3729 0 : #define TIMER1_CDTI0_PC11 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xb)
3730 0 : #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
3731 0 : #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
3732 0 : #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
3733 0 : #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
3734 0 : #define TIMER1_CDTI0_PD4 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x4)
3735 0 : #define TIMER1_CDTI0_PD5 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x5)
3736 0 : #define TIMER1_CDTI0_PD6 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x6)
3737 0 : #define TIMER1_CDTI0_PD7 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x7)
3738 0 : #define TIMER1_CDTI0_PD8 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x8)
3739 0 : #define TIMER1_CDTI0_PD9 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x9)
3740 0 : #define TIMER1_CDTI0_PD10 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xa)
3741 0 : #define TIMER1_CDTI0_PD11 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xb)
3742 0 : #define TIMER1_CDTI0_PD12 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xc)
3743 0 : #define TIMER1_CDTI0_PD13 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xd)
3744 0 : #define TIMER1_CDTI0_PD14 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xe)
3745 0 : #define TIMER1_CDTI0_PD15 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xf)
3746 0 : #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
3747 0 : #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
3748 0 : #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
3749 0 : #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
3750 0 : #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
3751 0 : #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
3752 0 : #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
3753 0 : #define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
3754 0 : #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
3755 0 : #define TIMER1_CDTI1_PA9 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x9)
3756 0 : #define TIMER1_CDTI1_PA10 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xa)
3757 0 : #define TIMER1_CDTI1_PA11 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xb)
3758 0 : #define TIMER1_CDTI1_PA12 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xc)
3759 0 : #define TIMER1_CDTI1_PA13 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xd)
3760 0 : #define TIMER1_CDTI1_PA14 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xe)
3761 0 : #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
3762 0 : #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
3763 0 : #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
3764 0 : #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
3765 0 : #define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
3766 0 : #define TIMER1_CDTI1_PB5 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x5)
3767 0 : #define TIMER1_CDTI1_PB6 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x6)
3768 0 : #define TIMER1_CDTI1_PB7 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x7)
3769 0 : #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
3770 0 : #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
3771 0 : #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
3772 0 : #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
3773 0 : #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
3774 0 : #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
3775 0 : #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
3776 0 : #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
3777 0 : #define TIMER1_CDTI1_PC8 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x8)
3778 0 : #define TIMER1_CDTI1_PC9 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x9)
3779 0 : #define TIMER1_CDTI1_PC10 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xa)
3780 0 : #define TIMER1_CDTI1_PC11 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xb)
3781 0 : #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
3782 0 : #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
3783 0 : #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
3784 0 : #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
3785 0 : #define TIMER1_CDTI1_PD4 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x4)
3786 0 : #define TIMER1_CDTI1_PD5 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x5)
3787 0 : #define TIMER1_CDTI1_PD6 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x6)
3788 0 : #define TIMER1_CDTI1_PD7 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x7)
3789 0 : #define TIMER1_CDTI1_PD8 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x8)
3790 0 : #define TIMER1_CDTI1_PD9 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x9)
3791 0 : #define TIMER1_CDTI1_PD10 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xa)
3792 0 : #define TIMER1_CDTI1_PD11 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xb)
3793 0 : #define TIMER1_CDTI1_PD12 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xc)
3794 0 : #define TIMER1_CDTI1_PD13 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xd)
3795 0 : #define TIMER1_CDTI1_PD14 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xe)
3796 0 : #define TIMER1_CDTI1_PD15 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xf)
3797 0 : #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
3798 0 : #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
3799 0 : #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
3800 0 : #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
3801 0 : #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
3802 0 : #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
3803 0 : #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
3804 0 : #define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
3805 0 : #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
3806 0 : #define TIMER1_CDTI2_PA9 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x9)
3807 0 : #define TIMER1_CDTI2_PA10 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xa)
3808 0 : #define TIMER1_CDTI2_PA11 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xb)
3809 0 : #define TIMER1_CDTI2_PA12 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xc)
3810 0 : #define TIMER1_CDTI2_PA13 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xd)
3811 0 : #define TIMER1_CDTI2_PA14 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xe)
3812 0 : #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
3813 0 : #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
3814 0 : #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
3815 0 : #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
3816 0 : #define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
3817 0 : #define TIMER1_CDTI2_PB5 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x5)
3818 0 : #define TIMER1_CDTI2_PB6 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x6)
3819 0 : #define TIMER1_CDTI2_PB7 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x7)
3820 0 : #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
3821 0 : #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
3822 0 : #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
3823 0 : #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
3824 0 : #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
3825 0 : #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
3826 0 : #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
3827 0 : #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
3828 0 : #define TIMER1_CDTI2_PC8 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x8)
3829 0 : #define TIMER1_CDTI2_PC9 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x9)
3830 0 : #define TIMER1_CDTI2_PC10 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xa)
3831 0 : #define TIMER1_CDTI2_PC11 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xb)
3832 0 : #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
3833 0 : #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
3834 0 : #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
3835 0 : #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
3836 0 : #define TIMER1_CDTI2_PD4 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x4)
3837 0 : #define TIMER1_CDTI2_PD5 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x5)
3838 0 : #define TIMER1_CDTI2_PD6 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x6)
3839 0 : #define TIMER1_CDTI2_PD7 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x7)
3840 0 : #define TIMER1_CDTI2_PD8 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x8)
3841 0 : #define TIMER1_CDTI2_PD9 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x9)
3842 0 : #define TIMER1_CDTI2_PD10 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xa)
3843 0 : #define TIMER1_CDTI2_PD11 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xb)
3844 0 : #define TIMER1_CDTI2_PD12 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xc)
3845 0 : #define TIMER1_CDTI2_PD13 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xd)
3846 0 : #define TIMER1_CDTI2_PD14 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xe)
3847 0 : #define TIMER1_CDTI2_PD15 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xf)
3848 :
3849 0 : #define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
3850 0 : #define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
3851 0 : #define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
3852 0 : #define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
3853 0 : #define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
3854 0 : #define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
3855 0 : #define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
3856 0 : #define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
3857 0 : #define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
3858 0 : #define TIMER2_CC0_PA9 SILABS_DBUS_TIMER2_CC0(0x0, 0x9)
3859 0 : #define TIMER2_CC0_PA10 SILABS_DBUS_TIMER2_CC0(0x0, 0xa)
3860 0 : #define TIMER2_CC0_PA11 SILABS_DBUS_TIMER2_CC0(0x0, 0xb)
3861 0 : #define TIMER2_CC0_PA12 SILABS_DBUS_TIMER2_CC0(0x0, 0xc)
3862 0 : #define TIMER2_CC0_PA13 SILABS_DBUS_TIMER2_CC0(0x0, 0xd)
3863 0 : #define TIMER2_CC0_PA14 SILABS_DBUS_TIMER2_CC0(0x0, 0xe)
3864 0 : #define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
3865 0 : #define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
3866 0 : #define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
3867 0 : #define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
3868 0 : #define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
3869 0 : #define TIMER2_CC0_PB5 SILABS_DBUS_TIMER2_CC0(0x1, 0x5)
3870 0 : #define TIMER2_CC0_PB6 SILABS_DBUS_TIMER2_CC0(0x1, 0x6)
3871 0 : #define TIMER2_CC0_PB7 SILABS_DBUS_TIMER2_CC0(0x1, 0x7)
3872 0 : #define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
3873 0 : #define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
3874 0 : #define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
3875 0 : #define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
3876 0 : #define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
3877 0 : #define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
3878 0 : #define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
3879 0 : #define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
3880 0 : #define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
3881 0 : #define TIMER2_CC1_PA9 SILABS_DBUS_TIMER2_CC1(0x0, 0x9)
3882 0 : #define TIMER2_CC1_PA10 SILABS_DBUS_TIMER2_CC1(0x0, 0xa)
3883 0 : #define TIMER2_CC1_PA11 SILABS_DBUS_TIMER2_CC1(0x0, 0xb)
3884 0 : #define TIMER2_CC1_PA12 SILABS_DBUS_TIMER2_CC1(0x0, 0xc)
3885 0 : #define TIMER2_CC1_PA13 SILABS_DBUS_TIMER2_CC1(0x0, 0xd)
3886 0 : #define TIMER2_CC1_PA14 SILABS_DBUS_TIMER2_CC1(0x0, 0xe)
3887 0 : #define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
3888 0 : #define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
3889 0 : #define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
3890 0 : #define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
3891 0 : #define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
3892 0 : #define TIMER2_CC1_PB5 SILABS_DBUS_TIMER2_CC1(0x1, 0x5)
3893 0 : #define TIMER2_CC1_PB6 SILABS_DBUS_TIMER2_CC1(0x1, 0x6)
3894 0 : #define TIMER2_CC1_PB7 SILABS_DBUS_TIMER2_CC1(0x1, 0x7)
3895 0 : #define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
3896 0 : #define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
3897 0 : #define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
3898 0 : #define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
3899 0 : #define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
3900 0 : #define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
3901 0 : #define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
3902 0 : #define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
3903 0 : #define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
3904 0 : #define TIMER2_CC2_PA9 SILABS_DBUS_TIMER2_CC2(0x0, 0x9)
3905 0 : #define TIMER2_CC2_PA10 SILABS_DBUS_TIMER2_CC2(0x0, 0xa)
3906 0 : #define TIMER2_CC2_PA11 SILABS_DBUS_TIMER2_CC2(0x0, 0xb)
3907 0 : #define TIMER2_CC2_PA12 SILABS_DBUS_TIMER2_CC2(0x0, 0xc)
3908 0 : #define TIMER2_CC2_PA13 SILABS_DBUS_TIMER2_CC2(0x0, 0xd)
3909 0 : #define TIMER2_CC2_PA14 SILABS_DBUS_TIMER2_CC2(0x0, 0xe)
3910 0 : #define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
3911 0 : #define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
3912 0 : #define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
3913 0 : #define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
3914 0 : #define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
3915 0 : #define TIMER2_CC2_PB5 SILABS_DBUS_TIMER2_CC2(0x1, 0x5)
3916 0 : #define TIMER2_CC2_PB6 SILABS_DBUS_TIMER2_CC2(0x1, 0x6)
3917 0 : #define TIMER2_CC2_PB7 SILABS_DBUS_TIMER2_CC2(0x1, 0x7)
3918 0 : #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
3919 0 : #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
3920 0 : #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
3921 0 : #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
3922 0 : #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
3923 0 : #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
3924 0 : #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
3925 0 : #define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
3926 0 : #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
3927 0 : #define TIMER2_CDTI0_PA9 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x9)
3928 0 : #define TIMER2_CDTI0_PA10 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xa)
3929 0 : #define TIMER2_CDTI0_PA11 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xb)
3930 0 : #define TIMER2_CDTI0_PA12 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xc)
3931 0 : #define TIMER2_CDTI0_PA13 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xd)
3932 0 : #define TIMER2_CDTI0_PA14 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xe)
3933 0 : #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
3934 0 : #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
3935 0 : #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
3936 0 : #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
3937 0 : #define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
3938 0 : #define TIMER2_CDTI0_PB5 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x5)
3939 0 : #define TIMER2_CDTI0_PB6 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x6)
3940 0 : #define TIMER2_CDTI0_PB7 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x7)
3941 0 : #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
3942 0 : #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
3943 0 : #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
3944 0 : #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
3945 0 : #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
3946 0 : #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
3947 0 : #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
3948 0 : #define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
3949 0 : #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
3950 0 : #define TIMER2_CDTI1_PA9 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x9)
3951 0 : #define TIMER2_CDTI1_PA10 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xa)
3952 0 : #define TIMER2_CDTI1_PA11 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xb)
3953 0 : #define TIMER2_CDTI1_PA12 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xc)
3954 0 : #define TIMER2_CDTI1_PA13 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xd)
3955 0 : #define TIMER2_CDTI1_PA14 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xe)
3956 0 : #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
3957 0 : #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
3958 0 : #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
3959 0 : #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
3960 0 : #define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
3961 0 : #define TIMER2_CDTI1_PB5 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x5)
3962 0 : #define TIMER2_CDTI1_PB6 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x6)
3963 0 : #define TIMER2_CDTI1_PB7 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x7)
3964 0 : #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
3965 0 : #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
3966 0 : #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
3967 0 : #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
3968 0 : #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
3969 0 : #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
3970 0 : #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
3971 0 : #define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
3972 0 : #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
3973 0 : #define TIMER2_CDTI2_PA9 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x9)
3974 0 : #define TIMER2_CDTI2_PA10 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xa)
3975 0 : #define TIMER2_CDTI2_PA11 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xb)
3976 0 : #define TIMER2_CDTI2_PA12 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xc)
3977 0 : #define TIMER2_CDTI2_PA13 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xd)
3978 0 : #define TIMER2_CDTI2_PA14 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xe)
3979 0 : #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
3980 0 : #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
3981 0 : #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
3982 0 : #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
3983 0 : #define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
3984 0 : #define TIMER2_CDTI2_PB5 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x5)
3985 0 : #define TIMER2_CDTI2_PB6 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x6)
3986 0 : #define TIMER2_CDTI2_PB7 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x7)
3987 :
3988 0 : #define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
3989 0 : #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
3990 0 : #define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
3991 0 : #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
3992 0 : #define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
3993 0 : #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
3994 0 : #define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
3995 0 : #define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
3996 0 : #define TIMER3_CC0_PC8 SILABS_DBUS_TIMER3_CC0(0x2, 0x8)
3997 0 : #define TIMER3_CC0_PC9 SILABS_DBUS_TIMER3_CC0(0x2, 0x9)
3998 0 : #define TIMER3_CC0_PC10 SILABS_DBUS_TIMER3_CC0(0x2, 0xa)
3999 0 : #define TIMER3_CC0_PC11 SILABS_DBUS_TIMER3_CC0(0x2, 0xb)
4000 0 : #define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
4001 0 : #define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
4002 0 : #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
4003 0 : #define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
4004 0 : #define TIMER3_CC0_PD4 SILABS_DBUS_TIMER3_CC0(0x3, 0x4)
4005 0 : #define TIMER3_CC0_PD5 SILABS_DBUS_TIMER3_CC0(0x3, 0x5)
4006 0 : #define TIMER3_CC0_PD6 SILABS_DBUS_TIMER3_CC0(0x3, 0x6)
4007 0 : #define TIMER3_CC0_PD7 SILABS_DBUS_TIMER3_CC0(0x3, 0x7)
4008 0 : #define TIMER3_CC0_PD8 SILABS_DBUS_TIMER3_CC0(0x3, 0x8)
4009 0 : #define TIMER3_CC0_PD9 SILABS_DBUS_TIMER3_CC0(0x3, 0x9)
4010 0 : #define TIMER3_CC0_PD10 SILABS_DBUS_TIMER3_CC0(0x3, 0xa)
4011 0 : #define TIMER3_CC0_PD11 SILABS_DBUS_TIMER3_CC0(0x3, 0xb)
4012 0 : #define TIMER3_CC0_PD12 SILABS_DBUS_TIMER3_CC0(0x3, 0xc)
4013 0 : #define TIMER3_CC0_PD13 SILABS_DBUS_TIMER3_CC0(0x3, 0xd)
4014 0 : #define TIMER3_CC0_PD14 SILABS_DBUS_TIMER3_CC0(0x3, 0xe)
4015 0 : #define TIMER3_CC0_PD15 SILABS_DBUS_TIMER3_CC0(0x3, 0xf)
4016 0 : #define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
4017 0 : #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
4018 0 : #define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
4019 0 : #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
4020 0 : #define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
4021 0 : #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
4022 0 : #define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
4023 0 : #define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
4024 0 : #define TIMER3_CC1_PC8 SILABS_DBUS_TIMER3_CC1(0x2, 0x8)
4025 0 : #define TIMER3_CC1_PC9 SILABS_DBUS_TIMER3_CC1(0x2, 0x9)
4026 0 : #define TIMER3_CC1_PC10 SILABS_DBUS_TIMER3_CC1(0x2, 0xa)
4027 0 : #define TIMER3_CC1_PC11 SILABS_DBUS_TIMER3_CC1(0x2, 0xb)
4028 0 : #define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
4029 0 : #define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
4030 0 : #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
4031 0 : #define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
4032 0 : #define TIMER3_CC1_PD4 SILABS_DBUS_TIMER3_CC1(0x3, 0x4)
4033 0 : #define TIMER3_CC1_PD5 SILABS_DBUS_TIMER3_CC1(0x3, 0x5)
4034 0 : #define TIMER3_CC1_PD6 SILABS_DBUS_TIMER3_CC1(0x3, 0x6)
4035 0 : #define TIMER3_CC1_PD7 SILABS_DBUS_TIMER3_CC1(0x3, 0x7)
4036 0 : #define TIMER3_CC1_PD8 SILABS_DBUS_TIMER3_CC1(0x3, 0x8)
4037 0 : #define TIMER3_CC1_PD9 SILABS_DBUS_TIMER3_CC1(0x3, 0x9)
4038 0 : #define TIMER3_CC1_PD10 SILABS_DBUS_TIMER3_CC1(0x3, 0xa)
4039 0 : #define TIMER3_CC1_PD11 SILABS_DBUS_TIMER3_CC1(0x3, 0xb)
4040 0 : #define TIMER3_CC1_PD12 SILABS_DBUS_TIMER3_CC1(0x3, 0xc)
4041 0 : #define TIMER3_CC1_PD13 SILABS_DBUS_TIMER3_CC1(0x3, 0xd)
4042 0 : #define TIMER3_CC1_PD14 SILABS_DBUS_TIMER3_CC1(0x3, 0xe)
4043 0 : #define TIMER3_CC1_PD15 SILABS_DBUS_TIMER3_CC1(0x3, 0xf)
4044 0 : #define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
4045 0 : #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
4046 0 : #define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
4047 0 : #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
4048 0 : #define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
4049 0 : #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
4050 0 : #define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
4051 0 : #define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
4052 0 : #define TIMER3_CC2_PC8 SILABS_DBUS_TIMER3_CC2(0x2, 0x8)
4053 0 : #define TIMER3_CC2_PC9 SILABS_DBUS_TIMER3_CC2(0x2, 0x9)
4054 0 : #define TIMER3_CC2_PC10 SILABS_DBUS_TIMER3_CC2(0x2, 0xa)
4055 0 : #define TIMER3_CC2_PC11 SILABS_DBUS_TIMER3_CC2(0x2, 0xb)
4056 0 : #define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
4057 0 : #define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
4058 0 : #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
4059 0 : #define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
4060 0 : #define TIMER3_CC2_PD4 SILABS_DBUS_TIMER3_CC2(0x3, 0x4)
4061 0 : #define TIMER3_CC2_PD5 SILABS_DBUS_TIMER3_CC2(0x3, 0x5)
4062 0 : #define TIMER3_CC2_PD6 SILABS_DBUS_TIMER3_CC2(0x3, 0x6)
4063 0 : #define TIMER3_CC2_PD7 SILABS_DBUS_TIMER3_CC2(0x3, 0x7)
4064 0 : #define TIMER3_CC2_PD8 SILABS_DBUS_TIMER3_CC2(0x3, 0x8)
4065 0 : #define TIMER3_CC2_PD9 SILABS_DBUS_TIMER3_CC2(0x3, 0x9)
4066 0 : #define TIMER3_CC2_PD10 SILABS_DBUS_TIMER3_CC2(0x3, 0xa)
4067 0 : #define TIMER3_CC2_PD11 SILABS_DBUS_TIMER3_CC2(0x3, 0xb)
4068 0 : #define TIMER3_CC2_PD12 SILABS_DBUS_TIMER3_CC2(0x3, 0xc)
4069 0 : #define TIMER3_CC2_PD13 SILABS_DBUS_TIMER3_CC2(0x3, 0xd)
4070 0 : #define TIMER3_CC2_PD14 SILABS_DBUS_TIMER3_CC2(0x3, 0xe)
4071 0 : #define TIMER3_CC2_PD15 SILABS_DBUS_TIMER3_CC2(0x3, 0xf)
4072 0 : #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
4073 0 : #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
4074 0 : #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
4075 0 : #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
4076 0 : #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
4077 0 : #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
4078 0 : #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
4079 0 : #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
4080 0 : #define TIMER3_CDTI0_PC8 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x8)
4081 0 : #define TIMER3_CDTI0_PC9 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x9)
4082 0 : #define TIMER3_CDTI0_PC10 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xa)
4083 0 : #define TIMER3_CDTI0_PC11 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xb)
4084 0 : #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
4085 0 : #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
4086 0 : #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
4087 0 : #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
4088 0 : #define TIMER3_CDTI0_PD4 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x4)
4089 0 : #define TIMER3_CDTI0_PD5 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x5)
4090 0 : #define TIMER3_CDTI0_PD6 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x6)
4091 0 : #define TIMER3_CDTI0_PD7 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x7)
4092 0 : #define TIMER3_CDTI0_PD8 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x8)
4093 0 : #define TIMER3_CDTI0_PD9 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x9)
4094 0 : #define TIMER3_CDTI0_PD10 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xa)
4095 0 : #define TIMER3_CDTI0_PD11 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xb)
4096 0 : #define TIMER3_CDTI0_PD12 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xc)
4097 0 : #define TIMER3_CDTI0_PD13 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xd)
4098 0 : #define TIMER3_CDTI0_PD14 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xe)
4099 0 : #define TIMER3_CDTI0_PD15 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xf)
4100 0 : #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
4101 0 : #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
4102 0 : #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
4103 0 : #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
4104 0 : #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
4105 0 : #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
4106 0 : #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
4107 0 : #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
4108 0 : #define TIMER3_CDTI1_PC8 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x8)
4109 0 : #define TIMER3_CDTI1_PC9 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x9)
4110 0 : #define TIMER3_CDTI1_PC10 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xa)
4111 0 : #define TIMER3_CDTI1_PC11 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xb)
4112 0 : #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
4113 0 : #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
4114 0 : #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
4115 0 : #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
4116 0 : #define TIMER3_CDTI1_PD4 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x4)
4117 0 : #define TIMER3_CDTI1_PD5 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x5)
4118 0 : #define TIMER3_CDTI1_PD6 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x6)
4119 0 : #define TIMER3_CDTI1_PD7 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x7)
4120 0 : #define TIMER3_CDTI1_PD8 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x8)
4121 0 : #define TIMER3_CDTI1_PD9 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x9)
4122 0 : #define TIMER3_CDTI1_PD10 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xa)
4123 0 : #define TIMER3_CDTI1_PD11 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xb)
4124 0 : #define TIMER3_CDTI1_PD12 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xc)
4125 0 : #define TIMER3_CDTI1_PD13 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xd)
4126 0 : #define TIMER3_CDTI1_PD14 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xe)
4127 0 : #define TIMER3_CDTI1_PD15 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xf)
4128 0 : #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
4129 0 : #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
4130 0 : #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
4131 0 : #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
4132 0 : #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
4133 0 : #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
4134 0 : #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
4135 0 : #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
4136 0 : #define TIMER3_CDTI2_PC8 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x8)
4137 0 : #define TIMER3_CDTI2_PC9 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x9)
4138 0 : #define TIMER3_CDTI2_PC10 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xa)
4139 0 : #define TIMER3_CDTI2_PC11 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xb)
4140 0 : #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
4141 0 : #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
4142 0 : #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
4143 0 : #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
4144 0 : #define TIMER3_CDTI2_PD4 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x4)
4145 0 : #define TIMER3_CDTI2_PD5 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x5)
4146 0 : #define TIMER3_CDTI2_PD6 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x6)
4147 0 : #define TIMER3_CDTI2_PD7 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x7)
4148 0 : #define TIMER3_CDTI2_PD8 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x8)
4149 0 : #define TIMER3_CDTI2_PD9 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x9)
4150 0 : #define TIMER3_CDTI2_PD10 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xa)
4151 0 : #define TIMER3_CDTI2_PD11 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xb)
4152 0 : #define TIMER3_CDTI2_PD12 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xc)
4153 0 : #define TIMER3_CDTI2_PD13 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xd)
4154 0 : #define TIMER3_CDTI2_PD14 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xe)
4155 0 : #define TIMER3_CDTI2_PD15 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xf)
4156 :
4157 0 : #define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
4158 0 : #define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
4159 0 : #define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
4160 0 : #define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
4161 0 : #define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
4162 0 : #define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
4163 0 : #define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
4164 0 : #define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
4165 0 : #define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
4166 0 : #define TIMER4_CC0_PA9 SILABS_DBUS_TIMER4_CC0(0x0, 0x9)
4167 0 : #define TIMER4_CC0_PA10 SILABS_DBUS_TIMER4_CC0(0x0, 0xa)
4168 0 : #define TIMER4_CC0_PA11 SILABS_DBUS_TIMER4_CC0(0x0, 0xb)
4169 0 : #define TIMER4_CC0_PA12 SILABS_DBUS_TIMER4_CC0(0x0, 0xc)
4170 0 : #define TIMER4_CC0_PA13 SILABS_DBUS_TIMER4_CC0(0x0, 0xd)
4171 0 : #define TIMER4_CC0_PA14 SILABS_DBUS_TIMER4_CC0(0x0, 0xe)
4172 0 : #define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
4173 0 : #define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
4174 0 : #define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
4175 0 : #define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
4176 0 : #define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
4177 0 : #define TIMER4_CC0_PB5 SILABS_DBUS_TIMER4_CC0(0x1, 0x5)
4178 0 : #define TIMER4_CC0_PB6 SILABS_DBUS_TIMER4_CC0(0x1, 0x6)
4179 0 : #define TIMER4_CC0_PB7 SILABS_DBUS_TIMER4_CC0(0x1, 0x7)
4180 0 : #define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
4181 0 : #define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
4182 0 : #define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
4183 0 : #define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
4184 0 : #define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
4185 0 : #define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
4186 0 : #define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
4187 0 : #define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
4188 0 : #define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
4189 0 : #define TIMER4_CC1_PA9 SILABS_DBUS_TIMER4_CC1(0x0, 0x9)
4190 0 : #define TIMER4_CC1_PA10 SILABS_DBUS_TIMER4_CC1(0x0, 0xa)
4191 0 : #define TIMER4_CC1_PA11 SILABS_DBUS_TIMER4_CC1(0x0, 0xb)
4192 0 : #define TIMER4_CC1_PA12 SILABS_DBUS_TIMER4_CC1(0x0, 0xc)
4193 0 : #define TIMER4_CC1_PA13 SILABS_DBUS_TIMER4_CC1(0x0, 0xd)
4194 0 : #define TIMER4_CC1_PA14 SILABS_DBUS_TIMER4_CC1(0x0, 0xe)
4195 0 : #define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
4196 0 : #define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
4197 0 : #define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
4198 0 : #define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
4199 0 : #define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
4200 0 : #define TIMER4_CC1_PB5 SILABS_DBUS_TIMER4_CC1(0x1, 0x5)
4201 0 : #define TIMER4_CC1_PB6 SILABS_DBUS_TIMER4_CC1(0x1, 0x6)
4202 0 : #define TIMER4_CC1_PB7 SILABS_DBUS_TIMER4_CC1(0x1, 0x7)
4203 0 : #define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
4204 0 : #define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
4205 0 : #define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
4206 0 : #define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
4207 0 : #define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
4208 0 : #define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
4209 0 : #define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
4210 0 : #define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
4211 0 : #define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
4212 0 : #define TIMER4_CC2_PA9 SILABS_DBUS_TIMER4_CC2(0x0, 0x9)
4213 0 : #define TIMER4_CC2_PA10 SILABS_DBUS_TIMER4_CC2(0x0, 0xa)
4214 0 : #define TIMER4_CC2_PA11 SILABS_DBUS_TIMER4_CC2(0x0, 0xb)
4215 0 : #define TIMER4_CC2_PA12 SILABS_DBUS_TIMER4_CC2(0x0, 0xc)
4216 0 : #define TIMER4_CC2_PA13 SILABS_DBUS_TIMER4_CC2(0x0, 0xd)
4217 0 : #define TIMER4_CC2_PA14 SILABS_DBUS_TIMER4_CC2(0x0, 0xe)
4218 0 : #define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
4219 0 : #define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
4220 0 : #define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
4221 0 : #define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
4222 0 : #define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
4223 0 : #define TIMER4_CC2_PB5 SILABS_DBUS_TIMER4_CC2(0x1, 0x5)
4224 0 : #define TIMER4_CC2_PB6 SILABS_DBUS_TIMER4_CC2(0x1, 0x6)
4225 0 : #define TIMER4_CC2_PB7 SILABS_DBUS_TIMER4_CC2(0x1, 0x7)
4226 0 : #define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
4227 0 : #define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
4228 0 : #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
4229 0 : #define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
4230 0 : #define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
4231 0 : #define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
4232 0 : #define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
4233 0 : #define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
4234 0 : #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
4235 0 : #define TIMER4_CDTI0_PA9 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x9)
4236 0 : #define TIMER4_CDTI0_PA10 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xa)
4237 0 : #define TIMER4_CDTI0_PA11 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xb)
4238 0 : #define TIMER4_CDTI0_PA12 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xc)
4239 0 : #define TIMER4_CDTI0_PA13 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xd)
4240 0 : #define TIMER4_CDTI0_PA14 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xe)
4241 0 : #define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
4242 0 : #define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
4243 0 : #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
4244 0 : #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
4245 0 : #define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
4246 0 : #define TIMER4_CDTI0_PB5 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x5)
4247 0 : #define TIMER4_CDTI0_PB6 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x6)
4248 0 : #define TIMER4_CDTI0_PB7 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x7)
4249 0 : #define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
4250 0 : #define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
4251 0 : #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
4252 0 : #define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
4253 0 : #define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
4254 0 : #define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
4255 0 : #define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
4256 0 : #define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
4257 0 : #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
4258 0 : #define TIMER4_CDTI1_PA9 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x9)
4259 0 : #define TIMER4_CDTI1_PA10 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xa)
4260 0 : #define TIMER4_CDTI1_PA11 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xb)
4261 0 : #define TIMER4_CDTI1_PA12 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xc)
4262 0 : #define TIMER4_CDTI1_PA13 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xd)
4263 0 : #define TIMER4_CDTI1_PA14 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xe)
4264 0 : #define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
4265 0 : #define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
4266 0 : #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
4267 0 : #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
4268 0 : #define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
4269 0 : #define TIMER4_CDTI1_PB5 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x5)
4270 0 : #define TIMER4_CDTI1_PB6 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x6)
4271 0 : #define TIMER4_CDTI1_PB7 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x7)
4272 0 : #define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
4273 0 : #define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
4274 0 : #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
4275 0 : #define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
4276 0 : #define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
4277 0 : #define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
4278 0 : #define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
4279 0 : #define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
4280 0 : #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
4281 0 : #define TIMER4_CDTI2_PA9 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x9)
4282 0 : #define TIMER4_CDTI2_PA10 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xa)
4283 0 : #define TIMER4_CDTI2_PA11 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xb)
4284 0 : #define TIMER4_CDTI2_PA12 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xc)
4285 0 : #define TIMER4_CDTI2_PA13 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xd)
4286 0 : #define TIMER4_CDTI2_PA14 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xe)
4287 0 : #define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
4288 0 : #define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
4289 0 : #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
4290 0 : #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
4291 0 : #define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
4292 0 : #define TIMER4_CDTI2_PB5 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x5)
4293 0 : #define TIMER4_CDTI2_PB6 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x6)
4294 0 : #define TIMER4_CDTI2_PB7 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x7)
4295 :
4296 0 : #define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0)
4297 0 : #define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1)
4298 0 : #define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2)
4299 0 : #define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3)
4300 0 : #define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4)
4301 0 : #define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5)
4302 0 : #define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6)
4303 0 : #define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7)
4304 0 : #define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8)
4305 0 : #define USART0_CS_PA9 SILABS_DBUS_USART0_CS(0x0, 0x9)
4306 0 : #define USART0_CS_PA10 SILABS_DBUS_USART0_CS(0x0, 0xa)
4307 0 : #define USART0_CS_PA11 SILABS_DBUS_USART0_CS(0x0, 0xb)
4308 0 : #define USART0_CS_PA12 SILABS_DBUS_USART0_CS(0x0, 0xc)
4309 0 : #define USART0_CS_PA13 SILABS_DBUS_USART0_CS(0x0, 0xd)
4310 0 : #define USART0_CS_PA14 SILABS_DBUS_USART0_CS(0x0, 0xe)
4311 0 : #define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0)
4312 0 : #define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1)
4313 0 : #define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2)
4314 0 : #define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3)
4315 0 : #define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4)
4316 0 : #define USART0_CS_PB5 SILABS_DBUS_USART0_CS(0x1, 0x5)
4317 0 : #define USART0_CS_PB6 SILABS_DBUS_USART0_CS(0x1, 0x6)
4318 0 : #define USART0_CS_PB7 SILABS_DBUS_USART0_CS(0x1, 0x7)
4319 0 : #define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0)
4320 0 : #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
4321 0 : #define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2)
4322 0 : #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
4323 0 : #define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4)
4324 0 : #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
4325 0 : #define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6)
4326 0 : #define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7)
4327 0 : #define USART0_CS_PC8 SILABS_DBUS_USART0_CS(0x2, 0x8)
4328 0 : #define USART0_CS_PC9 SILABS_DBUS_USART0_CS(0x2, 0x9)
4329 0 : #define USART0_CS_PC10 SILABS_DBUS_USART0_CS(0x2, 0xa)
4330 0 : #define USART0_CS_PC11 SILABS_DBUS_USART0_CS(0x2, 0xb)
4331 0 : #define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0)
4332 0 : #define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1)
4333 0 : #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
4334 0 : #define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3)
4335 0 : #define USART0_CS_PD4 SILABS_DBUS_USART0_CS(0x3, 0x4)
4336 0 : #define USART0_CS_PD5 SILABS_DBUS_USART0_CS(0x3, 0x5)
4337 0 : #define USART0_CS_PD6 SILABS_DBUS_USART0_CS(0x3, 0x6)
4338 0 : #define USART0_CS_PD7 SILABS_DBUS_USART0_CS(0x3, 0x7)
4339 0 : #define USART0_CS_PD8 SILABS_DBUS_USART0_CS(0x3, 0x8)
4340 0 : #define USART0_CS_PD9 SILABS_DBUS_USART0_CS(0x3, 0x9)
4341 0 : #define USART0_CS_PD10 SILABS_DBUS_USART0_CS(0x3, 0xa)
4342 0 : #define USART0_CS_PD11 SILABS_DBUS_USART0_CS(0x3, 0xb)
4343 0 : #define USART0_CS_PD12 SILABS_DBUS_USART0_CS(0x3, 0xc)
4344 0 : #define USART0_CS_PD13 SILABS_DBUS_USART0_CS(0x3, 0xd)
4345 0 : #define USART0_CS_PD14 SILABS_DBUS_USART0_CS(0x3, 0xe)
4346 0 : #define USART0_CS_PD15 SILABS_DBUS_USART0_CS(0x3, 0xf)
4347 0 : #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
4348 0 : #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
4349 0 : #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
4350 0 : #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
4351 0 : #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
4352 0 : #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
4353 0 : #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
4354 0 : #define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
4355 0 : #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
4356 0 : #define USART0_RTS_PA9 SILABS_DBUS_USART0_RTS(0x0, 0x9)
4357 0 : #define USART0_RTS_PA10 SILABS_DBUS_USART0_RTS(0x0, 0xa)
4358 0 : #define USART0_RTS_PA11 SILABS_DBUS_USART0_RTS(0x0, 0xb)
4359 0 : #define USART0_RTS_PA12 SILABS_DBUS_USART0_RTS(0x0, 0xc)
4360 0 : #define USART0_RTS_PA13 SILABS_DBUS_USART0_RTS(0x0, 0xd)
4361 0 : #define USART0_RTS_PA14 SILABS_DBUS_USART0_RTS(0x0, 0xe)
4362 0 : #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
4363 0 : #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
4364 0 : #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
4365 0 : #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
4366 0 : #define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
4367 0 : #define USART0_RTS_PB5 SILABS_DBUS_USART0_RTS(0x1, 0x5)
4368 0 : #define USART0_RTS_PB6 SILABS_DBUS_USART0_RTS(0x1, 0x6)
4369 0 : #define USART0_RTS_PB7 SILABS_DBUS_USART0_RTS(0x1, 0x7)
4370 0 : #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
4371 0 : #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
4372 0 : #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
4373 0 : #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
4374 0 : #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
4375 0 : #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
4376 0 : #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
4377 0 : #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
4378 0 : #define USART0_RTS_PC8 SILABS_DBUS_USART0_RTS(0x2, 0x8)
4379 0 : #define USART0_RTS_PC9 SILABS_DBUS_USART0_RTS(0x2, 0x9)
4380 0 : #define USART0_RTS_PC10 SILABS_DBUS_USART0_RTS(0x2, 0xa)
4381 0 : #define USART0_RTS_PC11 SILABS_DBUS_USART0_RTS(0x2, 0xb)
4382 0 : #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
4383 0 : #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
4384 0 : #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
4385 0 : #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
4386 0 : #define USART0_RTS_PD4 SILABS_DBUS_USART0_RTS(0x3, 0x4)
4387 0 : #define USART0_RTS_PD5 SILABS_DBUS_USART0_RTS(0x3, 0x5)
4388 0 : #define USART0_RTS_PD6 SILABS_DBUS_USART0_RTS(0x3, 0x6)
4389 0 : #define USART0_RTS_PD7 SILABS_DBUS_USART0_RTS(0x3, 0x7)
4390 0 : #define USART0_RTS_PD8 SILABS_DBUS_USART0_RTS(0x3, 0x8)
4391 0 : #define USART0_RTS_PD9 SILABS_DBUS_USART0_RTS(0x3, 0x9)
4392 0 : #define USART0_RTS_PD10 SILABS_DBUS_USART0_RTS(0x3, 0xa)
4393 0 : #define USART0_RTS_PD11 SILABS_DBUS_USART0_RTS(0x3, 0xb)
4394 0 : #define USART0_RTS_PD12 SILABS_DBUS_USART0_RTS(0x3, 0xc)
4395 0 : #define USART0_RTS_PD13 SILABS_DBUS_USART0_RTS(0x3, 0xd)
4396 0 : #define USART0_RTS_PD14 SILABS_DBUS_USART0_RTS(0x3, 0xe)
4397 0 : #define USART0_RTS_PD15 SILABS_DBUS_USART0_RTS(0x3, 0xf)
4398 0 : #define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0)
4399 0 : #define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1)
4400 0 : #define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2)
4401 0 : #define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3)
4402 0 : #define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4)
4403 0 : #define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5)
4404 0 : #define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6)
4405 0 : #define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7)
4406 0 : #define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8)
4407 0 : #define USART0_RX_PA9 SILABS_DBUS_USART0_RX(0x0, 0x9)
4408 0 : #define USART0_RX_PA10 SILABS_DBUS_USART0_RX(0x0, 0xa)
4409 0 : #define USART0_RX_PA11 SILABS_DBUS_USART0_RX(0x0, 0xb)
4410 0 : #define USART0_RX_PA12 SILABS_DBUS_USART0_RX(0x0, 0xc)
4411 0 : #define USART0_RX_PA13 SILABS_DBUS_USART0_RX(0x0, 0xd)
4412 0 : #define USART0_RX_PA14 SILABS_DBUS_USART0_RX(0x0, 0xe)
4413 0 : #define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0)
4414 0 : #define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1)
4415 0 : #define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2)
4416 0 : #define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3)
4417 0 : #define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4)
4418 0 : #define USART0_RX_PB5 SILABS_DBUS_USART0_RX(0x1, 0x5)
4419 0 : #define USART0_RX_PB6 SILABS_DBUS_USART0_RX(0x1, 0x6)
4420 0 : #define USART0_RX_PB7 SILABS_DBUS_USART0_RX(0x1, 0x7)
4421 0 : #define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0)
4422 0 : #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
4423 0 : #define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2)
4424 0 : #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
4425 0 : #define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4)
4426 0 : #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
4427 0 : #define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6)
4428 0 : #define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7)
4429 0 : #define USART0_RX_PC8 SILABS_DBUS_USART0_RX(0x2, 0x8)
4430 0 : #define USART0_RX_PC9 SILABS_DBUS_USART0_RX(0x2, 0x9)
4431 0 : #define USART0_RX_PC10 SILABS_DBUS_USART0_RX(0x2, 0xa)
4432 0 : #define USART0_RX_PC11 SILABS_DBUS_USART0_RX(0x2, 0xb)
4433 0 : #define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0)
4434 0 : #define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1)
4435 0 : #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
4436 0 : #define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3)
4437 0 : #define USART0_RX_PD4 SILABS_DBUS_USART0_RX(0x3, 0x4)
4438 0 : #define USART0_RX_PD5 SILABS_DBUS_USART0_RX(0x3, 0x5)
4439 0 : #define USART0_RX_PD6 SILABS_DBUS_USART0_RX(0x3, 0x6)
4440 0 : #define USART0_RX_PD7 SILABS_DBUS_USART0_RX(0x3, 0x7)
4441 0 : #define USART0_RX_PD8 SILABS_DBUS_USART0_RX(0x3, 0x8)
4442 0 : #define USART0_RX_PD9 SILABS_DBUS_USART0_RX(0x3, 0x9)
4443 0 : #define USART0_RX_PD10 SILABS_DBUS_USART0_RX(0x3, 0xa)
4444 0 : #define USART0_RX_PD11 SILABS_DBUS_USART0_RX(0x3, 0xb)
4445 0 : #define USART0_RX_PD12 SILABS_DBUS_USART0_RX(0x3, 0xc)
4446 0 : #define USART0_RX_PD13 SILABS_DBUS_USART0_RX(0x3, 0xd)
4447 0 : #define USART0_RX_PD14 SILABS_DBUS_USART0_RX(0x3, 0xe)
4448 0 : #define USART0_RX_PD15 SILABS_DBUS_USART0_RX(0x3, 0xf)
4449 0 : #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
4450 0 : #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
4451 0 : #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
4452 0 : #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
4453 0 : #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
4454 0 : #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
4455 0 : #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
4456 0 : #define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
4457 0 : #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
4458 0 : #define USART0_CLK_PA9 SILABS_DBUS_USART0_CLK(0x0, 0x9)
4459 0 : #define USART0_CLK_PA10 SILABS_DBUS_USART0_CLK(0x0, 0xa)
4460 0 : #define USART0_CLK_PA11 SILABS_DBUS_USART0_CLK(0x0, 0xb)
4461 0 : #define USART0_CLK_PA12 SILABS_DBUS_USART0_CLK(0x0, 0xc)
4462 0 : #define USART0_CLK_PA13 SILABS_DBUS_USART0_CLK(0x0, 0xd)
4463 0 : #define USART0_CLK_PA14 SILABS_DBUS_USART0_CLK(0x0, 0xe)
4464 0 : #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
4465 0 : #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
4466 0 : #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
4467 0 : #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
4468 0 : #define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
4469 0 : #define USART0_CLK_PB5 SILABS_DBUS_USART0_CLK(0x1, 0x5)
4470 0 : #define USART0_CLK_PB6 SILABS_DBUS_USART0_CLK(0x1, 0x6)
4471 0 : #define USART0_CLK_PB7 SILABS_DBUS_USART0_CLK(0x1, 0x7)
4472 0 : #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
4473 0 : #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
4474 0 : #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
4475 0 : #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
4476 0 : #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
4477 0 : #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
4478 0 : #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
4479 0 : #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
4480 0 : #define USART0_CLK_PC8 SILABS_DBUS_USART0_CLK(0x2, 0x8)
4481 0 : #define USART0_CLK_PC9 SILABS_DBUS_USART0_CLK(0x2, 0x9)
4482 0 : #define USART0_CLK_PC10 SILABS_DBUS_USART0_CLK(0x2, 0xa)
4483 0 : #define USART0_CLK_PC11 SILABS_DBUS_USART0_CLK(0x2, 0xb)
4484 0 : #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
4485 0 : #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
4486 0 : #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
4487 0 : #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
4488 0 : #define USART0_CLK_PD4 SILABS_DBUS_USART0_CLK(0x3, 0x4)
4489 0 : #define USART0_CLK_PD5 SILABS_DBUS_USART0_CLK(0x3, 0x5)
4490 0 : #define USART0_CLK_PD6 SILABS_DBUS_USART0_CLK(0x3, 0x6)
4491 0 : #define USART0_CLK_PD7 SILABS_DBUS_USART0_CLK(0x3, 0x7)
4492 0 : #define USART0_CLK_PD8 SILABS_DBUS_USART0_CLK(0x3, 0x8)
4493 0 : #define USART0_CLK_PD9 SILABS_DBUS_USART0_CLK(0x3, 0x9)
4494 0 : #define USART0_CLK_PD10 SILABS_DBUS_USART0_CLK(0x3, 0xa)
4495 0 : #define USART0_CLK_PD11 SILABS_DBUS_USART0_CLK(0x3, 0xb)
4496 0 : #define USART0_CLK_PD12 SILABS_DBUS_USART0_CLK(0x3, 0xc)
4497 0 : #define USART0_CLK_PD13 SILABS_DBUS_USART0_CLK(0x3, 0xd)
4498 0 : #define USART0_CLK_PD14 SILABS_DBUS_USART0_CLK(0x3, 0xe)
4499 0 : #define USART0_CLK_PD15 SILABS_DBUS_USART0_CLK(0x3, 0xf)
4500 0 : #define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0)
4501 0 : #define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1)
4502 0 : #define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2)
4503 0 : #define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3)
4504 0 : #define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4)
4505 0 : #define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5)
4506 0 : #define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6)
4507 0 : #define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7)
4508 0 : #define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8)
4509 0 : #define USART0_TX_PA9 SILABS_DBUS_USART0_TX(0x0, 0x9)
4510 0 : #define USART0_TX_PA10 SILABS_DBUS_USART0_TX(0x0, 0xa)
4511 0 : #define USART0_TX_PA11 SILABS_DBUS_USART0_TX(0x0, 0xb)
4512 0 : #define USART0_TX_PA12 SILABS_DBUS_USART0_TX(0x0, 0xc)
4513 0 : #define USART0_TX_PA13 SILABS_DBUS_USART0_TX(0x0, 0xd)
4514 0 : #define USART0_TX_PA14 SILABS_DBUS_USART0_TX(0x0, 0xe)
4515 0 : #define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0)
4516 0 : #define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1)
4517 0 : #define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2)
4518 0 : #define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3)
4519 0 : #define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4)
4520 0 : #define USART0_TX_PB5 SILABS_DBUS_USART0_TX(0x1, 0x5)
4521 0 : #define USART0_TX_PB6 SILABS_DBUS_USART0_TX(0x1, 0x6)
4522 0 : #define USART0_TX_PB7 SILABS_DBUS_USART0_TX(0x1, 0x7)
4523 0 : #define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0)
4524 0 : #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
4525 0 : #define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2)
4526 0 : #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
4527 0 : #define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4)
4528 0 : #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
4529 0 : #define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6)
4530 0 : #define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7)
4531 0 : #define USART0_TX_PC8 SILABS_DBUS_USART0_TX(0x2, 0x8)
4532 0 : #define USART0_TX_PC9 SILABS_DBUS_USART0_TX(0x2, 0x9)
4533 0 : #define USART0_TX_PC10 SILABS_DBUS_USART0_TX(0x2, 0xa)
4534 0 : #define USART0_TX_PC11 SILABS_DBUS_USART0_TX(0x2, 0xb)
4535 0 : #define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0)
4536 0 : #define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1)
4537 0 : #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
4538 0 : #define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3)
4539 0 : #define USART0_TX_PD4 SILABS_DBUS_USART0_TX(0x3, 0x4)
4540 0 : #define USART0_TX_PD5 SILABS_DBUS_USART0_TX(0x3, 0x5)
4541 0 : #define USART0_TX_PD6 SILABS_DBUS_USART0_TX(0x3, 0x6)
4542 0 : #define USART0_TX_PD7 SILABS_DBUS_USART0_TX(0x3, 0x7)
4543 0 : #define USART0_TX_PD8 SILABS_DBUS_USART0_TX(0x3, 0x8)
4544 0 : #define USART0_TX_PD9 SILABS_DBUS_USART0_TX(0x3, 0x9)
4545 0 : #define USART0_TX_PD10 SILABS_DBUS_USART0_TX(0x3, 0xa)
4546 0 : #define USART0_TX_PD11 SILABS_DBUS_USART0_TX(0x3, 0xb)
4547 0 : #define USART0_TX_PD12 SILABS_DBUS_USART0_TX(0x3, 0xc)
4548 0 : #define USART0_TX_PD13 SILABS_DBUS_USART0_TX(0x3, 0xd)
4549 0 : #define USART0_TX_PD14 SILABS_DBUS_USART0_TX(0x3, 0xe)
4550 0 : #define USART0_TX_PD15 SILABS_DBUS_USART0_TX(0x3, 0xf)
4551 0 : #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
4552 0 : #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
4553 0 : #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
4554 0 : #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
4555 0 : #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
4556 0 : #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
4557 0 : #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
4558 0 : #define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
4559 0 : #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
4560 0 : #define USART0_CTS_PA9 SILABS_DBUS_USART0_CTS(0x0, 0x9)
4561 0 : #define USART0_CTS_PA10 SILABS_DBUS_USART0_CTS(0x0, 0xa)
4562 0 : #define USART0_CTS_PA11 SILABS_DBUS_USART0_CTS(0x0, 0xb)
4563 0 : #define USART0_CTS_PA12 SILABS_DBUS_USART0_CTS(0x0, 0xc)
4564 0 : #define USART0_CTS_PA13 SILABS_DBUS_USART0_CTS(0x0, 0xd)
4565 0 : #define USART0_CTS_PA14 SILABS_DBUS_USART0_CTS(0x0, 0xe)
4566 0 : #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
4567 0 : #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
4568 0 : #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
4569 0 : #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
4570 0 : #define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
4571 0 : #define USART0_CTS_PB5 SILABS_DBUS_USART0_CTS(0x1, 0x5)
4572 0 : #define USART0_CTS_PB6 SILABS_DBUS_USART0_CTS(0x1, 0x6)
4573 0 : #define USART0_CTS_PB7 SILABS_DBUS_USART0_CTS(0x1, 0x7)
4574 0 : #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
4575 0 : #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
4576 0 : #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
4577 0 : #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
4578 0 : #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
4579 0 : #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
4580 0 : #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
4581 0 : #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
4582 0 : #define USART0_CTS_PC8 SILABS_DBUS_USART0_CTS(0x2, 0x8)
4583 0 : #define USART0_CTS_PC9 SILABS_DBUS_USART0_CTS(0x2, 0x9)
4584 0 : #define USART0_CTS_PC10 SILABS_DBUS_USART0_CTS(0x2, 0xa)
4585 0 : #define USART0_CTS_PC11 SILABS_DBUS_USART0_CTS(0x2, 0xb)
4586 0 : #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
4587 0 : #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
4588 0 : #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
4589 0 : #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
4590 0 : #define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4)
4591 0 : #define USART0_CTS_PD5 SILABS_DBUS_USART0_CTS(0x3, 0x5)
4592 0 : #define USART0_CTS_PD6 SILABS_DBUS_USART0_CTS(0x3, 0x6)
4593 0 : #define USART0_CTS_PD7 SILABS_DBUS_USART0_CTS(0x3, 0x7)
4594 0 : #define USART0_CTS_PD8 SILABS_DBUS_USART0_CTS(0x3, 0x8)
4595 0 : #define USART0_CTS_PD9 SILABS_DBUS_USART0_CTS(0x3, 0x9)
4596 0 : #define USART0_CTS_PD10 SILABS_DBUS_USART0_CTS(0x3, 0xa)
4597 0 : #define USART0_CTS_PD11 SILABS_DBUS_USART0_CTS(0x3, 0xb)
4598 0 : #define USART0_CTS_PD12 SILABS_DBUS_USART0_CTS(0x3, 0xc)
4599 0 : #define USART0_CTS_PD13 SILABS_DBUS_USART0_CTS(0x3, 0xd)
4600 0 : #define USART0_CTS_PD14 SILABS_DBUS_USART0_CTS(0x3, 0xe)
4601 0 : #define USART0_CTS_PD15 SILABS_DBUS_USART0_CTS(0x3, 0xf)
4602 :
4603 0 : #define ABUS_AEVEN0_IADC0 SILABS_ABUS(0x0, 0x0, 0x1)
4604 0 : #define ABUS_AEVEN0_ACMP0 SILABS_ABUS(0x0, 0x0, 0x2)
4605 0 : #define ABUS_AEVEN0_ACMP1 SILABS_ABUS(0x0, 0x0, 0x3)
4606 0 : #define ABUS_AEVEN0_VDAC0CH0 SILABS_ABUS(0x0, 0x0, 0x4)
4607 0 : #define ABUS_AEVEN1_IADC0 SILABS_ABUS(0x0, 0x1, 0x1)
4608 0 : #define ABUS_AEVEN1_ACMP0 SILABS_ABUS(0x0, 0x1, 0x2)
4609 0 : #define ABUS_AEVEN1_ACMP1 SILABS_ABUS(0x0, 0x1, 0x3)
4610 0 : #define ABUS_AEVEN1_VDAC0CH1 SILABS_ABUS(0x0, 0x1, 0x4)
4611 0 : #define ABUS_AODD0_IADC0 SILABS_ABUS(0x0, 0x2, 0x1)
4612 0 : #define ABUS_AODD0_ACMP0 SILABS_ABUS(0x0, 0x2, 0x2)
4613 0 : #define ABUS_AODD0_ACMP1 SILABS_ABUS(0x0, 0x2, 0x3)
4614 0 : #define ABUS_AODD0_VDAC0CH0 SILABS_ABUS(0x0, 0x2, 0x4)
4615 0 : #define ABUS_AODD1_IADC0 SILABS_ABUS(0x0, 0x3, 0x1)
4616 0 : #define ABUS_AODD1_ACMP0 SILABS_ABUS(0x0, 0x3, 0x2)
4617 0 : #define ABUS_AODD1_ACMP1 SILABS_ABUS(0x0, 0x3, 0x3)
4618 0 : #define ABUS_AODD1_VDAC0CH1 SILABS_ABUS(0x0, 0x3, 0x4)
4619 0 : #define ABUS_BEVEN0_IADC0 SILABS_ABUS(0x1, 0x0, 0x1)
4620 0 : #define ABUS_BEVEN0_ACMP0 SILABS_ABUS(0x1, 0x0, 0x2)
4621 0 : #define ABUS_BEVEN0_ACMP1 SILABS_ABUS(0x1, 0x0, 0x3)
4622 0 : #define ABUS_BEVEN0_VDAC0CH0 SILABS_ABUS(0x1, 0x0, 0x4)
4623 0 : #define ABUS_BEVEN1_IADC0 SILABS_ABUS(0x1, 0x1, 0x1)
4624 0 : #define ABUS_BEVEN1_ACMP0 SILABS_ABUS(0x1, 0x1, 0x2)
4625 0 : #define ABUS_BEVEN1_ACMP1 SILABS_ABUS(0x1, 0x1, 0x3)
4626 0 : #define ABUS_BEVEN1_VDAC0CH1 SILABS_ABUS(0x1, 0x1, 0x4)
4627 0 : #define ABUS_BODD0_IADC0 SILABS_ABUS(0x1, 0x2, 0x1)
4628 0 : #define ABUS_BODD0_ACMP0 SILABS_ABUS(0x1, 0x2, 0x2)
4629 0 : #define ABUS_BODD0_ACMP1 SILABS_ABUS(0x1, 0x2, 0x3)
4630 0 : #define ABUS_BODD0_VDAC0CH0 SILABS_ABUS(0x1, 0x2, 0x4)
4631 0 : #define ABUS_BODD1_IADC0 SILABS_ABUS(0x1, 0x3, 0x1)
4632 0 : #define ABUS_BODD1_ACMP0 SILABS_ABUS(0x1, 0x3, 0x2)
4633 0 : #define ABUS_BODD1_ACMP1 SILABS_ABUS(0x1, 0x3, 0x3)
4634 0 : #define ABUS_BODD1_VDAC0CH1 SILABS_ABUS(0x1, 0x3, 0x4)
4635 0 : #define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1)
4636 0 : #define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2)
4637 0 : #define ABUS_CDEVEN0_ACMP1 SILABS_ABUS(0x2, 0x0, 0x3)
4638 0 : #define ABUS_CDEVEN0_VDAC0CH0 SILABS_ABUS(0x2, 0x0, 0x4)
4639 0 : #define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1)
4640 0 : #define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2)
4641 0 : #define ABUS_CDEVEN1_ACMP1 SILABS_ABUS(0x2, 0x1, 0x3)
4642 0 : #define ABUS_CDEVEN1_VDAC0CH1 SILABS_ABUS(0x2, 0x1, 0x4)
4643 0 : #define ABUS_CDODD0_IADC0 SILABS_ABUS(0x2, 0x2, 0x1)
4644 0 : #define ABUS_CDODD0_ACMP0 SILABS_ABUS(0x2, 0x2, 0x2)
4645 0 : #define ABUS_CDODD0_ACMP1 SILABS_ABUS(0x2, 0x2, 0x3)
4646 0 : #define ABUS_CDODD0_VDAC0CH0 SILABS_ABUS(0x2, 0x2, 0x4)
4647 0 : #define ABUS_CDODD1_IADC0 SILABS_ABUS(0x2, 0x3, 0x1)
4648 0 : #define ABUS_CDODD1_ACMP0 SILABS_ABUS(0x2, 0x3, 0x2)
4649 0 : #define ABUS_CDODD1_ACMP1 SILABS_ABUS(0x2, 0x3, 0x3)
4650 0 : #define ABUS_CDODD1_VDAC0CH1 SILABS_ABUS(0x2, 0x3, 0x4)
4651 :
4652 : #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG28_PINCTRL_H_ */
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