Line data Source code
1 0 : /*
2 : * Copyright (c) 2025 Silicon Laboratories Inc.
3 : * SPDX-License-Identifier: Apache-2.0
4 : *
5 : * Pin Control for Silicon Labs XG29 devices
6 : *
7 : * This file was generated by the script gen_pinctrl.py in the hal_silabs module.
8 : * Do not manually edit.
9 : */
10 :
11 : #ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_
12 : #define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_
13 :
14 : #include <zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
15 :
16 0 : #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
17 :
18 0 : #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
19 0 : #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 7, 1, 1, 3)
20 0 : #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4)
21 0 : #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1)
22 :
23 0 : #define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1)
24 0 : #define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 19, 1, 1, 3)
25 0 : #define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 19, 1, 2, 4)
26 0 : #define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 19, 1, 3, 5)
27 0 : #define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 19, 1, 4, 6)
28 0 : #define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2)
29 :
30 0 : #define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1)
31 0 : #define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 27, 1, 1, 3)
32 0 : #define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 27, 1, 2, 4)
33 0 : #define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 3, 5)
34 0 : #define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 27, 1, 4, 6)
35 0 : #define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 27, 0, 0, 2)
36 :
37 0 : #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 35, 1, 0, 1)
38 0 : #define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 35, 1, 1, 2)
39 0 : #define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 35, 1, 2, 3)
40 :
41 0 : #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1)
42 0 : #define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 40, 1, 1, 2)
43 :
44 0 : #define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1)
45 0 : #define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 44, 1, 1, 2)
46 :
47 0 : #define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 48, 1, 0, 1)
48 0 : #define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 48, 1, 1, 2)
49 :
50 0 : #define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 52, 1, 0, 1)
51 0 : #define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 52, 1, 1, 2)
52 0 : #define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 52, 1, 2, 3)
53 0 : #define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 52, 1, 3, 4)
54 0 : #define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 52, 1, 4, 5)
55 0 : #define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 52, 1, 5, 6)
56 0 : #define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 52, 1, 6, 7)
57 0 : #define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 52, 1, 7, 8)
58 0 : #define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 52, 1, 8, 9)
59 0 : #define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 52, 1, 9, 10)
60 0 : #define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 52, 1, 10, 11)
61 0 : #define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 52, 1, 11, 12)
62 0 : #define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 52, 1, 12, 13)
63 0 : #define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 52, 1, 13, 14)
64 0 : #define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 52, 1, 14, 16)
65 0 : #define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 52, 0, 0, 15)
66 :
67 0 : #define SILABS_DBUS_PDM_CLK(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1)
68 0 : #define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 2)
69 0 : #define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 3)
70 :
71 0 : #define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 75, 1, 0, 1)
72 0 : #define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 75, 1, 1, 2)
73 0 : #define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 75, 1, 2, 3)
74 0 : #define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 75, 1, 3, 4)
75 0 : #define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 75, 1, 4, 5)
76 0 : #define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 75, 1, 5, 6)
77 0 : #define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 75, 1, 6, 7)
78 0 : #define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 75, 1, 7, 8)
79 0 : #define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 75, 1, 8, 9)
80 0 : #define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 75, 1, 9, 10)
81 0 : #define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 75, 1, 10, 11)
82 0 : #define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 75, 1, 11, 12)
83 0 : #define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 75, 1, 12, 13)
84 0 : #define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 75, 1, 13, 14)
85 0 : #define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 75, 1, 14, 15)
86 0 : #define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 75, 1, 15, 16)
87 :
88 0 : #define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 93, 1, 0, 1)
89 0 : #define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 93, 1, 1, 2)
90 0 : #define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 93, 1, 2, 3)
91 0 : #define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 93, 1, 3, 4)
92 0 : #define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 93, 1, 4, 5)
93 0 : #define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 93, 1, 5, 6)
94 :
95 0 : #define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 101, 1, 0, 1)
96 0 : #define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 101, 1, 1, 2)
97 0 : #define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 101, 1, 2, 3)
98 0 : #define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 101, 1, 3, 4)
99 0 : #define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 101, 1, 4, 5)
100 0 : #define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 101, 1, 5, 6)
101 :
102 0 : #define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 109, 1, 0, 1)
103 0 : #define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 109, 1, 1, 2)
104 0 : #define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 109, 1, 2, 3)
105 0 : #define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 109, 1, 3, 4)
106 0 : #define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 109, 1, 4, 5)
107 0 : #define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 109, 1, 5, 6)
108 :
109 0 : #define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 117, 1, 0, 1)
110 0 : #define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 117, 1, 1, 2)
111 0 : #define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 117, 1, 2, 3)
112 0 : #define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 117, 1, 3, 4)
113 0 : #define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 117, 1, 4, 5)
114 0 : #define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 117, 1, 5, 6)
115 :
116 0 : #define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 125, 1, 0, 1)
117 0 : #define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 125, 1, 1, 2)
118 0 : #define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 125, 1, 2, 3)
119 0 : #define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 125, 1, 3, 4)
120 0 : #define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 125, 1, 4, 5)
121 0 : #define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 125, 1, 5, 6)
122 :
123 0 : #define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 133, 1, 0, 1)
124 0 : #define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 133, 1, 1, 3)
125 0 : #define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 133, 1, 2, 4)
126 0 : #define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 133, 1, 3, 5)
127 0 : #define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 133, 1, 4, 6)
128 0 : #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 133, 0, 0, 2)
129 :
130 0 : #define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 141, 1, 0, 1)
131 0 : #define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 141, 1, 1, 3)
132 0 : #define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 141, 1, 2, 4)
133 0 : #define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 141, 1, 3, 5)
134 0 : #define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 141, 1, 4, 6)
135 0 : #define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 141, 0, 0, 2)
136 :
137 0 : #define GPIO_SWCLKTCK_PA1 SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
138 0 : #define GPIO_SWDIOTMS_PA2 SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
139 0 : #define GPIO_TDO_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
140 0 : #define GPIO_TDI_PA4 SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
141 0 : #define GPIO_SWV_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
142 0 : #define GPIO_TRACECLK_PA4 SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
143 0 : #define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
144 0 : #define GPIO_TRACEDATA1_PA5 SILABS_FIXED_ROUTE(0x0, 0x5, 1, 3)
145 0 : #define GPIO_TRACEDATA2_PA6 SILABS_FIXED_ROUTE(0x0, 0x6, 1, 4)
146 0 : #define GPIO_TRACEDATA3_PA7 SILABS_FIXED_ROUTE(0x0, 0x7, 1, 5)
147 :
148 0 : #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
149 0 : #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
150 0 : #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
151 0 : #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
152 0 : #define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4)
153 0 : #define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
154 0 : #define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
155 0 : #define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7)
156 0 : #define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8)
157 0 : #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
158 0 : #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
159 0 : #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
160 0 : #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
161 0 : #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
162 0 : #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
163 0 : #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
164 0 : #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
165 0 : #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
166 0 : #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
167 0 : #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
168 0 : #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
169 0 : #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
170 0 : #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
171 0 : #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
172 0 : #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
173 0 : #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
174 :
175 0 : #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
176 0 : #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
177 0 : #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
178 0 : #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
179 0 : #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
180 0 : #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
181 0 : #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
182 0 : #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
183 0 : #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
184 0 : #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
185 0 : #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
186 0 : #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
187 0 : #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
188 0 : #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
189 0 : #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
190 0 : #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
191 0 : #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
192 0 : #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
193 0 : #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
194 0 : #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
195 0 : #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
196 0 : #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
197 0 : #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
198 0 : #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
199 0 : #define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
200 0 : #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
201 0 : #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
202 0 : #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
203 0 : #define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
204 0 : #define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
205 0 : #define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
206 0 : #define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
207 0 : #define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
208 0 : #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
209 0 : #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
210 0 : #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
211 0 : #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
212 0 : #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
213 0 : #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
214 0 : #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
215 0 : #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
216 0 : #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
217 0 : #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
218 0 : #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
219 0 : #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
220 0 : #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
221 0 : #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
222 0 : #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
223 0 : #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
224 0 : #define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
225 :
226 0 : #define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0)
227 0 : #define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1)
228 0 : #define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2)
229 0 : #define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3)
230 0 : #define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4)
231 0 : #define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5)
232 0 : #define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6)
233 0 : #define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7)
234 0 : #define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8)
235 0 : #define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0)
236 0 : #define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1)
237 0 : #define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2)
238 0 : #define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3)
239 0 : #define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4)
240 0 : #define EUSART0_CS_PC0 SILABS_DBUS_EUSART0_CS(0x2, 0x0)
241 0 : #define EUSART0_CS_PC1 SILABS_DBUS_EUSART0_CS(0x2, 0x1)
242 0 : #define EUSART0_CS_PC2 SILABS_DBUS_EUSART0_CS(0x2, 0x2)
243 0 : #define EUSART0_CS_PC3 SILABS_DBUS_EUSART0_CS(0x2, 0x3)
244 0 : #define EUSART0_CS_PC4 SILABS_DBUS_EUSART0_CS(0x2, 0x4)
245 0 : #define EUSART0_CS_PC5 SILABS_DBUS_EUSART0_CS(0x2, 0x5)
246 0 : #define EUSART0_CS_PC6 SILABS_DBUS_EUSART0_CS(0x2, 0x6)
247 0 : #define EUSART0_CS_PC7 SILABS_DBUS_EUSART0_CS(0x2, 0x7)
248 0 : #define EUSART0_CS_PD0 SILABS_DBUS_EUSART0_CS(0x3, 0x0)
249 0 : #define EUSART0_CS_PD1 SILABS_DBUS_EUSART0_CS(0x3, 0x1)
250 0 : #define EUSART0_CS_PD2 SILABS_DBUS_EUSART0_CS(0x3, 0x2)
251 0 : #define EUSART0_CS_PD3 SILABS_DBUS_EUSART0_CS(0x3, 0x3)
252 0 : #define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0)
253 0 : #define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1)
254 0 : #define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2)
255 0 : #define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3)
256 0 : #define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4)
257 0 : #define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5)
258 0 : #define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6)
259 0 : #define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7)
260 0 : #define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8)
261 0 : #define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0)
262 0 : #define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1)
263 0 : #define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
264 0 : #define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
265 0 : #define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4)
266 0 : #define EUSART0_RTS_PC0 SILABS_DBUS_EUSART0_RTS(0x2, 0x0)
267 0 : #define EUSART0_RTS_PC1 SILABS_DBUS_EUSART0_RTS(0x2, 0x1)
268 0 : #define EUSART0_RTS_PC2 SILABS_DBUS_EUSART0_RTS(0x2, 0x2)
269 0 : #define EUSART0_RTS_PC3 SILABS_DBUS_EUSART0_RTS(0x2, 0x3)
270 0 : #define EUSART0_RTS_PC4 SILABS_DBUS_EUSART0_RTS(0x2, 0x4)
271 0 : #define EUSART0_RTS_PC5 SILABS_DBUS_EUSART0_RTS(0x2, 0x5)
272 0 : #define EUSART0_RTS_PC6 SILABS_DBUS_EUSART0_RTS(0x2, 0x6)
273 0 : #define EUSART0_RTS_PC7 SILABS_DBUS_EUSART0_RTS(0x2, 0x7)
274 0 : #define EUSART0_RTS_PD0 SILABS_DBUS_EUSART0_RTS(0x3, 0x0)
275 0 : #define EUSART0_RTS_PD1 SILABS_DBUS_EUSART0_RTS(0x3, 0x1)
276 0 : #define EUSART0_RTS_PD2 SILABS_DBUS_EUSART0_RTS(0x3, 0x2)
277 0 : #define EUSART0_RTS_PD3 SILABS_DBUS_EUSART0_RTS(0x3, 0x3)
278 0 : #define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0)
279 0 : #define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1)
280 0 : #define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2)
281 0 : #define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3)
282 0 : #define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4)
283 0 : #define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5)
284 0 : #define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6)
285 0 : #define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7)
286 0 : #define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8)
287 0 : #define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0)
288 0 : #define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1)
289 0 : #define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2)
290 0 : #define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3)
291 0 : #define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4)
292 0 : #define EUSART0_RX_PC0 SILABS_DBUS_EUSART0_RX(0x2, 0x0)
293 0 : #define EUSART0_RX_PC1 SILABS_DBUS_EUSART0_RX(0x2, 0x1)
294 0 : #define EUSART0_RX_PC2 SILABS_DBUS_EUSART0_RX(0x2, 0x2)
295 0 : #define EUSART0_RX_PC3 SILABS_DBUS_EUSART0_RX(0x2, 0x3)
296 0 : #define EUSART0_RX_PC4 SILABS_DBUS_EUSART0_RX(0x2, 0x4)
297 0 : #define EUSART0_RX_PC5 SILABS_DBUS_EUSART0_RX(0x2, 0x5)
298 0 : #define EUSART0_RX_PC6 SILABS_DBUS_EUSART0_RX(0x2, 0x6)
299 0 : #define EUSART0_RX_PC7 SILABS_DBUS_EUSART0_RX(0x2, 0x7)
300 0 : #define EUSART0_RX_PD0 SILABS_DBUS_EUSART0_RX(0x3, 0x0)
301 0 : #define EUSART0_RX_PD1 SILABS_DBUS_EUSART0_RX(0x3, 0x1)
302 0 : #define EUSART0_RX_PD2 SILABS_DBUS_EUSART0_RX(0x3, 0x2)
303 0 : #define EUSART0_RX_PD3 SILABS_DBUS_EUSART0_RX(0x3, 0x3)
304 0 : #define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0)
305 0 : #define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1)
306 0 : #define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2)
307 0 : #define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3)
308 0 : #define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4)
309 0 : #define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5)
310 0 : #define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6)
311 0 : #define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7)
312 0 : #define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8)
313 0 : #define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0)
314 0 : #define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1)
315 0 : #define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
316 0 : #define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
317 0 : #define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4)
318 0 : #define EUSART0_SCLK_PC0 SILABS_DBUS_EUSART0_SCLK(0x2, 0x0)
319 0 : #define EUSART0_SCLK_PC1 SILABS_DBUS_EUSART0_SCLK(0x2, 0x1)
320 0 : #define EUSART0_SCLK_PC2 SILABS_DBUS_EUSART0_SCLK(0x2, 0x2)
321 0 : #define EUSART0_SCLK_PC3 SILABS_DBUS_EUSART0_SCLK(0x2, 0x3)
322 0 : #define EUSART0_SCLK_PC4 SILABS_DBUS_EUSART0_SCLK(0x2, 0x4)
323 0 : #define EUSART0_SCLK_PC5 SILABS_DBUS_EUSART0_SCLK(0x2, 0x5)
324 0 : #define EUSART0_SCLK_PC6 SILABS_DBUS_EUSART0_SCLK(0x2, 0x6)
325 0 : #define EUSART0_SCLK_PC7 SILABS_DBUS_EUSART0_SCLK(0x2, 0x7)
326 0 : #define EUSART0_SCLK_PD0 SILABS_DBUS_EUSART0_SCLK(0x3, 0x0)
327 0 : #define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1)
328 0 : #define EUSART0_SCLK_PD2 SILABS_DBUS_EUSART0_SCLK(0x3, 0x2)
329 0 : #define EUSART0_SCLK_PD3 SILABS_DBUS_EUSART0_SCLK(0x3, 0x3)
330 0 : #define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0)
331 0 : #define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1)
332 0 : #define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2)
333 0 : #define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3)
334 0 : #define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4)
335 0 : #define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5)
336 0 : #define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6)
337 0 : #define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7)
338 0 : #define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8)
339 0 : #define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0)
340 0 : #define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1)
341 0 : #define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2)
342 0 : #define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3)
343 0 : #define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4)
344 0 : #define EUSART0_TX_PC0 SILABS_DBUS_EUSART0_TX(0x2, 0x0)
345 0 : #define EUSART0_TX_PC1 SILABS_DBUS_EUSART0_TX(0x2, 0x1)
346 0 : #define EUSART0_TX_PC2 SILABS_DBUS_EUSART0_TX(0x2, 0x2)
347 0 : #define EUSART0_TX_PC3 SILABS_DBUS_EUSART0_TX(0x2, 0x3)
348 0 : #define EUSART0_TX_PC4 SILABS_DBUS_EUSART0_TX(0x2, 0x4)
349 0 : #define EUSART0_TX_PC5 SILABS_DBUS_EUSART0_TX(0x2, 0x5)
350 0 : #define EUSART0_TX_PC6 SILABS_DBUS_EUSART0_TX(0x2, 0x6)
351 0 : #define EUSART0_TX_PC7 SILABS_DBUS_EUSART0_TX(0x2, 0x7)
352 0 : #define EUSART0_TX_PD0 SILABS_DBUS_EUSART0_TX(0x3, 0x0)
353 0 : #define EUSART0_TX_PD1 SILABS_DBUS_EUSART0_TX(0x3, 0x1)
354 0 : #define EUSART0_TX_PD2 SILABS_DBUS_EUSART0_TX(0x3, 0x2)
355 0 : #define EUSART0_TX_PD3 SILABS_DBUS_EUSART0_TX(0x3, 0x3)
356 0 : #define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0)
357 0 : #define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1)
358 0 : #define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2)
359 0 : #define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3)
360 0 : #define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4)
361 0 : #define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5)
362 0 : #define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6)
363 0 : #define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7)
364 0 : #define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8)
365 0 : #define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0)
366 0 : #define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1)
367 0 : #define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
368 0 : #define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
369 0 : #define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4)
370 0 : #define EUSART0_CTS_PC0 SILABS_DBUS_EUSART0_CTS(0x2, 0x0)
371 0 : #define EUSART0_CTS_PC1 SILABS_DBUS_EUSART0_CTS(0x2, 0x1)
372 0 : #define EUSART0_CTS_PC2 SILABS_DBUS_EUSART0_CTS(0x2, 0x2)
373 0 : #define EUSART0_CTS_PC3 SILABS_DBUS_EUSART0_CTS(0x2, 0x3)
374 0 : #define EUSART0_CTS_PC4 SILABS_DBUS_EUSART0_CTS(0x2, 0x4)
375 0 : #define EUSART0_CTS_PC5 SILABS_DBUS_EUSART0_CTS(0x2, 0x5)
376 0 : #define EUSART0_CTS_PC6 SILABS_DBUS_EUSART0_CTS(0x2, 0x6)
377 0 : #define EUSART0_CTS_PC7 SILABS_DBUS_EUSART0_CTS(0x2, 0x7)
378 0 : #define EUSART0_CTS_PD0 SILABS_DBUS_EUSART0_CTS(0x3, 0x0)
379 0 : #define EUSART0_CTS_PD1 SILABS_DBUS_EUSART0_CTS(0x3, 0x1)
380 0 : #define EUSART0_CTS_PD2 SILABS_DBUS_EUSART0_CTS(0x3, 0x2)
381 0 : #define EUSART0_CTS_PD3 SILABS_DBUS_EUSART0_CTS(0x3, 0x3)
382 :
383 0 : #define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0)
384 0 : #define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1)
385 0 : #define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2)
386 0 : #define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3)
387 0 : #define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4)
388 0 : #define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5)
389 0 : #define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6)
390 0 : #define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7)
391 0 : #define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8)
392 0 : #define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0)
393 0 : #define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1)
394 0 : #define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2)
395 0 : #define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3)
396 0 : #define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4)
397 0 : #define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0)
398 0 : #define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1)
399 0 : #define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2)
400 0 : #define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3)
401 0 : #define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4)
402 0 : #define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5)
403 0 : #define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6)
404 0 : #define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7)
405 0 : #define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0)
406 0 : #define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1)
407 0 : #define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2)
408 0 : #define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3)
409 0 : #define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0)
410 0 : #define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1)
411 0 : #define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2)
412 0 : #define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3)
413 0 : #define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4)
414 0 : #define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5)
415 0 : #define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6)
416 0 : #define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7)
417 0 : #define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8)
418 0 : #define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0)
419 0 : #define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1)
420 0 : #define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2)
421 0 : #define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3)
422 0 : #define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4)
423 0 : #define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0)
424 0 : #define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1)
425 0 : #define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2)
426 0 : #define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3)
427 0 : #define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4)
428 0 : #define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5)
429 0 : #define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6)
430 0 : #define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7)
431 0 : #define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0)
432 0 : #define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1)
433 0 : #define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2)
434 0 : #define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3)
435 0 : #define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0)
436 0 : #define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1)
437 0 : #define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2)
438 0 : #define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3)
439 0 : #define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4)
440 0 : #define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5)
441 0 : #define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6)
442 0 : #define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7)
443 0 : #define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8)
444 0 : #define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0)
445 0 : #define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1)
446 0 : #define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2)
447 0 : #define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3)
448 0 : #define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4)
449 0 : #define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0)
450 0 : #define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1)
451 0 : #define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2)
452 0 : #define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3)
453 0 : #define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4)
454 0 : #define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5)
455 0 : #define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6)
456 0 : #define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7)
457 0 : #define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0)
458 0 : #define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1)
459 0 : #define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2)
460 0 : #define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3)
461 0 : #define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0)
462 0 : #define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1)
463 0 : #define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2)
464 0 : #define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3)
465 0 : #define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4)
466 0 : #define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5)
467 0 : #define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6)
468 0 : #define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7)
469 0 : #define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8)
470 0 : #define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0)
471 0 : #define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1)
472 0 : #define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2)
473 0 : #define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3)
474 0 : #define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4)
475 0 : #define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0)
476 0 : #define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1)
477 0 : #define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2)
478 0 : #define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3)
479 0 : #define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4)
480 0 : #define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5)
481 0 : #define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6)
482 0 : #define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7)
483 0 : #define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0)
484 0 : #define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1)
485 0 : #define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2)
486 0 : #define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3)
487 0 : #define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0)
488 0 : #define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1)
489 0 : #define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2)
490 0 : #define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3)
491 0 : #define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4)
492 0 : #define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5)
493 0 : #define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6)
494 0 : #define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7)
495 0 : #define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8)
496 0 : #define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0)
497 0 : #define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1)
498 0 : #define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2)
499 0 : #define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3)
500 0 : #define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4)
501 0 : #define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0)
502 0 : #define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1)
503 0 : #define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2)
504 0 : #define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3)
505 0 : #define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4)
506 0 : #define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5)
507 0 : #define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6)
508 0 : #define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7)
509 0 : #define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0)
510 0 : #define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1)
511 0 : #define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2)
512 0 : #define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3)
513 0 : #define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0)
514 0 : #define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1)
515 0 : #define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2)
516 0 : #define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3)
517 0 : #define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4)
518 0 : #define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5)
519 0 : #define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6)
520 0 : #define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7)
521 0 : #define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8)
522 0 : #define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0)
523 0 : #define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1)
524 0 : #define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2)
525 0 : #define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3)
526 0 : #define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4)
527 0 : #define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0)
528 0 : #define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1)
529 0 : #define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2)
530 0 : #define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3)
531 0 : #define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4)
532 0 : #define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5)
533 0 : #define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6)
534 0 : #define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7)
535 0 : #define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0)
536 0 : #define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1)
537 0 : #define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2)
538 0 : #define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3)
539 :
540 0 : #define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0)
541 0 : #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
542 0 : #define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2)
543 0 : #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
544 0 : #define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4)
545 0 : #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
546 0 : #define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6)
547 0 : #define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7)
548 0 : #define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0)
549 0 : #define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1)
550 0 : #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
551 0 : #define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3)
552 0 : #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
553 0 : #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
554 0 : #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
555 0 : #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
556 0 : #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
557 0 : #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
558 0 : #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
559 0 : #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
560 0 : #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
561 0 : #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
562 0 : #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
563 0 : #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
564 0 : #define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0)
565 0 : #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
566 0 : #define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2)
567 0 : #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
568 0 : #define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4)
569 0 : #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
570 0 : #define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6)
571 0 : #define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7)
572 0 : #define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0)
573 0 : #define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1)
574 0 : #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
575 0 : #define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3)
576 :
577 0 : #define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
578 0 : #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
579 0 : #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
580 0 : #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
581 0 : #define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
582 0 : #define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
583 0 : #define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
584 0 : #define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
585 0 : #define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
586 0 : #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
587 0 : #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
588 0 : #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
589 0 : #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
590 0 : #define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
591 0 : #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
592 0 : #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
593 0 : #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
594 0 : #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
595 0 : #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
596 0 : #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
597 0 : #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
598 0 : #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
599 0 : #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
600 0 : #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
601 0 : #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
602 0 : #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
603 0 : #define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
604 0 : #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
605 0 : #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
606 0 : #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
607 0 : #define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
608 0 : #define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
609 0 : #define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
610 0 : #define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
611 0 : #define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
612 0 : #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
613 0 : #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
614 0 : #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
615 0 : #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
616 0 : #define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
617 0 : #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
618 0 : #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
619 0 : #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
620 0 : #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
621 0 : #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
622 0 : #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
623 0 : #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
624 0 : #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
625 0 : #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
626 0 : #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
627 0 : #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
628 0 : #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
629 :
630 0 : #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
631 0 : #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
632 0 : #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
633 0 : #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
634 0 : #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
635 0 : #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
636 0 : #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
637 0 : #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
638 0 : #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
639 0 : #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
640 0 : #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
641 0 : #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
642 0 : #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
643 0 : #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
644 0 : #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
645 0 : #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
646 0 : #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
647 0 : #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
648 0 : #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
649 0 : #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
650 0 : #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
651 0 : #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
652 0 : #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
653 0 : #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
654 :
655 0 : #define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
656 0 : #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
657 0 : #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
658 0 : #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
659 0 : #define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
660 0 : #define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
661 0 : #define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
662 0 : #define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
663 0 : #define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
664 0 : #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
665 0 : #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
666 0 : #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
667 0 : #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
668 0 : #define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
669 0 : #define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
670 0 : #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
671 0 : #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
672 0 : #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
673 0 : #define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
674 0 : #define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
675 0 : #define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
676 0 : #define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
677 0 : #define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
678 0 : #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
679 0 : #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
680 0 : #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
681 0 : #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
682 0 : #define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
683 :
684 0 : #define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
685 0 : #define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
686 0 : #define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
687 0 : #define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
688 0 : #define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
689 0 : #define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
690 0 : #define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
691 0 : #define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
692 0 : #define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
693 0 : #define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
694 0 : #define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
695 0 : #define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
696 0 : #define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
697 0 : #define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
698 0 : #define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
699 0 : #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
700 0 : #define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
701 0 : #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
702 0 : #define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
703 0 : #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
704 0 : #define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
705 0 : #define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
706 0 : #define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
707 0 : #define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
708 0 : #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
709 0 : #define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
710 0 : #define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
711 0 : #define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
712 0 : #define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
713 0 : #define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
714 0 : #define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
715 0 : #define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
716 0 : #define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
717 0 : #define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
718 0 : #define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
719 0 : #define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
720 0 : #define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
721 0 : #define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
722 0 : #define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
723 0 : #define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
724 0 : #define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
725 0 : #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
726 0 : #define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
727 0 : #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
728 0 : #define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
729 0 : #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
730 0 : #define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
731 0 : #define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
732 0 : #define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
733 0 : #define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
734 0 : #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
735 0 : #define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
736 0 : #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
737 0 : #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
738 0 : #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
739 0 : #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
740 0 : #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
741 0 : #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
742 0 : #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
743 0 : #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
744 0 : #define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
745 0 : #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
746 0 : #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
747 0 : #define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
748 0 : #define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
749 0 : #define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
750 0 : #define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
751 0 : #define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
752 0 : #define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
753 0 : #define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
754 0 : #define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
755 0 : #define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
756 0 : #define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
757 0 : #define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
758 0 : #define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
759 0 : #define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
760 0 : #define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
761 0 : #define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
762 0 : #define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
763 0 : #define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
764 0 : #define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
765 0 : #define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
766 0 : #define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
767 0 : #define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
768 0 : #define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
769 0 : #define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
770 0 : #define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
771 0 : #define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
772 0 : #define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
773 0 : #define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
774 0 : #define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
775 0 : #define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
776 0 : #define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
777 0 : #define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
778 0 : #define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
779 0 : #define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
780 0 : #define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
781 0 : #define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
782 0 : #define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
783 0 : #define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
784 0 : #define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
785 0 : #define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
786 0 : #define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
787 0 : #define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
788 0 : #define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
789 0 : #define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
790 0 : #define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
791 0 : #define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
792 0 : #define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
793 0 : #define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
794 0 : #define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
795 0 : #define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
796 0 : #define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
797 0 : #define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
798 0 : #define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
799 0 : #define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
800 0 : #define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
801 0 : #define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
802 0 : #define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
803 0 : #define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
804 0 : #define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
805 0 : #define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
806 0 : #define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
807 0 : #define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
808 0 : #define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
809 0 : #define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
810 0 : #define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
811 0 : #define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
812 0 : #define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
813 0 : #define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
814 0 : #define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
815 0 : #define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
816 0 : #define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
817 0 : #define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
818 0 : #define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
819 0 : #define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
820 0 : #define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
821 0 : #define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
822 0 : #define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
823 0 : #define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
824 0 : #define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
825 0 : #define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
826 0 : #define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
827 0 : #define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
828 0 : #define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
829 0 : #define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
830 0 : #define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
831 0 : #define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
832 0 : #define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
833 0 : #define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
834 0 : #define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
835 0 : #define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
836 0 : #define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
837 0 : #define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
838 0 : #define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
839 0 : #define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
840 0 : #define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
841 0 : #define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
842 0 : #define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
843 0 : #define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
844 0 : #define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
845 0 : #define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
846 0 : #define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
847 0 : #define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
848 0 : #define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
849 0 : #define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
850 0 : #define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
851 0 : #define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
852 0 : #define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
853 0 : #define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
854 0 : #define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
855 0 : #define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
856 0 : #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
857 0 : #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
858 0 : #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
859 0 : #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
860 0 : #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
861 0 : #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
862 0 : #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
863 0 : #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
864 0 : #define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
865 0 : #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
866 0 : #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
867 0 : #define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
868 0 : #define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
869 0 : #define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
870 0 : #define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
871 0 : #define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
872 0 : #define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
873 0 : #define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
874 0 : #define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
875 0 : #define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
876 0 : #define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
877 0 : #define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
878 0 : #define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
879 0 : #define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
880 0 : #define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
881 0 : #define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
882 0 : #define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
883 0 : #define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
884 0 : #define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
885 0 : #define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
886 0 : #define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
887 0 : #define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
888 0 : #define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
889 0 : #define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
890 0 : #define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
891 0 : #define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
892 0 : #define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
893 0 : #define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
894 0 : #define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
895 0 : #define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
896 0 : #define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0)
897 0 : #define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1)
898 0 : #define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2)
899 0 : #define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3)
900 0 : #define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4)
901 0 : #define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5)
902 0 : #define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6)
903 0 : #define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7)
904 0 : #define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8)
905 0 : #define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0)
906 0 : #define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1)
907 0 : #define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2)
908 0 : #define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3)
909 0 : #define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4)
910 :
911 0 : #define PDM_CLK_PA0 SILABS_DBUS_PDM_CLK(0x0, 0x0)
912 0 : #define PDM_CLK_PA1 SILABS_DBUS_PDM_CLK(0x0, 0x1)
913 0 : #define PDM_CLK_PA2 SILABS_DBUS_PDM_CLK(0x0, 0x2)
914 0 : #define PDM_CLK_PA3 SILABS_DBUS_PDM_CLK(0x0, 0x3)
915 0 : #define PDM_CLK_PA4 SILABS_DBUS_PDM_CLK(0x0, 0x4)
916 0 : #define PDM_CLK_PA5 SILABS_DBUS_PDM_CLK(0x0, 0x5)
917 0 : #define PDM_CLK_PA6 SILABS_DBUS_PDM_CLK(0x0, 0x6)
918 0 : #define PDM_CLK_PA7 SILABS_DBUS_PDM_CLK(0x0, 0x7)
919 0 : #define PDM_CLK_PA8 SILABS_DBUS_PDM_CLK(0x0, 0x8)
920 0 : #define PDM_CLK_PB0 SILABS_DBUS_PDM_CLK(0x1, 0x0)
921 0 : #define PDM_CLK_PB1 SILABS_DBUS_PDM_CLK(0x1, 0x1)
922 0 : #define PDM_CLK_PB2 SILABS_DBUS_PDM_CLK(0x1, 0x2)
923 0 : #define PDM_CLK_PB3 SILABS_DBUS_PDM_CLK(0x1, 0x3)
924 0 : #define PDM_CLK_PB4 SILABS_DBUS_PDM_CLK(0x1, 0x4)
925 0 : #define PDM_CLK_PC0 SILABS_DBUS_PDM_CLK(0x2, 0x0)
926 0 : #define PDM_CLK_PC1 SILABS_DBUS_PDM_CLK(0x2, 0x1)
927 0 : #define PDM_CLK_PC2 SILABS_DBUS_PDM_CLK(0x2, 0x2)
928 0 : #define PDM_CLK_PC3 SILABS_DBUS_PDM_CLK(0x2, 0x3)
929 0 : #define PDM_CLK_PC4 SILABS_DBUS_PDM_CLK(0x2, 0x4)
930 0 : #define PDM_CLK_PC5 SILABS_DBUS_PDM_CLK(0x2, 0x5)
931 0 : #define PDM_CLK_PC6 SILABS_DBUS_PDM_CLK(0x2, 0x6)
932 0 : #define PDM_CLK_PC7 SILABS_DBUS_PDM_CLK(0x2, 0x7)
933 0 : #define PDM_CLK_PD0 SILABS_DBUS_PDM_CLK(0x3, 0x0)
934 0 : #define PDM_CLK_PD1 SILABS_DBUS_PDM_CLK(0x3, 0x1)
935 0 : #define PDM_CLK_PD2 SILABS_DBUS_PDM_CLK(0x3, 0x2)
936 0 : #define PDM_CLK_PD3 SILABS_DBUS_PDM_CLK(0x3, 0x3)
937 0 : #define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0)
938 0 : #define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1)
939 0 : #define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2)
940 0 : #define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3)
941 0 : #define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4)
942 0 : #define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5)
943 0 : #define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6)
944 0 : #define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7)
945 0 : #define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8)
946 0 : #define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0)
947 0 : #define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1)
948 0 : #define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2)
949 0 : #define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3)
950 0 : #define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4)
951 0 : #define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0)
952 0 : #define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1)
953 0 : #define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2)
954 0 : #define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3)
955 0 : #define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4)
956 0 : #define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5)
957 0 : #define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6)
958 0 : #define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7)
959 0 : #define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0)
960 0 : #define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1)
961 0 : #define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2)
962 0 : #define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3)
963 0 : #define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0)
964 0 : #define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1)
965 0 : #define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2)
966 0 : #define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3)
967 0 : #define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4)
968 0 : #define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5)
969 0 : #define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6)
970 0 : #define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7)
971 0 : #define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8)
972 0 : #define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0)
973 0 : #define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1)
974 0 : #define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2)
975 0 : #define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3)
976 0 : #define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4)
977 0 : #define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0)
978 0 : #define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1)
979 0 : #define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2)
980 0 : #define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3)
981 0 : #define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4)
982 0 : #define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5)
983 0 : #define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6)
984 0 : #define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7)
985 0 : #define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0)
986 0 : #define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1)
987 0 : #define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2)
988 0 : #define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3)
989 :
990 0 : #define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
991 0 : #define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
992 0 : #define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
993 0 : #define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
994 0 : #define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
995 0 : #define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
996 0 : #define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
997 0 : #define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
998 0 : #define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
999 0 : #define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
1000 0 : #define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
1001 0 : #define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
1002 0 : #define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
1003 0 : #define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
1004 0 : #define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
1005 0 : #define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
1006 0 : #define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
1007 0 : #define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
1008 0 : #define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
1009 0 : #define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
1010 0 : #define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
1011 0 : #define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
1012 0 : #define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
1013 0 : #define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
1014 0 : #define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
1015 0 : #define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
1016 0 : #define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
1017 0 : #define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
1018 0 : #define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
1019 0 : #define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
1020 0 : #define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
1021 0 : #define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
1022 0 : #define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
1023 0 : #define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
1024 0 : #define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
1025 0 : #define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
1026 0 : #define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
1027 0 : #define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
1028 0 : #define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
1029 0 : #define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
1030 0 : #define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
1031 0 : #define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
1032 0 : #define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
1033 0 : #define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
1034 0 : #define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
1035 0 : #define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
1036 0 : #define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
1037 0 : #define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
1038 0 : #define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
1039 0 : #define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
1040 0 : #define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
1041 0 : #define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
1042 0 : #define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
1043 0 : #define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
1044 0 : #define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
1045 0 : #define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
1046 0 : #define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
1047 0 : #define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
1048 0 : #define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
1049 0 : #define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
1050 0 : #define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
1051 0 : #define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
1052 0 : #define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
1053 0 : #define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
1054 0 : #define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
1055 0 : #define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
1056 0 : #define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
1057 0 : #define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
1058 0 : #define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
1059 0 : #define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
1060 0 : #define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
1061 0 : #define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
1062 0 : #define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
1063 0 : #define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
1064 0 : #define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
1065 0 : #define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
1066 0 : #define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
1067 0 : #define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
1068 0 : #define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
1069 0 : #define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
1070 0 : #define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
1071 0 : #define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
1072 0 : #define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
1073 0 : #define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
1074 0 : #define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
1075 0 : #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
1076 0 : #define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
1077 0 : #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
1078 0 : #define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
1079 0 : #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
1080 0 : #define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
1081 0 : #define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
1082 0 : #define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
1083 0 : #define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
1084 0 : #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
1085 0 : #define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
1086 0 : #define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
1087 0 : #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
1088 0 : #define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
1089 0 : #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
1090 0 : #define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
1091 0 : #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
1092 0 : #define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
1093 0 : #define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
1094 0 : #define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
1095 0 : #define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
1096 0 : #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
1097 0 : #define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
1098 0 : #define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
1099 0 : #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
1100 0 : #define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
1101 0 : #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
1102 0 : #define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
1103 0 : #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
1104 0 : #define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
1105 0 : #define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
1106 0 : #define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
1107 0 : #define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
1108 0 : #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
1109 0 : #define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
1110 0 : #define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
1111 0 : #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
1112 0 : #define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
1113 0 : #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
1114 0 : #define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
1115 0 : #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
1116 0 : #define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
1117 0 : #define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
1118 0 : #define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
1119 0 : #define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
1120 0 : #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
1121 0 : #define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
1122 0 : #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
1123 0 : #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
1124 0 : #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
1125 0 : #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
1126 0 : #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
1127 0 : #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
1128 0 : #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
1129 0 : #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
1130 0 : #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
1131 0 : #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
1132 0 : #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
1133 0 : #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
1134 0 : #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
1135 0 : #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
1136 0 : #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
1137 0 : #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
1138 0 : #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
1139 0 : #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
1140 0 : #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
1141 0 : #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
1142 0 : #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
1143 0 : #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
1144 0 : #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
1145 0 : #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
1146 0 : #define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
1147 0 : #define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
1148 0 : #define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
1149 0 : #define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
1150 0 : #define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
1151 0 : #define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
1152 0 : #define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
1153 0 : #define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
1154 0 : #define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
1155 0 : #define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
1156 0 : #define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
1157 0 : #define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
1158 0 : #define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
1159 0 : #define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
1160 0 : #define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
1161 0 : #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
1162 0 : #define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
1163 0 : #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
1164 0 : #define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
1165 0 : #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
1166 0 : #define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
1167 0 : #define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
1168 0 : #define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
1169 0 : #define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
1170 0 : #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
1171 0 : #define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
1172 0 : #define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
1173 0 : #define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
1174 0 : #define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
1175 0 : #define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
1176 0 : #define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
1177 0 : #define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
1178 0 : #define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
1179 0 : #define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
1180 0 : #define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
1181 0 : #define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
1182 0 : #define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
1183 0 : #define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
1184 0 : #define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
1185 0 : #define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
1186 0 : #define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
1187 0 : #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
1188 0 : #define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
1189 0 : #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
1190 0 : #define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
1191 0 : #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
1192 0 : #define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
1193 0 : #define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
1194 0 : #define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
1195 0 : #define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
1196 0 : #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
1197 0 : #define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
1198 0 : #define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
1199 0 : #define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
1200 0 : #define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
1201 0 : #define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
1202 0 : #define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
1203 0 : #define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
1204 0 : #define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
1205 0 : #define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
1206 0 : #define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
1207 0 : #define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
1208 0 : #define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
1209 0 : #define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
1210 0 : #define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
1211 0 : #define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
1212 0 : #define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
1213 0 : #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
1214 0 : #define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
1215 0 : #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
1216 0 : #define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
1217 0 : #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
1218 0 : #define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
1219 0 : #define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
1220 0 : #define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
1221 0 : #define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
1222 0 : #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
1223 0 : #define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
1224 0 : #define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
1225 0 : #define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
1226 0 : #define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
1227 0 : #define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
1228 0 : #define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
1229 0 : #define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
1230 0 : #define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
1231 0 : #define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
1232 0 : #define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
1233 0 : #define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
1234 0 : #define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
1235 0 : #define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
1236 0 : #define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
1237 0 : #define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
1238 0 : #define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
1239 0 : #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
1240 0 : #define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
1241 0 : #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
1242 0 : #define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
1243 0 : #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
1244 0 : #define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
1245 0 : #define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
1246 0 : #define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
1247 0 : #define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
1248 0 : #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
1249 0 : #define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
1250 :
1251 0 : #define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
1252 0 : #define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
1253 0 : #define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
1254 0 : #define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
1255 0 : #define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
1256 0 : #define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
1257 0 : #define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
1258 0 : #define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
1259 0 : #define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
1260 0 : #define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
1261 0 : #define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
1262 0 : #define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
1263 0 : #define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
1264 0 : #define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
1265 0 : #define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
1266 0 : #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
1267 0 : #define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
1268 0 : #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
1269 0 : #define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
1270 0 : #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
1271 0 : #define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
1272 0 : #define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
1273 0 : #define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
1274 0 : #define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
1275 0 : #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
1276 0 : #define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
1277 0 : #define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
1278 0 : #define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
1279 0 : #define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
1280 0 : #define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
1281 0 : #define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
1282 0 : #define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
1283 0 : #define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
1284 0 : #define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
1285 0 : #define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
1286 0 : #define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
1287 0 : #define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
1288 0 : #define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
1289 0 : #define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
1290 0 : #define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
1291 0 : #define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
1292 0 : #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
1293 0 : #define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
1294 0 : #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
1295 0 : #define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
1296 0 : #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
1297 0 : #define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
1298 0 : #define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
1299 0 : #define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
1300 0 : #define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
1301 0 : #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
1302 0 : #define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
1303 0 : #define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
1304 0 : #define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
1305 0 : #define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
1306 0 : #define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
1307 0 : #define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
1308 0 : #define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
1309 0 : #define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
1310 0 : #define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
1311 0 : #define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
1312 0 : #define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
1313 0 : #define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
1314 0 : #define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
1315 0 : #define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
1316 0 : #define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
1317 0 : #define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
1318 0 : #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
1319 0 : #define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
1320 0 : #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
1321 0 : #define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
1322 0 : #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
1323 0 : #define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
1324 0 : #define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
1325 0 : #define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
1326 0 : #define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
1327 0 : #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
1328 0 : #define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
1329 0 : #define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
1330 0 : #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
1331 0 : #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
1332 0 : #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
1333 0 : #define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
1334 0 : #define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
1335 0 : #define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
1336 0 : #define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
1337 0 : #define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
1338 0 : #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
1339 0 : #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
1340 0 : #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
1341 0 : #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
1342 0 : #define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
1343 0 : #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
1344 0 : #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
1345 0 : #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
1346 0 : #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
1347 0 : #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
1348 0 : #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
1349 0 : #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
1350 0 : #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
1351 0 : #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
1352 0 : #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
1353 0 : #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
1354 0 : #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
1355 0 : #define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
1356 0 : #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
1357 0 : #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
1358 0 : #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
1359 0 : #define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
1360 0 : #define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
1361 0 : #define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
1362 0 : #define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
1363 0 : #define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
1364 0 : #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
1365 0 : #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
1366 0 : #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
1367 0 : #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
1368 0 : #define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
1369 0 : #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
1370 0 : #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
1371 0 : #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
1372 0 : #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
1373 0 : #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
1374 0 : #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
1375 0 : #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
1376 0 : #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
1377 0 : #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
1378 0 : #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
1379 0 : #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
1380 0 : #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
1381 0 : #define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
1382 0 : #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
1383 0 : #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
1384 0 : #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
1385 0 : #define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
1386 0 : #define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
1387 0 : #define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
1388 0 : #define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
1389 0 : #define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
1390 0 : #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
1391 0 : #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
1392 0 : #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
1393 0 : #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
1394 0 : #define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
1395 0 : #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
1396 0 : #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
1397 0 : #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
1398 0 : #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
1399 0 : #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
1400 0 : #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
1401 0 : #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
1402 0 : #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
1403 0 : #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
1404 0 : #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
1405 0 : #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
1406 0 : #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
1407 :
1408 0 : #define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
1409 0 : #define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
1410 0 : #define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
1411 0 : #define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
1412 0 : #define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
1413 0 : #define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
1414 0 : #define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
1415 0 : #define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
1416 0 : #define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
1417 0 : #define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
1418 0 : #define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
1419 0 : #define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
1420 0 : #define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
1421 0 : #define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
1422 0 : #define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
1423 0 : #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
1424 0 : #define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
1425 0 : #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
1426 0 : #define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
1427 0 : #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
1428 0 : #define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
1429 0 : #define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
1430 0 : #define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
1431 0 : #define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
1432 0 : #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
1433 0 : #define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
1434 0 : #define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
1435 0 : #define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
1436 0 : #define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
1437 0 : #define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
1438 0 : #define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
1439 0 : #define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
1440 0 : #define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
1441 0 : #define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
1442 0 : #define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
1443 0 : #define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
1444 0 : #define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
1445 0 : #define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
1446 0 : #define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
1447 0 : #define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
1448 0 : #define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
1449 0 : #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
1450 0 : #define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
1451 0 : #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
1452 0 : #define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
1453 0 : #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
1454 0 : #define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
1455 0 : #define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
1456 0 : #define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
1457 0 : #define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
1458 0 : #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
1459 0 : #define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
1460 0 : #define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
1461 0 : #define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
1462 0 : #define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
1463 0 : #define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
1464 0 : #define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
1465 0 : #define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
1466 0 : #define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
1467 0 : #define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
1468 0 : #define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
1469 0 : #define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
1470 0 : #define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
1471 0 : #define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
1472 0 : #define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
1473 0 : #define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
1474 0 : #define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
1475 0 : #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
1476 0 : #define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
1477 0 : #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
1478 0 : #define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
1479 0 : #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
1480 0 : #define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
1481 0 : #define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
1482 0 : #define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
1483 0 : #define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
1484 0 : #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
1485 0 : #define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
1486 0 : #define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
1487 0 : #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
1488 0 : #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
1489 0 : #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
1490 0 : #define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
1491 0 : #define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
1492 0 : #define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
1493 0 : #define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
1494 0 : #define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
1495 0 : #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
1496 0 : #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
1497 0 : #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
1498 0 : #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
1499 0 : #define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
1500 0 : #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
1501 0 : #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
1502 0 : #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
1503 0 : #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
1504 0 : #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
1505 0 : #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
1506 0 : #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
1507 0 : #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
1508 0 : #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
1509 0 : #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
1510 0 : #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
1511 0 : #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
1512 0 : #define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
1513 0 : #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
1514 0 : #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
1515 0 : #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
1516 0 : #define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
1517 0 : #define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
1518 0 : #define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
1519 0 : #define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
1520 0 : #define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
1521 0 : #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
1522 0 : #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
1523 0 : #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
1524 0 : #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
1525 0 : #define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
1526 0 : #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
1527 0 : #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
1528 0 : #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
1529 0 : #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
1530 0 : #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
1531 0 : #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
1532 0 : #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
1533 0 : #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
1534 0 : #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
1535 0 : #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
1536 0 : #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
1537 0 : #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
1538 0 : #define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
1539 0 : #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
1540 0 : #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
1541 0 : #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
1542 0 : #define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
1543 0 : #define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
1544 0 : #define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
1545 0 : #define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
1546 0 : #define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
1547 0 : #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
1548 0 : #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
1549 0 : #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
1550 0 : #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
1551 0 : #define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
1552 0 : #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
1553 0 : #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
1554 0 : #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
1555 0 : #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
1556 0 : #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
1557 0 : #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
1558 0 : #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
1559 0 : #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
1560 0 : #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
1561 0 : #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
1562 0 : #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
1563 0 : #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
1564 :
1565 0 : #define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
1566 0 : #define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
1567 0 : #define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
1568 0 : #define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
1569 0 : #define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
1570 0 : #define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
1571 0 : #define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
1572 0 : #define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
1573 0 : #define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
1574 0 : #define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
1575 0 : #define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
1576 0 : #define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
1577 0 : #define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
1578 0 : #define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
1579 0 : #define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
1580 0 : #define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
1581 0 : #define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
1582 0 : #define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
1583 0 : #define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
1584 0 : #define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
1585 0 : #define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
1586 0 : #define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
1587 0 : #define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
1588 0 : #define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
1589 0 : #define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
1590 0 : #define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
1591 0 : #define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
1592 0 : #define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
1593 0 : #define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
1594 0 : #define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
1595 0 : #define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
1596 0 : #define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
1597 0 : #define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
1598 0 : #define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
1599 0 : #define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
1600 0 : #define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
1601 0 : #define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
1602 0 : #define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
1603 0 : #define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
1604 0 : #define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
1605 0 : #define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
1606 0 : #define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
1607 0 : #define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
1608 0 : #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
1609 0 : #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
1610 0 : #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
1611 0 : #define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
1612 0 : #define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
1613 0 : #define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
1614 0 : #define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
1615 0 : #define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
1616 0 : #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
1617 0 : #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
1618 0 : #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
1619 0 : #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
1620 0 : #define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
1621 0 : #define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
1622 0 : #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
1623 0 : #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
1624 0 : #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
1625 0 : #define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
1626 0 : #define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
1627 0 : #define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
1628 0 : #define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
1629 0 : #define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
1630 0 : #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
1631 0 : #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
1632 0 : #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
1633 0 : #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
1634 0 : #define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
1635 0 : #define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
1636 0 : #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
1637 0 : #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
1638 0 : #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
1639 0 : #define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
1640 0 : #define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
1641 0 : #define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
1642 0 : #define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
1643 0 : #define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
1644 0 : #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
1645 0 : #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
1646 0 : #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
1647 0 : #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
1648 0 : #define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
1649 :
1650 0 : #define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
1651 0 : #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
1652 0 : #define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
1653 0 : #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
1654 0 : #define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
1655 0 : #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
1656 0 : #define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
1657 0 : #define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
1658 0 : #define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
1659 0 : #define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
1660 0 : #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
1661 0 : #define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
1662 0 : #define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
1663 0 : #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
1664 0 : #define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
1665 0 : #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
1666 0 : #define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
1667 0 : #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
1668 0 : #define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
1669 0 : #define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
1670 0 : #define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
1671 0 : #define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
1672 0 : #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
1673 0 : #define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
1674 0 : #define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
1675 0 : #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
1676 0 : #define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
1677 0 : #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
1678 0 : #define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
1679 0 : #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
1680 0 : #define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
1681 0 : #define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
1682 0 : #define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
1683 0 : #define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
1684 0 : #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
1685 0 : #define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
1686 0 : #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
1687 0 : #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
1688 0 : #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
1689 0 : #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
1690 0 : #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
1691 0 : #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
1692 0 : #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
1693 0 : #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
1694 0 : #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
1695 0 : #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
1696 0 : #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
1697 0 : #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
1698 0 : #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
1699 0 : #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
1700 0 : #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
1701 0 : #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
1702 0 : #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
1703 0 : #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
1704 0 : #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
1705 0 : #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
1706 0 : #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
1707 0 : #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
1708 0 : #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
1709 0 : #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
1710 0 : #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
1711 0 : #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
1712 0 : #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
1713 0 : #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
1714 0 : #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
1715 0 : #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
1716 0 : #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
1717 0 : #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
1718 0 : #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
1719 0 : #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
1720 0 : #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
1721 0 : #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
1722 :
1723 0 : #define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
1724 0 : #define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
1725 0 : #define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
1726 0 : #define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
1727 0 : #define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
1728 0 : #define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
1729 0 : #define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
1730 0 : #define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
1731 0 : #define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
1732 0 : #define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
1733 0 : #define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
1734 0 : #define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
1735 0 : #define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
1736 0 : #define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
1737 0 : #define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
1738 0 : #define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
1739 0 : #define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
1740 0 : #define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
1741 0 : #define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
1742 0 : #define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
1743 0 : #define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
1744 0 : #define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
1745 0 : #define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
1746 0 : #define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
1747 0 : #define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
1748 0 : #define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
1749 0 : #define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
1750 0 : #define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
1751 0 : #define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
1752 0 : #define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
1753 0 : #define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
1754 0 : #define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
1755 0 : #define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
1756 0 : #define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
1757 0 : #define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
1758 0 : #define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
1759 0 : #define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
1760 0 : #define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
1761 0 : #define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
1762 0 : #define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
1763 0 : #define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
1764 0 : #define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
1765 0 : #define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
1766 0 : #define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
1767 0 : #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
1768 0 : #define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
1769 0 : #define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
1770 0 : #define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
1771 0 : #define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
1772 0 : #define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
1773 0 : #define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
1774 0 : #define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
1775 0 : #define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
1776 0 : #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
1777 0 : #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
1778 0 : #define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
1779 0 : #define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
1780 0 : #define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
1781 0 : #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
1782 0 : #define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
1783 0 : #define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
1784 0 : #define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
1785 0 : #define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
1786 0 : #define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
1787 0 : #define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
1788 0 : #define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
1789 0 : #define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
1790 0 : #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
1791 0 : #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
1792 0 : #define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
1793 0 : #define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
1794 0 : #define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
1795 0 : #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
1796 0 : #define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
1797 0 : #define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
1798 0 : #define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
1799 0 : #define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
1800 0 : #define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
1801 0 : #define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
1802 0 : #define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
1803 0 : #define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
1804 0 : #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
1805 0 : #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
1806 0 : #define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
1807 :
1808 0 : #define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0)
1809 0 : #define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1)
1810 0 : #define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2)
1811 0 : #define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3)
1812 0 : #define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4)
1813 0 : #define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5)
1814 0 : #define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6)
1815 0 : #define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7)
1816 0 : #define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8)
1817 0 : #define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0)
1818 0 : #define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1)
1819 0 : #define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2)
1820 0 : #define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3)
1821 0 : #define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4)
1822 0 : #define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0)
1823 0 : #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
1824 0 : #define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2)
1825 0 : #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
1826 0 : #define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4)
1827 0 : #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
1828 0 : #define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6)
1829 0 : #define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7)
1830 0 : #define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0)
1831 0 : #define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1)
1832 0 : #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
1833 0 : #define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3)
1834 0 : #define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
1835 0 : #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
1836 0 : #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
1837 0 : #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
1838 0 : #define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
1839 0 : #define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
1840 0 : #define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
1841 0 : #define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
1842 0 : #define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
1843 0 : #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
1844 0 : #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
1845 0 : #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
1846 0 : #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
1847 0 : #define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
1848 0 : #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
1849 0 : #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
1850 0 : #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
1851 0 : #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
1852 0 : #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
1853 0 : #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
1854 0 : #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
1855 0 : #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
1856 0 : #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
1857 0 : #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
1858 0 : #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
1859 0 : #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
1860 0 : #define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0)
1861 0 : #define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1)
1862 0 : #define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2)
1863 0 : #define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3)
1864 0 : #define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4)
1865 0 : #define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5)
1866 0 : #define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6)
1867 0 : #define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7)
1868 0 : #define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8)
1869 0 : #define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0)
1870 0 : #define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1)
1871 0 : #define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2)
1872 0 : #define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3)
1873 0 : #define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4)
1874 0 : #define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0)
1875 0 : #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
1876 0 : #define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2)
1877 0 : #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
1878 0 : #define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4)
1879 0 : #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
1880 0 : #define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6)
1881 0 : #define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7)
1882 0 : #define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0)
1883 0 : #define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1)
1884 0 : #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
1885 0 : #define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3)
1886 0 : #define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
1887 0 : #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
1888 0 : #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
1889 0 : #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
1890 0 : #define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
1891 0 : #define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
1892 0 : #define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
1893 0 : #define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
1894 0 : #define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
1895 0 : #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
1896 0 : #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
1897 0 : #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
1898 0 : #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
1899 0 : #define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
1900 0 : #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
1901 0 : #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
1902 0 : #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
1903 0 : #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
1904 0 : #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
1905 0 : #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
1906 0 : #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
1907 0 : #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
1908 0 : #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
1909 0 : #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
1910 0 : #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
1911 0 : #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
1912 0 : #define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0)
1913 0 : #define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1)
1914 0 : #define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2)
1915 0 : #define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3)
1916 0 : #define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4)
1917 0 : #define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5)
1918 0 : #define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6)
1919 0 : #define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7)
1920 0 : #define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8)
1921 0 : #define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0)
1922 0 : #define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1)
1923 0 : #define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2)
1924 0 : #define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3)
1925 0 : #define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4)
1926 0 : #define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0)
1927 0 : #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
1928 0 : #define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2)
1929 0 : #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
1930 0 : #define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4)
1931 0 : #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
1932 0 : #define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6)
1933 0 : #define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7)
1934 0 : #define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0)
1935 0 : #define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1)
1936 0 : #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
1937 0 : #define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3)
1938 0 : #define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
1939 0 : #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
1940 0 : #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
1941 0 : #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
1942 0 : #define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
1943 0 : #define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
1944 0 : #define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
1945 0 : #define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
1946 0 : #define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
1947 0 : #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
1948 0 : #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
1949 0 : #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
1950 0 : #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
1951 0 : #define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
1952 0 : #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
1953 0 : #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
1954 0 : #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
1955 0 : #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
1956 0 : #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
1957 0 : #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
1958 0 : #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
1959 0 : #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
1960 0 : #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
1961 0 : #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
1962 0 : #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
1963 0 : #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
1964 :
1965 0 : #define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0)
1966 0 : #define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1)
1967 0 : #define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2)
1968 0 : #define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3)
1969 0 : #define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4)
1970 0 : #define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5)
1971 0 : #define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6)
1972 0 : #define USART1_CS_PA7 SILABS_DBUS_USART1_CS(0x0, 0x7)
1973 0 : #define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8)
1974 0 : #define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0)
1975 0 : #define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1)
1976 0 : #define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2)
1977 0 : #define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3)
1978 0 : #define USART1_CS_PB4 SILABS_DBUS_USART1_CS(0x1, 0x4)
1979 0 : #define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0)
1980 0 : #define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1)
1981 0 : #define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2)
1982 0 : #define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3)
1983 0 : #define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4)
1984 0 : #define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5)
1985 0 : #define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
1986 0 : #define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7)
1987 0 : #define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8)
1988 0 : #define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0)
1989 0 : #define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1)
1990 0 : #define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2)
1991 0 : #define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3)
1992 0 : #define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4)
1993 0 : #define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0)
1994 0 : #define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1)
1995 0 : #define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2)
1996 0 : #define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3)
1997 0 : #define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4)
1998 0 : #define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5)
1999 0 : #define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6)
2000 0 : #define USART1_RX_PA7 SILABS_DBUS_USART1_RX(0x0, 0x7)
2001 0 : #define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8)
2002 0 : #define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0)
2003 0 : #define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1)
2004 0 : #define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2)
2005 0 : #define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3)
2006 0 : #define USART1_RX_PB4 SILABS_DBUS_USART1_RX(0x1, 0x4)
2007 0 : #define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0)
2008 0 : #define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1)
2009 0 : #define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2)
2010 0 : #define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3)
2011 0 : #define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4)
2012 0 : #define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5)
2013 0 : #define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
2014 0 : #define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7)
2015 0 : #define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8)
2016 0 : #define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0)
2017 0 : #define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1)
2018 0 : #define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2)
2019 0 : #define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3)
2020 0 : #define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4)
2021 0 : #define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0)
2022 0 : #define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1)
2023 0 : #define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2)
2024 0 : #define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3)
2025 0 : #define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4)
2026 0 : #define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5)
2027 0 : #define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6)
2028 0 : #define USART1_TX_PA7 SILABS_DBUS_USART1_TX(0x0, 0x7)
2029 0 : #define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8)
2030 0 : #define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0)
2031 0 : #define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1)
2032 0 : #define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2)
2033 0 : #define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3)
2034 0 : #define USART1_TX_PB4 SILABS_DBUS_USART1_TX(0x1, 0x4)
2035 0 : #define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0)
2036 0 : #define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1)
2037 0 : #define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2)
2038 0 : #define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3)
2039 0 : #define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4)
2040 0 : #define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5)
2041 0 : #define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)
2042 0 : #define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7)
2043 0 : #define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8)
2044 0 : #define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0)
2045 0 : #define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1)
2046 0 : #define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2)
2047 0 : #define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
2048 0 : #define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)
2049 :
2050 0 : #define ABUS_AEVEN0_IADC0 SILABS_ABUS(0x0, 0x0, 0x1)
2051 0 : #define ABUS_AEVEN0_ACMP0 SILABS_ABUS(0x0, 0x0, 0x2)
2052 0 : #define ABUS_AEVEN1_IADC0 SILABS_ABUS(0x0, 0x1, 0x1)
2053 0 : #define ABUS_AEVEN1_ACMP0 SILABS_ABUS(0x0, 0x1, 0x2)
2054 0 : #define ABUS_AODD0_IADC0 SILABS_ABUS(0x0, 0x2, 0x1)
2055 0 : #define ABUS_AODD0_ACMP0 SILABS_ABUS(0x0, 0x2, 0x2)
2056 0 : #define ABUS_AODD1_IADC0 SILABS_ABUS(0x0, 0x3, 0x1)
2057 0 : #define ABUS_AODD1_ACMP0 SILABS_ABUS(0x0, 0x3, 0x2)
2058 0 : #define ABUS_BEVEN0_IADC0 SILABS_ABUS(0x1, 0x0, 0x1)
2059 0 : #define ABUS_BEVEN0_ACMP0 SILABS_ABUS(0x1, 0x0, 0x2)
2060 0 : #define ABUS_BEVEN1_IADC0 SILABS_ABUS(0x1, 0x1, 0x1)
2061 0 : #define ABUS_BEVEN1_ACMP0 SILABS_ABUS(0x1, 0x1, 0x2)
2062 0 : #define ABUS_BODD0_IADC0 SILABS_ABUS(0x1, 0x2, 0x1)
2063 0 : #define ABUS_BODD0_ACMP0 SILABS_ABUS(0x1, 0x2, 0x2)
2064 0 : #define ABUS_BODD1_IADC0 SILABS_ABUS(0x1, 0x3, 0x1)
2065 0 : #define ABUS_BODD1_ACMP0 SILABS_ABUS(0x1, 0x3, 0x2)
2066 0 : #define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1)
2067 0 : #define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2)
2068 0 : #define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1)
2069 0 : #define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2)
2070 0 : #define ABUS_CDODD0_IADC0 SILABS_ABUS(0x2, 0x2, 0x1)
2071 0 : #define ABUS_CDODD0_ACMP0 SILABS_ABUS(0x2, 0x2, 0x2)
2072 0 : #define ABUS_CDODD1_IADC0 SILABS_ABUS(0x2, 0x3, 0x1)
2073 0 : #define ABUS_CDODD1_ACMP0 SILABS_ABUS(0x2, 0x3, 0x2)
2074 :
2075 : #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_ */
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